2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/thread_info.h>
33 * Endian independent macros for shifting bytes within registers.
38 #define get_byte_0 lsl #0
39 #define get_byte_1 lsr #8
40 #define get_byte_2 lsr #16
41 #define get_byte_3 lsr #24
42 #define put_byte_0 lsl #0
43 #define put_byte_1 lsl #8
44 #define put_byte_2 lsl #16
45 #define put_byte_3 lsl #24
49 #define get_byte_0 lsr #24
50 #define get_byte_1 lsr #16
51 #define get_byte_2 lsr #8
52 #define get_byte_3 lsl #0
53 #define put_byte_0 lsl #24
54 #define put_byte_1 lsl #16
55 #define put_byte_2 lsl #8
56 #define put_byte_3 lsl #0
59 /* Select code for any configuration running in BE8 mode */
60 #ifdef CONFIG_CPU_ENDIAN_BE8
61 #define ARM_BE8(code...) code
63 #define ARM_BE8(code...)
67 * Data preload for architectures that support it
69 #if __LINUX_ARM_ARCH__ >= 5
70 #define PLD(code...) code
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
82 * On Feroceon there is much to gain however, regardless of cache mode.
84 #ifdef CONFIG_CPU_FEROCEON
85 #define CALGN(code...) code
87 #define CALGN(code...)
91 * Enable and disable interrupts
93 #if __LINUX_ARM_ARCH__ >= 6
94 .macro disable_irq_notrace
98 .macro enable_irq_notrace
102 .macro disable_irq_notrace
103 msr cpsr_c, #PSR_I_BIT | SVC_MODE
106 .macro enable_irq_notrace
107 msr cpsr_c, #SVC_MODE
111 .macro asm_trace_hardirqs_off
112 #if defined(CONFIG_TRACE_IRQFLAGS)
113 stmdb sp!, {r0-r3, ip, lr}
114 bl trace_hardirqs_off
115 ldmia sp!, {r0-r3, ip, lr}
119 .macro asm_trace_hardirqs_on, cond=al
120 #if defined(CONFIG_TRACE_IRQFLAGS)
122 * actually the registers should be pushed and pop'd conditionally, but
123 * after bl the flags are certainly clobbered
125 stmdb sp!, {r0-r3, ip, lr}
126 bl\cond trace_hardirqs_on
127 ldmia sp!, {r0-r3, ip, lr}
133 asm_trace_hardirqs_off
137 asm_trace_hardirqs_on
141 * Save the current IRQ state and disable IRQs. Note that this macro
142 * assumes FIQs are enabled, and that the processor is in SVC mode.
144 .macro save_and_disable_irqs, oldcpsr
145 #ifdef CONFIG_CPU_V7M
146 mrs \oldcpsr, primask
153 .macro save_and_disable_irqs_notrace, oldcpsr
159 * Restore interrupt state previously stored in a register. We don't
160 * guarantee that this will preserve the flags.
162 .macro restore_irqs_notrace, oldcpsr
163 #ifdef CONFIG_CPU_V7M
164 msr primask, \oldcpsr
170 .macro restore_irqs, oldcpsr
171 tst \oldcpsr, #PSR_I_BIT
172 asm_trace_hardirqs_on cond=eq
173 restore_irqs_notrace \oldcpsr
177 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
178 * reference local symbols in the same assembly file which are to be
179 * resolved by the assembler. Other usage is undefined.
181 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
182 .macro badr\c, rd, sym
183 #ifdef CONFIG_THUMB2_KERNEL
192 * Get current thread_info.
194 .macro get_thread_info, rd
195 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
197 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
198 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
202 * Increment/decrement the preempt count.
204 #ifdef CONFIG_PREEMPT_COUNT
205 .macro inc_preempt_count, ti, tmp
206 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
207 add \tmp, \tmp, #1 @ increment it
208 str \tmp, [\ti, #TI_PREEMPT]
211 .macro dec_preempt_count, ti, tmp
212 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
213 sub \tmp, \tmp, #1 @ decrement it
214 str \tmp, [\ti, #TI_PREEMPT]
217 .macro dec_preempt_count_ti, ti, tmp
219 dec_preempt_count \ti, \tmp
222 .macro inc_preempt_count, ti, tmp
225 .macro dec_preempt_count, ti, tmp
228 .macro dec_preempt_count_ti, ti, tmp
234 .pushsection __ex_table,"a"; \
240 #define ALT_SMP(instr...) \
243 * Note: if you get assembler errors from ALT_UP() when building with
244 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
245 * ALT_SMP( W(instr) ... )
247 #define ALT_UP(instr...) \
248 .pushsection ".alt.smp.init", "a" ;\
251 .if . - 9997b == 2 ;\
254 .if . - 9997b != 4 ;\
255 .error "ALT_UP() content must assemble to exactly 4 bytes";\
258 #define ALT_UP_B(label) \
259 .equ up_b_offset, label - 9998b ;\
260 .pushsection ".alt.smp.init", "a" ;\
262 W(b) . + up_b_offset ;\
265 #define ALT_SMP(instr...)
266 #define ALT_UP(instr...) instr
267 #define ALT_UP_B(label) b label
271 * Instruction barrier
274 #if __LINUX_ARM_ARCH__ >= 7
276 #elif __LINUX_ARM_ARCH__ == 6
277 mcr p15, 0, r0, c7, c5, 4
282 * SMP data memory barrier
286 #if __LINUX_ARM_ARCH__ >= 7
292 #elif __LINUX_ARM_ARCH__ == 6
293 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
295 #error Incompatible SMP platform
305 #if defined(CONFIG_CPU_V7M)
307 * setmode is used to assert to be in svc mode during boot. For v7-M
308 * this is done in __v7m_setup, so setmode can be empty here.
310 .macro setmode, mode, reg
312 #elif defined(CONFIG_THUMB2_KERNEL)
313 .macro setmode, mode, reg
318 .macro setmode, mode, reg
324 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
325 * a scratch register for the macro to overwrite.
327 * This macro is intended for forcing the CPU into SVC mode at boot time.
328 * you cannot return to the original mode.
330 .macro safe_svcmode_maskall reg:req
331 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
333 eor \reg, \reg, #HYP_MODE
335 bic \reg , \reg , #MODE_MASK
336 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
337 THUMB( orr \reg , \reg , #PSR_T_BIT )
339 orr \reg, \reg, #PSR_A_BIT
348 * workaround for possibly broken pre-v6 hardware
349 * (akita, Sharp Zaurus C-1000, PXA270-based)
351 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
356 * STRT/LDRT access macros with ARM and Thumb-2 variants
358 #ifdef CONFIG_THUMB2_KERNEL
360 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
363 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
365 \instr\cond\()\t\().w \reg, [\ptr, #\off]
367 .error "Unsupported inc macro argument"
370 .pushsection __ex_table,"a"
376 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
377 @ explicit IT instruction needed because of the label
378 @ introduced by the USER macro
385 .error "Unsupported rept macro argument"
389 @ Slightly optimised to avoid incrementing the pointer twice
390 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
392 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
395 add\cond \ptr, #\rept * \inc
398 #else /* !CONFIG_THUMB2_KERNEL */
400 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
404 \instr\cond\()b\()\t \reg, [\ptr], #\inc
406 \instr\cond\()\t \reg, [\ptr], #\inc
408 .error "Unsupported inc macro argument"
411 .pushsection __ex_table,"a"
418 #endif /* CONFIG_THUMB2_KERNEL */
420 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
421 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
424 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
425 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
428 /* Utility macro for declaring string literals */
429 .macro string name:req, string
430 .type \name , #object
433 .size \name , . - \name
436 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
437 #ifndef CONFIG_CPU_USE_DOMAINS
438 adds \tmp, \addr, #\size - 1
439 sbcccs \tmp, \tmp, \limit
444 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
446 #if __LINUX_ARM_ARCH__ < 6
460 #ifdef CONFIG_THUMB2_KERNEL
465 #endif /* __ASM_ASSEMBLER_H__ */