2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/thread_info.h>
33 * Endian independent macros for shifting bytes within registers.
38 #define get_byte_0 lsl #0
39 #define get_byte_1 lsr #8
40 #define get_byte_2 lsr #16
41 #define get_byte_3 lsr #24
42 #define put_byte_0 lsl #0
43 #define put_byte_1 lsl #8
44 #define put_byte_2 lsl #16
45 #define put_byte_3 lsl #24
49 #define get_byte_0 lsr #24
50 #define get_byte_1 lsr #16
51 #define get_byte_2 lsr #8
52 #define get_byte_3 lsl #0
53 #define put_byte_0 lsl #24
54 #define put_byte_1 lsl #16
55 #define put_byte_2 lsl #8
56 #define put_byte_3 lsl #0
59 /* Select code for any configuration running in BE8 mode */
60 #ifdef CONFIG_CPU_ENDIAN_BE8
61 #define ARM_BE8(code...) code
63 #define ARM_BE8(code...)
67 * Data preload for architectures that support it
69 #if __LINUX_ARM_ARCH__ >= 5
70 #define PLD(code...) code
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
82 * On Feroceon there is much to gain however, regardless of cache mode.
84 #ifdef CONFIG_CPU_FEROCEON
85 #define CALGN(code...) code
87 #define CALGN(code...)
90 #define IMM12_MASK 0xfff
93 * Enable and disable interrupts
95 #if __LINUX_ARM_ARCH__ >= 6
96 .macro disable_irq_notrace
100 .macro enable_irq_notrace
104 .macro disable_irq_notrace
105 msr cpsr_c, #PSR_I_BIT | SVC_MODE
108 .macro enable_irq_notrace
109 msr cpsr_c, #SVC_MODE
113 .macro asm_trace_hardirqs_off, save=1
114 #if defined(CONFIG_TRACE_IRQFLAGS)
116 stmdb sp!, {r0-r3, ip, lr}
118 bl trace_hardirqs_off
120 ldmia sp!, {r0-r3, ip, lr}
125 .macro asm_trace_hardirqs_on, cond=al, save=1
126 #if defined(CONFIG_TRACE_IRQFLAGS)
128 * actually the registers should be pushed and pop'd conditionally, but
129 * after bl the flags are certainly clobbered
132 stmdb sp!, {r0-r3, ip, lr}
134 bl\cond trace_hardirqs_on
136 ldmia sp!, {r0-r3, ip, lr}
141 .macro disable_irq, save=1
143 asm_trace_hardirqs_off \save
147 asm_trace_hardirqs_on
151 * Save the current IRQ state and disable IRQs. Note that this macro
152 * assumes FIQs are enabled, and that the processor is in SVC mode.
154 .macro save_and_disable_irqs, oldcpsr
155 #ifdef CONFIG_CPU_V7M
156 mrs \oldcpsr, primask
163 .macro save_and_disable_irqs_notrace, oldcpsr
164 #ifdef CONFIG_CPU_V7M
165 mrs \oldcpsr, primask
173 * Restore interrupt state previously stored in a register. We don't
174 * guarantee that this will preserve the flags.
176 .macro restore_irqs_notrace, oldcpsr
177 #ifdef CONFIG_CPU_V7M
178 msr primask, \oldcpsr
184 .macro restore_irqs, oldcpsr
185 tst \oldcpsr, #PSR_I_BIT
186 asm_trace_hardirqs_on cond=eq
187 restore_irqs_notrace \oldcpsr
191 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
192 * reference local symbols in the same assembly file which are to be
193 * resolved by the assembler. Other usage is undefined.
195 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
196 .macro badr\c, rd, sym
197 #ifdef CONFIG_THUMB2_KERNEL
206 * Get current thread_info.
208 .macro get_thread_info, rd
209 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
211 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
212 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
216 * Increment/decrement the preempt count.
218 #ifdef CONFIG_PREEMPT_COUNT
219 .macro inc_preempt_count, ti, tmp
220 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
221 add \tmp, \tmp, #1 @ increment it
222 str \tmp, [\ti, #TI_PREEMPT]
225 .macro dec_preempt_count, ti, tmp
226 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
227 sub \tmp, \tmp, #1 @ decrement it
228 str \tmp, [\ti, #TI_PREEMPT]
231 .macro dec_preempt_count_ti, ti, tmp
233 dec_preempt_count \ti, \tmp
236 .macro inc_preempt_count, ti, tmp
239 .macro dec_preempt_count, ti, tmp
242 .macro dec_preempt_count_ti, ti, tmp
246 #define USERL(l, x...) \
248 .pushsection __ex_table,"a"; \
253 #define USER(x...) USERL(9001f, x)
256 #define ALT_SMP(instr...) \
259 * Note: if you get assembler errors from ALT_UP() when building with
260 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
261 * ALT_SMP( W(instr) ... )
263 #define ALT_UP(instr...) \
264 .pushsection ".alt.smp.init", "a" ;\
267 .if . - 9997b == 2 ;\
270 .if . - 9997b != 4 ;\
271 .error "ALT_UP() content must assemble to exactly 4 bytes";\
274 #define ALT_UP_B(label) \
275 .equ up_b_offset, label - 9998b ;\
276 .pushsection ".alt.smp.init", "a" ;\
278 W(b) . + up_b_offset ;\
281 #define ALT_SMP(instr...)
282 #define ALT_UP(instr...) instr
283 #define ALT_UP_B(label) b label
287 * Instruction barrier
290 #if __LINUX_ARM_ARCH__ >= 7
292 #elif __LINUX_ARM_ARCH__ == 6
293 mcr p15, 0, r0, c7, c5, 4
298 * SMP data memory barrier
302 #if __LINUX_ARM_ARCH__ >= 7
308 #elif __LINUX_ARM_ARCH__ == 6
309 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
311 #error Incompatible SMP platform
321 #if defined(CONFIG_CPU_V7M)
323 * setmode is used to assert to be in svc mode during boot. For v7-M
324 * this is done in __v7m_setup, so setmode can be empty here.
326 .macro setmode, mode, reg
328 #elif defined(CONFIG_THUMB2_KERNEL)
329 .macro setmode, mode, reg
334 .macro setmode, mode, reg
340 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
341 * a scratch register for the macro to overwrite.
343 * This macro is intended for forcing the CPU into SVC mode at boot time.
344 * you cannot return to the original mode.
346 .macro safe_svcmode_maskall reg:req
347 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
349 eor \reg, \reg, #HYP_MODE
351 bic \reg , \reg , #MODE_MASK
352 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
353 THUMB( orr \reg , \reg , #PSR_T_BIT )
355 orr \reg, \reg, #PSR_A_BIT
364 * workaround for possibly broken pre-v6 hardware
365 * (akita, Sharp Zaurus C-1000, PXA270-based)
367 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
372 * STRT/LDRT access macros with ARM and Thumb-2 variants
374 #ifdef CONFIG_THUMB2_KERNEL
376 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
379 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
381 \instr\t\cond\().w \reg, [\ptr, #\off]
383 .error "Unsupported inc macro argument"
386 .pushsection __ex_table,"a"
392 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
393 @ explicit IT instruction needed because of the label
394 @ introduced by the USER macro
401 .error "Unsupported rept macro argument"
405 @ Slightly optimised to avoid incrementing the pointer twice
406 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
408 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
411 add\cond \ptr, #\rept * \inc
414 #else /* !CONFIG_THUMB2_KERNEL */
416 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
420 \instr\()b\t\cond \reg, [\ptr], #\inc
422 \instr\t\cond \reg, [\ptr], #\inc
424 .error "Unsupported inc macro argument"
427 .pushsection __ex_table,"a"
434 #endif /* CONFIG_THUMB2_KERNEL */
436 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
437 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
440 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
441 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
444 /* Utility macro for declaring string literals */
445 .macro string name:req, string
446 .type \name , #object
449 .size \name , . - \name
453 #ifdef CONFIG_THUMB2_KERNEL
460 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
461 #ifndef CONFIG_CPU_USE_DOMAINS
462 adds \tmp, \addr, #\size - 1
463 sbcscc \tmp, \tmp, \limit
465 #ifdef CONFIG_CPU_SPECTRE
472 .macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req
473 #ifdef CONFIG_CPU_SPECTRE
475 subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
476 addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
477 subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) }
478 movlo \addr, #0 @ if (tmp < 0) addr = NULL
483 .macro uaccess_disable, tmp, isb=1
484 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
486 * Whenever we re-enter userspace, the domains should always be
489 mov \tmp, #DACR_UACCESS_DISABLE
490 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
497 .macro uaccess_enable, tmp, isb=1
498 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
500 * Whenever we re-enter userspace, the domains should always be
503 mov \tmp, #DACR_UACCESS_ENABLE
504 mcr p15, 0, \tmp, c3, c0, 0
511 .macro uaccess_save, tmp
512 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
513 mrc p15, 0, \tmp, c3, c0, 0
514 str \tmp, [sp, #SVC_DACR]
518 .macro uaccess_restore
519 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
520 ldr r0, [sp, #SVC_DACR]
521 mcr p15, 0, r0, c3, c0, 0
525 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
527 #if __LINUX_ARM_ARCH__ < 6
541 #ifdef CONFIG_THUMB2_KERNEL
546 .macro bug, msg, line
547 #ifdef CONFIG_THUMB2_KERNEL
552 #ifdef CONFIG_DEBUG_BUGVERBOSE
553 .pushsection .rodata.str, "aMS", %progbits, 1
556 .pushsection __bug_table, "aw"
564 #ifdef CONFIG_KPROBES
565 #define _ASM_NOKPROBE(entry) \
566 .pushsection "_kprobe_blacklist", "aw" ; \
571 #define _ASM_NOKPROBE(entry)
574 #endif /* __ASM_ASSEMBLER_H__ */