2 * EDMA3 support for DaVinci
4 * Copyright (C) 2006-2009 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/edma.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/platform_data/edma.h>
37 /* Offsets matching "struct edmacc_param" */
40 #define PARM_A_B_CNT 0x08
42 #define PARM_SRC_DST_BIDX 0x10
43 #define PARM_LINK_BCNTRLD 0x14
44 #define PARM_SRC_DST_CIDX 0x18
45 #define PARM_CCNT 0x1c
47 #define PARM_SIZE 0x20
49 /* Offsets for EDMA CC global channel registers and their shadows */
50 #define SH_ER 0x00 /* 64 bits */
51 #define SH_ECR 0x08 /* 64 bits */
52 #define SH_ESR 0x10 /* 64 bits */
53 #define SH_CER 0x18 /* 64 bits */
54 #define SH_EER 0x20 /* 64 bits */
55 #define SH_EECR 0x28 /* 64 bits */
56 #define SH_EESR 0x30 /* 64 bits */
57 #define SH_SER 0x38 /* 64 bits */
58 #define SH_SECR 0x40 /* 64 bits */
59 #define SH_IER 0x50 /* 64 bits */
60 #define SH_IECR 0x58 /* 64 bits */
61 #define SH_IESR 0x60 /* 64 bits */
62 #define SH_IPR 0x68 /* 64 bits */
63 #define SH_ICR 0x70 /* 64 bits */
73 /* Offsets for EDMA CC global registers */
74 #define EDMA_REV 0x0000
75 #define EDMA_CCCFG 0x0004
76 #define EDMA_QCHMAP 0x0200 /* 8 registers */
77 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
78 #define EDMA_QDMAQNUM 0x0260
79 #define EDMA_QUETCMAP 0x0280
80 #define EDMA_QUEPRI 0x0284
81 #define EDMA_EMR 0x0300 /* 64 bits */
82 #define EDMA_EMCR 0x0308 /* 64 bits */
83 #define EDMA_QEMR 0x0310
84 #define EDMA_QEMCR 0x0314
85 #define EDMA_CCERR 0x0318
86 #define EDMA_CCERRCLR 0x031c
87 #define EDMA_EEVAL 0x0320
88 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
89 #define EDMA_QRAE 0x0380 /* 4 registers */
90 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
91 #define EDMA_QSTAT 0x0600 /* 2 registers */
92 #define EDMA_QWMTHRA 0x0620
93 #define EDMA_QWMTHRB 0x0624
94 #define EDMA_CCSTAT 0x0640
96 #define EDMA_M 0x1000 /* global channel registers */
97 #define EDMA_ECR 0x1008
98 #define EDMA_ECRH 0x100C
99 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
100 #define EDMA_PARM 0x4000 /* 128 param entries */
102 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
104 #define EDMA_DCHMAP 0x0100 /* 64 registers */
105 #define CHMAP_EXIST BIT(24)
107 #define EDMA_MAX_DMACH 64
108 #define EDMA_MAX_PARAMENTRY 512
110 /*****************************************************************************/
112 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
114 static inline unsigned int edma_read(unsigned ctlr, int offset)
116 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
119 static inline void edma_write(unsigned ctlr, int offset, int val)
121 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
123 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
126 unsigned val = edma_read(ctlr, offset);
129 edma_write(ctlr, offset, val);
131 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
133 unsigned val = edma_read(ctlr, offset);
135 edma_write(ctlr, offset, val);
137 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
139 unsigned val = edma_read(ctlr, offset);
141 edma_write(ctlr, offset, val);
143 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
145 return edma_read(ctlr, offset + (i << 2));
147 static inline void edma_write_array(unsigned ctlr, int offset, int i,
150 edma_write(ctlr, offset + (i << 2), val);
152 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
153 unsigned and, unsigned or)
155 edma_modify(ctlr, offset + (i << 2), and, or);
157 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
159 edma_or(ctlr, offset + (i << 2), or);
161 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
164 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
166 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
169 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
171 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
173 return edma_read(ctlr, EDMA_SHADOW0 + offset);
175 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
178 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
180 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
182 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
184 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
187 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
189 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
192 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
194 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
197 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
199 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
200 unsigned and, unsigned or)
202 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
204 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
207 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
209 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
212 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
215 static inline void set_bits(int offset, int len, unsigned long *p)
217 for (; len > 0; len--)
218 set_bit(offset + (len - 1), p);
221 static inline void clear_bits(int offset, int len, unsigned long *p)
223 for (; len > 0; len--)
224 clear_bit(offset + (len - 1), p);
227 /*****************************************************************************/
229 /* actual number of DMA channels and slots on this silicon */
231 /* how many dma resources of each type */
232 unsigned num_channels;
237 enum dma_event_q default_queue;
239 /* list of channels with no even trigger; terminated by "-1" */
242 /* The edma_inuse bit for each PaRAM slot is clear unless the
243 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
245 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
247 /* The edma_unused bit for each channel is clear unless
248 * it is not being used on this platform. It uses a bit
249 * of SOC-specific initialization code.
251 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
253 unsigned irq_res_start;
254 unsigned irq_res_end;
256 struct dma_interrupt_data {
257 void (*callback)(unsigned channel, unsigned short ch_status,
260 } intr_data[EDMA_MAX_DMACH];
263 static struct edma *edma_cc[EDMA_MAX_CC];
264 static int arch_num_cc;
266 /* dummy param set used to (re)initialize parameter RAM slots */
267 static const struct edmacc_param dummy_paramset = {
268 .link_bcntrld = 0xffff,
272 static const struct of_device_id edma_of_ids[] = {
273 { .compatible = "ti,edma3", },
277 /*****************************************************************************/
279 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
280 enum dma_event_q queue_no)
282 int bit = (ch_no & 0x7) * 4;
284 /* default to low priority queue */
285 if (queue_no == EVENTQ_DEFAULT)
286 queue_no = edma_cc[ctlr]->default_queue;
289 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
290 ~(0x7 << bit), queue_no << bit);
293 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
296 int bit = queue_no * 4;
297 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
298 ((priority & 0x7) << bit));
302 * map_dmach_param - Maps channel number to param entry number
304 * This maps the dma channel number to param entry numberter. In
305 * other words using the DMA channel mapping registers a param entry
306 * can be mapped to any channel
308 * Callers are responsible for ensuring the channel mapping logic is
309 * included in that particular EDMA variant (Eg : dm646x)
312 static void __init map_dmach_param(unsigned ctlr)
315 for (i = 0; i < EDMA_MAX_DMACH; i++)
316 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
320 setup_dma_interrupt(unsigned lch,
321 void (*callback)(unsigned channel, u16 ch_status, void *data),
326 ctlr = EDMA_CTLR(lch);
327 lch = EDMA_CHAN_SLOT(lch);
330 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
333 edma_cc[ctlr]->intr_data[lch].callback = callback;
334 edma_cc[ctlr]->intr_data[lch].data = data;
337 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
339 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
344 static int irq2ctlr(int irq)
346 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
348 else if (irq >= edma_cc[1]->irq_res_start &&
349 irq <= edma_cc[1]->irq_res_end)
355 /******************************************************************************
357 * DMA interrupt handler
359 *****************************************************************************/
360 static irqreturn_t dma_irq_handler(int irq, void *data)
367 ctlr = irq2ctlr(irq);
371 dev_dbg(data, "dma_irq_handler\n");
373 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
375 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
378 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
381 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
389 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
391 slot = __ffs(sh_ipr);
392 sh_ipr &= ~(BIT(slot));
394 if (sh_ier & BIT(slot)) {
395 channel = (bank << 5) | slot;
396 /* Clear the corresponding IPR bits */
397 edma_shadow0_write_array(ctlr, SH_ICR, bank,
399 if (edma_cc[ctlr]->intr_data[channel].callback)
400 edma_cc[ctlr]->intr_data[channel].callback(
401 channel, EDMA_DMA_COMPLETE,
402 edma_cc[ctlr]->intr_data[channel].data);
406 edma_shadow0_write(ctlr, SH_IEVAL, 1);
410 /******************************************************************************
412 * DMA error interrupt handler
414 *****************************************************************************/
415 static irqreturn_t dma_ccerr_handler(int irq, void *data)
419 unsigned int cnt = 0;
421 ctlr = irq2ctlr(irq);
425 dev_dbg(data, "dma_ccerr_handler\n");
427 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
428 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
429 (edma_read(ctlr, EDMA_QEMR) == 0) &&
430 (edma_read(ctlr, EDMA_CCERR) == 0))
435 if (edma_read_array(ctlr, EDMA_EMR, 0))
437 else if (edma_read_array(ctlr, EDMA_EMR, 1))
440 dev_dbg(data, "EMR%d %08x\n", j,
441 edma_read_array(ctlr, EDMA_EMR, j));
442 for (i = 0; i < 32; i++) {
443 int k = (j << 5) + i;
444 if (edma_read_array(ctlr, EDMA_EMR, j) &
446 /* Clear the corresponding EMR bits */
447 edma_write_array(ctlr, EDMA_EMCR, j,
450 edma_shadow0_write_array(ctlr, SH_SECR,
452 if (edma_cc[ctlr]->intr_data[k].
454 edma_cc[ctlr]->intr_data[k].
457 edma_cc[ctlr]->intr_data
462 } else if (edma_read(ctlr, EDMA_QEMR)) {
463 dev_dbg(data, "QEMR %02x\n",
464 edma_read(ctlr, EDMA_QEMR));
465 for (i = 0; i < 8; i++) {
466 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
467 /* Clear the corresponding IPR bits */
468 edma_write(ctlr, EDMA_QEMCR, BIT(i));
469 edma_shadow0_write(ctlr, SH_QSECR,
472 /* NOTE: not reported!! */
475 } else if (edma_read(ctlr, EDMA_CCERR)) {
476 dev_dbg(data, "CCERR %08x\n",
477 edma_read(ctlr, EDMA_CCERR));
478 /* FIXME: CCERR.BIT(16) ignored! much better
479 * to just write CCERRCLR with CCERR value...
481 for (i = 0; i < 8; i++) {
482 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
483 /* Clear the corresponding IPR bits */
484 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
486 /* NOTE: not reported!! */
490 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
491 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
492 (edma_read(ctlr, EDMA_QEMR) == 0) &&
493 (edma_read(ctlr, EDMA_CCERR) == 0))
499 edma_write(ctlr, EDMA_EEVAL, 1);
503 static int reserve_contiguous_slots(int ctlr, unsigned int id,
504 unsigned int num_slots,
505 unsigned int start_slot)
508 unsigned int count = num_slots;
509 int stop_slot = start_slot;
510 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
512 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
513 j = EDMA_CHAN_SLOT(i);
514 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
515 /* Record our current beginning slot */
516 if (count == num_slots)
520 set_bit(j, tmp_inuse);
525 clear_bit(j, tmp_inuse);
527 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
537 * We have to clear any bits that we set
538 * if we run out parameter RAM slots, i.e we do find a set
539 * of contiguous parameter RAM slots but do not find the exact number
540 * requested as we may reach the total number of parameter RAM slots
542 if (i == edma_cc[ctlr]->num_slots)
546 for_each_set_bit_from(j, tmp_inuse, stop_slot)
547 clear_bit(j, edma_cc[ctlr]->edma_inuse);
552 for (j = i - num_slots + 1; j <= i; ++j)
553 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
554 &dummy_paramset, PARM_SIZE);
556 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
559 static int prepare_unused_channel_list(struct device *dev, void *data)
561 struct platform_device *pdev = to_platform_device(dev);
563 struct of_phandle_args dma_spec;
566 count = of_property_count_strings(dev->of_node, "dma-names");
569 for (i = 0; i < count; i++) {
570 if (of_parse_phandle_with_args(dev->of_node, "dmas",
575 if (!of_match_node(edma_of_ids, dma_spec.np)) {
576 of_node_put(dma_spec.np);
580 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
581 edma_cc[0]->edma_unused);
582 of_node_put(dma_spec.np);
587 /* For non-OF case */
588 for (i = 0; i < pdev->num_resources; i++) {
589 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
590 (int)pdev->resource[i].start >= 0) {
591 ctlr = EDMA_CTLR(pdev->resource[i].start);
592 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
593 edma_cc[ctlr]->edma_unused);
600 /*-----------------------------------------------------------------------*/
602 static bool unused_chan_list_done;
604 /* Resource alloc/free: dma channels, parameter RAM slots */
607 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
608 * @channel: specific channel to allocate; negative for "any unmapped channel"
609 * @callback: optional; to be issued on DMA completion or errors
610 * @data: passed to callback
611 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
612 * Controller (TC) executes requests using this channel. Use
613 * EVENTQ_DEFAULT unless you really need a high priority queue.
615 * This allocates a DMA channel and its associated parameter RAM slot.
616 * The parameter RAM is initialized to hold a dummy transfer.
618 * Normal use is to pass a specific channel number as @channel, to make
619 * use of hardware events mapped to that channel. When the channel will
620 * be used only for software triggering or event chaining, channels not
621 * mapped to hardware events (or mapped to unused events) are preferable.
623 * DMA transfers start from a channel using edma_start(), or by
624 * chaining. When the transfer described in that channel's parameter RAM
625 * slot completes, that slot's data may be reloaded through a link.
627 * DMA errors are only reported to the @callback associated with the
628 * channel driving that transfer, but transfer completion callbacks can
629 * be sent to another channel under control of the TCC field in
630 * the option word of the transfer's parameter RAM set. Drivers must not
631 * use DMA transfer completion callbacks for channels they did not allocate.
632 * (The same applies to TCC codes used in transfer chaining.)
634 * Returns the number of the channel, else negative errno.
636 int edma_alloc_channel(int channel,
637 void (*callback)(unsigned channel, u16 ch_status, void *data),
639 enum dma_event_q eventq_no)
641 unsigned i, done = 0, ctlr = 0;
644 if (!unused_chan_list_done) {
646 * Scan all the platform devices to find out the EDMA channels
647 * used and clear them in the unused list, making the rest
648 * available for ARM usage.
650 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
651 prepare_unused_channel_list);
655 unused_chan_list_done = true;
659 ctlr = EDMA_CTLR(channel);
660 channel = EDMA_CHAN_SLOT(channel);
664 for (i = 0; i < arch_num_cc; i++) {
667 channel = find_next_bit(edma_cc[i]->edma_unused,
668 edma_cc[i]->num_channels,
670 if (channel == edma_cc[i]->num_channels)
672 if (!test_and_set_bit(channel,
673 edma_cc[i]->edma_inuse)) {
685 } else if (channel >= edma_cc[ctlr]->num_channels) {
687 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
691 /* ensure access through shadow region 0 */
692 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
694 /* ensure no events are pending */
695 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
696 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
697 &dummy_paramset, PARM_SIZE);
700 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
703 map_dmach_queue(ctlr, channel, eventq_no);
705 return EDMA_CTLR_CHAN(ctlr, channel);
707 EXPORT_SYMBOL(edma_alloc_channel);
711 * edma_free_channel - deallocate DMA channel
712 * @channel: dma channel returned from edma_alloc_channel()
714 * This deallocates the DMA channel and associated parameter RAM slot
715 * allocated by edma_alloc_channel().
717 * Callers are responsible for ensuring the channel is inactive, and
718 * will not be reactivated by linking, chaining, or software calls to
721 void edma_free_channel(unsigned channel)
725 ctlr = EDMA_CTLR(channel);
726 channel = EDMA_CHAN_SLOT(channel);
728 if (channel >= edma_cc[ctlr]->num_channels)
731 setup_dma_interrupt(channel, NULL, NULL);
732 /* REVISIT should probably take out of shadow region 0 */
734 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
735 &dummy_paramset, PARM_SIZE);
736 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
738 EXPORT_SYMBOL(edma_free_channel);
741 * edma_alloc_slot - allocate DMA parameter RAM
742 * @slot: specific slot to allocate; negative for "any unused slot"
744 * This allocates a parameter RAM slot, initializing it to hold a
745 * dummy transfer. Slots allocated using this routine have not been
746 * mapped to a hardware DMA channel, and will normally be used by
747 * linking to them from a slot associated with a DMA channel.
749 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
750 * slots may be allocated on behalf of DSP firmware.
752 * Returns the number of the slot, else negative errno.
754 int edma_alloc_slot(unsigned ctlr, int slot)
760 slot = EDMA_CHAN_SLOT(slot);
763 slot = edma_cc[ctlr]->num_channels;
765 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
766 edma_cc[ctlr]->num_slots, slot);
767 if (slot == edma_cc[ctlr]->num_slots)
769 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
772 } else if (slot < edma_cc[ctlr]->num_channels ||
773 slot >= edma_cc[ctlr]->num_slots) {
775 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
779 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
780 &dummy_paramset, PARM_SIZE);
782 return EDMA_CTLR_CHAN(ctlr, slot);
784 EXPORT_SYMBOL(edma_alloc_slot);
787 * edma_free_slot - deallocate DMA parameter RAM
788 * @slot: parameter RAM slot returned from edma_alloc_slot()
790 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
791 * Callers are responsible for ensuring the slot is inactive, and will
794 void edma_free_slot(unsigned slot)
798 ctlr = EDMA_CTLR(slot);
799 slot = EDMA_CHAN_SLOT(slot);
801 if (slot < edma_cc[ctlr]->num_channels ||
802 slot >= edma_cc[ctlr]->num_slots)
805 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
806 &dummy_paramset, PARM_SIZE);
807 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
809 EXPORT_SYMBOL(edma_free_slot);
813 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
814 * The API will return the starting point of a set of
815 * contiguous parameter RAM slots that have been requested
817 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
818 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
819 * @count: number of contiguous Paramter RAM slots
820 * @slot - the start value of Parameter RAM slot that should be passed if id
821 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
823 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
824 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
825 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
827 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
828 * set of contiguous parameter RAM slots from the "slot" that is passed as an
829 * argument to the API.
831 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
832 * starts looking for a set of contiguous parameter RAMs from the "slot"
833 * that is passed as an argument to the API. On failure the API will try to
834 * find a set of contiguous Parameter RAM slots from the remaining Parameter
837 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
840 * The start slot requested should be greater than
841 * the number of channels and lesser than the total number
844 if ((id != EDMA_CONT_PARAMS_ANY) &&
845 (slot < edma_cc[ctlr]->num_channels ||
846 slot >= edma_cc[ctlr]->num_slots))
850 * The number of parameter RAM slots requested cannot be less than 1
851 * and cannot be more than the number of slots minus the number of
854 if (count < 1 || count >
855 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
859 case EDMA_CONT_PARAMS_ANY:
860 return reserve_contiguous_slots(ctlr, id, count,
861 edma_cc[ctlr]->num_channels);
862 case EDMA_CONT_PARAMS_FIXED_EXACT:
863 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
864 return reserve_contiguous_slots(ctlr, id, count, slot);
870 EXPORT_SYMBOL(edma_alloc_cont_slots);
873 * edma_free_cont_slots - deallocate DMA parameter RAM slots
874 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
875 * @count: the number of contiguous parameter RAM slots to be freed
877 * This deallocates the parameter RAM slots allocated by
878 * edma_alloc_cont_slots.
879 * Callers/applications need to keep track of sets of contiguous
880 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
882 * Callers are responsible for ensuring the slots are inactive, and will
885 int edma_free_cont_slots(unsigned slot, int count)
887 unsigned ctlr, slot_to_free;
890 ctlr = EDMA_CTLR(slot);
891 slot = EDMA_CHAN_SLOT(slot);
893 if (slot < edma_cc[ctlr]->num_channels ||
894 slot >= edma_cc[ctlr]->num_slots ||
898 for (i = slot; i < slot + count; ++i) {
900 slot_to_free = EDMA_CHAN_SLOT(i);
902 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
903 &dummy_paramset, PARM_SIZE);
904 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
909 EXPORT_SYMBOL(edma_free_cont_slots);
911 /*-----------------------------------------------------------------------*/
913 /* Parameter RAM operations (i) -- read/write partial slots */
916 * edma_set_src - set initial DMA source address in parameter RAM slot
917 * @slot: parameter RAM slot being configured
918 * @src_port: physical address of source (memory, controller FIFO, etc)
919 * @addressMode: INCR, except in very rare cases
920 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
921 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
923 * Note that the source address is modified during the DMA transfer
924 * according to edma_set_src_index().
926 void edma_set_src(unsigned slot, dma_addr_t src_port,
927 enum address_mode mode, enum fifo_width width)
931 ctlr = EDMA_CTLR(slot);
932 slot = EDMA_CHAN_SLOT(slot);
934 if (slot < edma_cc[ctlr]->num_slots) {
935 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
938 /* set SAM and program FWID */
939 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
944 edma_parm_write(ctlr, PARM_OPT, slot, i);
946 /* set the source port address
947 in source register of param structure */
948 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
951 EXPORT_SYMBOL(edma_set_src);
954 * edma_set_dest - set initial DMA destination address in parameter RAM slot
955 * @slot: parameter RAM slot being configured
956 * @dest_port: physical address of destination (memory, controller FIFO, etc)
957 * @addressMode: INCR, except in very rare cases
958 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
959 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
961 * Note that the destination address is modified during the DMA transfer
962 * according to edma_set_dest_index().
964 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
965 enum address_mode mode, enum fifo_width width)
969 ctlr = EDMA_CTLR(slot);
970 slot = EDMA_CHAN_SLOT(slot);
972 if (slot < edma_cc[ctlr]->num_slots) {
973 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
976 /* set DAM and program FWID */
977 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
982 edma_parm_write(ctlr, PARM_OPT, slot, i);
983 /* set the destination port address
984 in dest register of param structure */
985 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
988 EXPORT_SYMBOL(edma_set_dest);
991 * edma_get_position - returns the current transfer point
992 * @slot: parameter RAM slot being examined
993 * @dst: true selects the dest position, false the source
995 * Returns the position of the current active slot
997 dma_addr_t edma_get_position(unsigned slot, bool dst)
999 u32 offs, ctlr = EDMA_CTLR(slot);
1001 slot = EDMA_CHAN_SLOT(slot);
1003 offs = PARM_OFFSET(slot);
1004 offs += dst ? PARM_DST : PARM_SRC;
1006 return edma_read(ctlr, offs);
1010 * edma_set_src_index - configure DMA source address indexing
1011 * @slot: parameter RAM slot being configured
1012 * @src_bidx: byte offset between source arrays in a frame
1013 * @src_cidx: byte offset between source frames in a block
1015 * Offsets are specified to support either contiguous or discontiguous
1016 * memory transfers, or repeated access to a hardware register, as needed.
1017 * When accessing hardware registers, both offsets are normally zero.
1019 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1023 ctlr = EDMA_CTLR(slot);
1024 slot = EDMA_CHAN_SLOT(slot);
1026 if (slot < edma_cc[ctlr]->num_slots) {
1027 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1028 0xffff0000, src_bidx);
1029 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1030 0xffff0000, src_cidx);
1033 EXPORT_SYMBOL(edma_set_src_index);
1036 * edma_set_dest_index - configure DMA destination address indexing
1037 * @slot: parameter RAM slot being configured
1038 * @dest_bidx: byte offset between destination arrays in a frame
1039 * @dest_cidx: byte offset between destination frames in a block
1041 * Offsets are specified to support either contiguous or discontiguous
1042 * memory transfers, or repeated access to a hardware register, as needed.
1043 * When accessing hardware registers, both offsets are normally zero.
1045 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1049 ctlr = EDMA_CTLR(slot);
1050 slot = EDMA_CHAN_SLOT(slot);
1052 if (slot < edma_cc[ctlr]->num_slots) {
1053 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1054 0x0000ffff, dest_bidx << 16);
1055 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1056 0x0000ffff, dest_cidx << 16);
1059 EXPORT_SYMBOL(edma_set_dest_index);
1062 * edma_set_transfer_params - configure DMA transfer parameters
1063 * @slot: parameter RAM slot being configured
1064 * @acnt: how many bytes per array (at least one)
1065 * @bcnt: how many arrays per frame (at least one)
1066 * @ccnt: how many frames per block (at least one)
1067 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1068 * the value to reload into bcnt when it decrements to zero
1069 * @sync_mode: ASYNC or ABSYNC
1071 * See the EDMA3 documentation to understand how to configure and link
1072 * transfers using the fields in PaRAM slots. If you are not doing it
1073 * all at once with edma_write_slot(), you will use this routine
1074 * plus two calls each for source and destination, setting the initial
1075 * address and saying how to index that address.
1077 * An example of an A-Synchronized transfer is a serial link using a
1078 * single word shift register. In that case, @acnt would be equal to
1079 * that word size; the serial controller issues a DMA synchronization
1080 * event to transfer each word, and memory access by the DMA transfer
1081 * controller will be word-at-a-time.
1083 * An example of an AB-Synchronized transfer is a device using a FIFO.
1084 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1085 * The controller with the FIFO issues DMA synchronization events when
1086 * the FIFO threshold is reached, and the DMA transfer controller will
1087 * transfer one frame to (or from) the FIFO. It will probably use
1088 * efficient burst modes to access memory.
1090 void edma_set_transfer_params(unsigned slot,
1091 u16 acnt, u16 bcnt, u16 ccnt,
1092 u16 bcnt_rld, enum sync_dimension sync_mode)
1096 ctlr = EDMA_CTLR(slot);
1097 slot = EDMA_CHAN_SLOT(slot);
1099 if (slot < edma_cc[ctlr]->num_slots) {
1100 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1101 0x0000ffff, bcnt_rld << 16);
1102 if (sync_mode == ASYNC)
1103 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1105 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1106 /* Set the acount, bcount, ccount registers */
1107 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1108 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1111 EXPORT_SYMBOL(edma_set_transfer_params);
1114 * edma_link - link one parameter RAM slot to another
1115 * @from: parameter RAM slot originating the link
1116 * @to: parameter RAM slot which is the link target
1118 * The originating slot should not be part of any active DMA transfer.
1120 void edma_link(unsigned from, unsigned to)
1122 unsigned ctlr_from, ctlr_to;
1124 ctlr_from = EDMA_CTLR(from);
1125 from = EDMA_CHAN_SLOT(from);
1126 ctlr_to = EDMA_CTLR(to);
1127 to = EDMA_CHAN_SLOT(to);
1129 if (from >= edma_cc[ctlr_from]->num_slots)
1131 if (to >= edma_cc[ctlr_to]->num_slots)
1133 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1136 EXPORT_SYMBOL(edma_link);
1139 * edma_unlink - cut link from one parameter RAM slot
1140 * @from: parameter RAM slot originating the link
1142 * The originating slot should not be part of any active DMA transfer.
1143 * Its link is set to 0xffff.
1145 void edma_unlink(unsigned from)
1149 ctlr = EDMA_CTLR(from);
1150 from = EDMA_CHAN_SLOT(from);
1152 if (from >= edma_cc[ctlr]->num_slots)
1154 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1156 EXPORT_SYMBOL(edma_unlink);
1158 /*-----------------------------------------------------------------------*/
1160 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1163 * edma_write_slot - write parameter RAM data for slot
1164 * @slot: number of parameter RAM slot being modified
1165 * @param: data to be written into parameter RAM slot
1167 * Use this to assign all parameters of a transfer at once. This
1168 * allows more efficient setup of transfers than issuing multiple
1169 * calls to set up those parameters in small pieces, and provides
1170 * complete control over all transfer options.
1172 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1176 ctlr = EDMA_CTLR(slot);
1177 slot = EDMA_CHAN_SLOT(slot);
1179 if (slot >= edma_cc[ctlr]->num_slots)
1181 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1184 EXPORT_SYMBOL(edma_write_slot);
1187 * edma_read_slot - read parameter RAM data from slot
1188 * @slot: number of parameter RAM slot being copied
1189 * @param: where to store copy of parameter RAM data
1191 * Use this to read data from a parameter RAM slot, perhaps to
1192 * save them as a template for later reuse.
1194 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1198 ctlr = EDMA_CTLR(slot);
1199 slot = EDMA_CHAN_SLOT(slot);
1201 if (slot >= edma_cc[ctlr]->num_slots)
1203 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1206 EXPORT_SYMBOL(edma_read_slot);
1208 /*-----------------------------------------------------------------------*/
1210 /* Various EDMA channel control operations */
1213 * edma_pause - pause dma on a channel
1214 * @channel: on which edma_start() has been called
1216 * This temporarily disables EDMA hardware events on the specified channel,
1217 * preventing them from triggering new transfers on its behalf
1219 void edma_pause(unsigned channel)
1223 ctlr = EDMA_CTLR(channel);
1224 channel = EDMA_CHAN_SLOT(channel);
1226 if (channel < edma_cc[ctlr]->num_channels) {
1227 unsigned int mask = BIT(channel & 0x1f);
1229 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1232 EXPORT_SYMBOL(edma_pause);
1235 * edma_resume - resumes dma on a paused channel
1236 * @channel: on which edma_pause() has been called
1238 * This re-enables EDMA hardware events on the specified channel.
1240 void edma_resume(unsigned channel)
1244 ctlr = EDMA_CTLR(channel);
1245 channel = EDMA_CHAN_SLOT(channel);
1247 if (channel < edma_cc[ctlr]->num_channels) {
1248 unsigned int mask = BIT(channel & 0x1f);
1250 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1253 EXPORT_SYMBOL(edma_resume);
1255 int edma_trigger_channel(unsigned channel)
1260 ctlr = EDMA_CTLR(channel);
1261 channel = EDMA_CHAN_SLOT(channel);
1262 mask = BIT(channel & 0x1f);
1264 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
1266 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
1267 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
1270 EXPORT_SYMBOL(edma_trigger_channel);
1273 * edma_start - start dma on a channel
1274 * @channel: channel being activated
1276 * Channels with event associations will be triggered by their hardware
1277 * events, and channels without such associations will be triggered by
1278 * software. (At this writing there is no interface for using software
1279 * triggers except with channels that don't support hardware triggers.)
1281 * Returns zero on success, else negative errno.
1283 int edma_start(unsigned channel)
1287 ctlr = EDMA_CTLR(channel);
1288 channel = EDMA_CHAN_SLOT(channel);
1290 if (channel < edma_cc[ctlr]->num_channels) {
1291 int j = channel >> 5;
1292 unsigned int mask = BIT(channel & 0x1f);
1294 /* EDMA channels without event association */
1295 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1296 pr_debug("EDMA: ESR%d %08x\n", j,
1297 edma_shadow0_read_array(ctlr, SH_ESR, j));
1298 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1302 /* EDMA channel with event association */
1303 pr_debug("EDMA: ER%d %08x\n", j,
1304 edma_shadow0_read_array(ctlr, SH_ER, j));
1305 /* Clear any pending event or error */
1306 edma_write_array(ctlr, EDMA_ECR, j, mask);
1307 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1309 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1310 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1311 pr_debug("EDMA: EER%d %08x\n", j,
1312 edma_shadow0_read_array(ctlr, SH_EER, j));
1318 EXPORT_SYMBOL(edma_start);
1321 * edma_stop - stops dma on the channel passed
1322 * @channel: channel being deactivated
1324 * When @lch is a channel, any active transfer is paused and
1325 * all pending hardware events are cleared. The current transfer
1326 * may not be resumed, and the channel's Parameter RAM should be
1327 * reinitialized before being reused.
1329 void edma_stop(unsigned channel)
1333 ctlr = EDMA_CTLR(channel);
1334 channel = EDMA_CHAN_SLOT(channel);
1336 if (channel < edma_cc[ctlr]->num_channels) {
1337 int j = channel >> 5;
1338 unsigned int mask = BIT(channel & 0x1f);
1340 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1341 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1342 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1343 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1345 pr_debug("EDMA: EER%d %08x\n", j,
1346 edma_shadow0_read_array(ctlr, SH_EER, j));
1348 /* REVISIT: consider guarding against inappropriate event
1349 * chaining by overwriting with dummy_paramset.
1353 EXPORT_SYMBOL(edma_stop);
1355 /******************************************************************************
1357 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1358 * been removed before EDMA has finished.It is usedful for removable media.
1360 * ch_no - channel no
1362 * Return: zero on success, or corresponding error no on failure
1364 * FIXME this should not be needed ... edma_stop() should suffice.
1366 *****************************************************************************/
1368 void edma_clean_channel(unsigned channel)
1372 ctlr = EDMA_CTLR(channel);
1373 channel = EDMA_CHAN_SLOT(channel);
1375 if (channel < edma_cc[ctlr]->num_channels) {
1376 int j = (channel >> 5);
1377 unsigned int mask = BIT(channel & 0x1f);
1379 pr_debug("EDMA: EMR%d %08x\n", j,
1380 edma_read_array(ctlr, EDMA_EMR, j));
1381 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1382 /* Clear the corresponding EMR bits */
1383 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1385 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1386 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1389 EXPORT_SYMBOL(edma_clean_channel);
1392 * edma_clear_event - clear an outstanding event on the DMA channel
1394 * channel - channel number
1396 void edma_clear_event(unsigned channel)
1400 ctlr = EDMA_CTLR(channel);
1401 channel = EDMA_CHAN_SLOT(channel);
1403 if (channel >= edma_cc[ctlr]->num_channels)
1406 edma_write(ctlr, EDMA_ECR, BIT(channel));
1408 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1410 EXPORT_SYMBOL(edma_clear_event);
1412 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1414 static int edma_of_read_u32_to_s16_array(const struct device_node *np,
1415 const char *propname, s16 *out_values,
1420 ret = of_property_read_u16_array(np, propname, out_values, sz);
1431 static int edma_xbar_event_map(struct device *dev,
1432 struct device_node *node,
1433 struct edma_soc_info *pdata, int len)
1436 struct resource res;
1438 const s16 (*xbar_chans)[2];
1439 u32 shift, offset, mux;
1441 xbar_chans = devm_kzalloc(dev,
1442 len/sizeof(s16) + 2*sizeof(s16),
1447 ret = of_address_to_resource(node, 1, &res);
1451 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1455 ret = edma_of_read_u32_to_s16_array(node,
1456 "ti,edma-xbar-event-map",
1462 for (i = 0; xbar_chans[i][0] != -1; i++) {
1463 shift = (xbar_chans[i][1] & 0x03) << 3;
1464 offset = xbar_chans[i][1] & 0xfffffffc;
1465 mux = readl(xbar + offset);
1466 mux &= ~(0xff << shift);
1467 mux |= xbar_chans[i][0] << shift;
1468 writel(mux, (xbar + offset));
1471 pdata->xbar_chans = xbar_chans;
1476 static int edma_of_parse_dt(struct device *dev,
1477 struct device_node *node,
1478 struct edma_soc_info *pdata)
1482 struct property *prop;
1484 struct edma_rsv_info *rsv_info;
1485 s8 (*queue_priority_map)[2];
1487 ret = of_property_read_u32(node, "dma-channels", &value);
1490 pdata->n_channel = value;
1492 ret = of_property_read_u32(node, "ti,edma-regions", &value);
1495 pdata->n_region = value;
1497 ret = of_property_read_u32(node, "ti,edma-slots", &value);
1500 pdata->n_slot = value;
1505 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1508 pdata->rsv = rsv_info;
1510 queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
1511 if (!queue_priority_map)
1514 for (i = 0; i < 3; i++) {
1515 queue_priority_map[i][0] = i;
1516 queue_priority_map[i][1] = i;
1518 queue_priority_map[i][0] = -1;
1519 queue_priority_map[i][1] = -1;
1521 pdata->queue_priority_mapping = queue_priority_map;
1523 pdata->default_queue = 0;
1525 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1527 ret = edma_xbar_event_map(dev, node, pdata, sz);
1532 static struct of_dma_filter_info edma_filter_info = {
1533 .filter_fn = edma_filter_fn,
1536 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1537 struct device_node *node)
1539 struct edma_soc_info *info;
1542 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1544 return ERR_PTR(-ENOMEM);
1546 ret = edma_of_parse_dt(dev, node, info);
1548 return ERR_PTR(ret);
1550 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1551 dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
1552 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1558 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1559 struct device_node *node)
1561 return ERR_PTR(-ENOSYS);
1565 static int edma_probe(struct platform_device *pdev)
1567 struct edma_soc_info **info = pdev->dev.platform_data;
1568 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1569 s8 (*queue_priority_mapping)[2];
1570 int i, j, off, ln, found = 0;
1572 const s16 (*rsv_chans)[2];
1573 const s16 (*rsv_slots)[2];
1574 const s16 (*xbar_chans)[2];
1575 int irq[EDMA_MAX_CC] = {0, 0};
1576 int err_irq[EDMA_MAX_CC] = {0, 0};
1577 struct resource *r[EDMA_MAX_CC] = {NULL};
1578 struct resource res[EDMA_MAX_CC];
1580 struct device_node *node = pdev->dev.of_node;
1581 struct device *dev = &pdev->dev;
1585 /* Check if this is a second instance registered */
1587 dev_err(dev, "only one EDMA instance is supported via DT\n");
1591 ninfo[0] = edma_setup_info_from_dt(dev, node);
1592 if (IS_ERR(ninfo[0])) {
1593 dev_err(dev, "failed to get DT data\n");
1594 return PTR_ERR(ninfo[0]);
1603 pm_runtime_enable(dev);
1604 ret = pm_runtime_get_sync(dev);
1606 dev_err(dev, "pm_runtime_get_sync() failed\n");
1610 for (j = 0; j < EDMA_MAX_CC; j++) {
1617 ret = of_address_to_resource(node, j, &res[j]);
1621 sprintf(res_name, "edma_cc%d", j);
1622 r[j] = platform_get_resource_byname(pdev,
1635 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1636 if (IS_ERR(edmacc_regs_base[j]))
1637 return PTR_ERR(edmacc_regs_base[j]);
1639 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1644 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
1646 edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
1647 EDMA_MAX_PARAMENTRY);
1648 edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
1650 edma_cc[j]->num_tc = info[j]->n_tc;
1652 edma_cc[j]->default_queue = info[j]->default_queue;
1654 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1655 edmacc_regs_base[j]);
1657 for (i = 0; i < edma_cc[j]->num_slots; i++)
1658 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1659 &dummy_paramset, PARM_SIZE);
1661 /* Mark all channels as unused */
1662 memset(edma_cc[j]->edma_unused, 0xff,
1663 sizeof(edma_cc[j]->edma_unused));
1667 /* Clear the reserved channels in unused list */
1668 rsv_chans = info[j]->rsv->rsv_chans;
1670 for (i = 0; rsv_chans[i][0] != -1; i++) {
1671 off = rsv_chans[i][0];
1672 ln = rsv_chans[i][1];
1674 edma_cc[j]->edma_unused);
1678 /* Set the reserved slots in inuse list */
1679 rsv_slots = info[j]->rsv->rsv_slots;
1681 for (i = 0; rsv_slots[i][0] != -1; i++) {
1682 off = rsv_slots[i][0];
1683 ln = rsv_slots[i][1];
1685 edma_cc[j]->edma_inuse);
1690 /* Clear the xbar mapped channels in unused list */
1691 xbar_chans = info[j]->xbar_chans;
1693 for (i = 0; xbar_chans[i][1] != -1; i++) {
1694 off = xbar_chans[i][1];
1696 edma_cc[j]->edma_unused);
1701 irq[j] = irq_of_parse_and_map(node, 0);
1702 err_irq[j] = irq_of_parse_and_map(node, 2);
1706 sprintf(irq_name, "edma%d", j);
1707 irq[j] = platform_get_irq_byname(pdev, irq_name);
1709 sprintf(irq_name, "edma%d_err", j);
1710 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1712 edma_cc[j]->irq_res_start = irq[j];
1713 edma_cc[j]->irq_res_end = err_irq[j];
1715 status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
1719 "devm_request_irq %d failed --> %d\n",
1724 status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
1728 "devm_request_irq %d failed --> %d\n",
1729 err_irq[j], status);
1733 for (i = 0; i < edma_cc[j]->num_channels; i++)
1734 map_dmach_queue(j, i, info[j]->default_queue);
1736 queue_priority_mapping = info[j]->queue_priority_mapping;
1738 /* Event queue priority mapping */
1739 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1740 assign_priority_to_queue(j,
1741 queue_priority_mapping[i][0],
1742 queue_priority_mapping[i][1]);
1744 /* Map the channel to param entry if channel mapping logic
1747 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1750 for (i = 0; i < info[j]->n_region; i++) {
1751 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1752 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1753 edma_write_array(j, EDMA_QRAE, i, 0x0);
1761 static struct platform_driver edma_driver = {
1764 .of_match_table = edma_of_ids,
1766 .probe = edma_probe,
1769 static int __init edma_init(void)
1771 return platform_driver_probe(&edma_driver, edma_probe);
1773 arch_initcall(edma_init);