1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
4 * Copyright (C) 2012 National Instruments Corp.
7 #include "zynq-7000.dtsi"
10 model = "Zynq ZC702 Development Board";
11 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20 device_type = "memory";
21 reg = <0x0 0x40000000>;
26 stdout-path = "serial0:115200n8";
30 compatible = "gpio-keys";
36 gpios = <&gpio0 12 0>;
37 linux,code = <108>; /* down */
43 gpios = <&gpio0 14 0>;
44 linux,code = <103>; /* up */
51 compatible = "gpio-leds";
55 gpios = <&gpio0 10 0>;
56 linux,default-trigger = "heartbeat";
61 compatible = "usb-nop-xceiv";
68 compatible = "mmio-sram";
69 reg = <0xfffc0000 0x10000>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_can0_default>;
80 ps-clk-frequency = <33333333>;
85 phy-mode = "rgmii-id";
86 phy-handle = <ðernet_phy>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_gem0_default>;
90 ethernet_phy: ethernet-phy@7 {
92 device_type = "ethernet-phy";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_gpio0_default>;
103 clock-frequency = <400000>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_i2c0_default>;
108 compatible = "nxp,pca9548";
109 #address-cells = <1>;
114 #address-cells = <1>;
117 si570: clock-generator@5d {
119 compatible = "silabs,si570";
120 temperature-stability = <50>;
122 factory-fout = <156250000>;
123 clock-frequency = <148500000>;
128 #address-cells = <1>;
131 adv7511: hdmi-tx@39 {
132 compatible = "adi,adv7511";
134 adi,input-depth = <8>;
135 adi,input-colorspace = "yuv422";
136 adi,input-clock = "1x";
137 adi,input-style = <3>;
138 adi,input-justification = "right";
143 #address-cells = <1>;
147 compatible = "atmel,24c08";
153 #address-cells = <1>;
157 compatible = "ti,tca6416";
165 #address-cells = <1>;
169 compatible = "nxp,pcf8563";
175 #address-cells = <1>;
179 compatible = "ti,ucd9248";
183 compatible = "ti,ucd9248";
187 compatible = "ti,ucd9248";
195 pinctrl_can0_default: can0-default {
198 groups = "can0_9_grp";
202 groups = "can0_9_grp";
218 pinctrl_gem0_default: gem0-default {
220 function = "ethernet0";
221 groups = "ethernet0_0_grp";
225 groups = "ethernet0_0_grp";
231 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
237 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
244 groups = "mdio0_0_grp";
248 groups = "mdio0_0_grp";
255 pinctrl_gpio0_default: gpio0-default {
258 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
259 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
260 "gpio0_13_grp", "gpio0_14_grp";
264 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
265 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
266 "gpio0_13_grp", "gpio0_14_grp";
272 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
277 pins = "MIO7", "MIO8";
282 pinctrl_i2c0_default: i2c0-default {
284 groups = "i2c0_10_grp";
289 groups = "i2c0_10_grp";
296 pinctrl_sdhci0_default: sdhci0-default {
298 groups = "sdio0_2_grp";
303 groups = "sdio0_2_grp";
310 groups = "gpio0_0_grp";
311 function = "sdio0_cd";
315 groups = "gpio0_0_grp";
323 groups = "gpio0_15_grp";
324 function = "sdio0_wp";
328 groups = "gpio0_15_grp";
336 pinctrl_uart1_default: uart1-default {
338 groups = "uart1_10_grp";
343 groups = "uart1_10_grp";
359 pinctrl_usb0_default: usb0-default {
361 groups = "usb0_0_grp";
366 groups = "usb0_0_grp";
372 pins = "MIO29", "MIO31", "MIO36";
377 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
378 "MIO35", "MIO37", "MIO38", "MIO39";
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_sdhci0_default>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_uart1_default>;
399 usb-phy = <&usb_phy0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_usb0_default>;