1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
4 * Copyright (C) 2012 National Instruments Corp.
7 #include "zynq-7000.dtsi"
10 model = "Xilinx ZC702 board";
11 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
21 device_type = "memory";
22 reg = <0x0 0x40000000>;
27 stdout-path = "serial0:115200n8";
31 compatible = "gpio-keys";
35 gpios = <&gpio0 12 0>;
36 linux,code = <108>; /* down */
42 gpios = <&gpio0 14 0>;
43 linux,code = <103>; /* up */
50 compatible = "gpio-leds";
54 gpios = <&gpio0 10 0>;
55 linux,default-trigger = "heartbeat";
60 compatible = "usb-nop-xceiv";
67 compatible = "mmio-sram";
68 reg = <0xfffc0000 0x10000>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_can0_default>;
79 ps-clk-frequency = <33333333>;
84 phy-mode = "rgmii-id";
85 phy-handle = <ðernet_phy>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gem0_default>;
89 ethernet_phy: ethernet-phy@7 {
91 device_type = "ethernet-phy";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_gpio0_default>;
102 clock-frequency = <400000>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_i2c0_default>;
107 compatible = "nxp,pca9548";
108 #address-cells = <1>;
113 #address-cells = <1>;
116 si570: clock-generator@5d {
118 compatible = "silabs,si570";
119 temperature-stability = <50>;
121 factory-fout = <156250000>;
122 clock-frequency = <148500000>;
127 #address-cells = <1>;
130 adv7511: hdmi-tx@39 {
131 compatible = "adi,adv7511";
133 adi,input-depth = <8>;
134 adi,input-colorspace = "yuv422";
135 adi,input-clock = "1x";
136 adi,input-style = <3>;
137 adi,input-justification = "right";
142 #address-cells = <1>;
146 compatible = "atmel,24c08";
152 #address-cells = <1>;
156 compatible = "ti,tca6416";
164 #address-cells = <1>;
168 compatible = "nxp,pcf8563";
174 #address-cells = <1>;
178 compatible = "ti,ucd9248";
182 compatible = "ti,ucd9248";
186 compatible = "ti,ucd9248";
194 pinctrl_can0_default: can0-default {
197 groups = "can0_9_grp";
201 groups = "can0_9_grp";
217 pinctrl_gem0_default: gem0-default {
219 function = "ethernet0";
220 groups = "ethernet0_0_grp";
224 groups = "ethernet0_0_grp";
230 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
236 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
243 groups = "mdio0_0_grp";
247 groups = "mdio0_0_grp";
254 pinctrl_gpio0_default: gpio0-default {
257 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
258 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
259 "gpio0_13_grp", "gpio0_14_grp";
263 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
264 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
265 "gpio0_13_grp", "gpio0_14_grp";
271 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
276 pins = "MIO7", "MIO8";
281 pinctrl_i2c0_default: i2c0-default {
283 groups = "i2c0_10_grp";
288 groups = "i2c0_10_grp";
295 pinctrl_sdhci0_default: sdhci0-default {
297 groups = "sdio0_2_grp";
302 groups = "sdio0_2_grp";
309 groups = "gpio0_0_grp";
310 function = "sdio0_cd";
314 groups = "gpio0_0_grp";
322 groups = "gpio0_15_grp";
323 function = "sdio0_wp";
327 groups = "gpio0_15_grp";
335 pinctrl_uart1_default: uart1-default {
337 groups = "uart1_10_grp";
342 groups = "uart1_10_grp";
358 pinctrl_usb0_default: usb0-default {
360 groups = "usb0_0_grp";
365 groups = "usb0_0_grp";
371 pins = "MIO29", "MIO31", "MIO36";
376 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
377 "MIO35", "MIO37", "MIO38", "MIO39";
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_sdhci0_default>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart1_default>;
398 usb-phy = <&usb_phy0>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usb0_default>;