1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
6 /include/ "zynq-7000.dtsi"
9 model = "Ebang EBAZ4205";
10 compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
18 device_type = "memory";
19 reg = <0x0 0x10000000>;
23 stdout-path = "serial0:115200n8";
28 ps-clk-frequency = <33333333>;
38 assigned-clocks = <&clkc 18>;
39 assigned-clock-rates = <25000000>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_gpio0_default>;
52 pinctrl_gpio0_default: gpio0-default {
54 groups = "gpio0_20_grp", "gpio0_32_grp";
59 groups = "gpio0_20_grp", "gpio0_32_grp";
65 pins = "MIO20", "MIO32";
70 pinctrl_sdhci0_default: sdhci0-default {
72 groups = "sdio0_2_grp";
77 groups = "sdio0_2_grp";
84 groups = "gpio0_34_grp";
85 function = "sdio0_cd";
89 groups = "gpio0_34_grp";
97 pinctrl_uart1_default: uart1-default {
99 groups = "uart1_4_grp";
104 groups = "uart1_4_grp";
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_sdhci0_default>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart1_default>;