arch/arm/boot/dts/zynq-7000.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2011 - 2014 Xilinx
   4  */
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         compatible = "xlnx,zynq-7000";
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14
  15                 cpu0: cpu@0 {
  16                         compatible = "arm,cortex-a9";
  17                         device_type = "cpu";
  18                         reg = <0>;
  19                         clocks = <&clkc 3>;
  20                         clock-latency = <1000>;
  21                         cpu0-supply = <&regulator_vccpint>;
  22                         operating-points = <
  23                                 /* kHz    uV */
  24                                 666667  1000000
  25                                 333334  1000000
  26                         >;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a9";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                         clocks = <&clkc 3>;
  34                 };
  35         };
  36
  37         fpga_full: fpga-full {
  38                 compatible = "fpga-region";
  39                 fpga-mgr = <&devcfg>;
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 ranges;
  43         };
  44
  45         pmu@f8891000 {
  46                 compatible = "arm,cortex-a9-pmu";
  47                 interrupts = <0 5 4>, <0 6 4>;
  48                 interrupt-parent = <&intc>;
  49                 reg = <0xf8891000 0x1000>,
  50                       <0xf8893000 0x1000>;
  51         };
  52
  53         regulator_vccpint: fixedregulator {
  54                 compatible = "regulator-fixed";
  55                 regulator-name = "VCCPINT";
  56                 regulator-min-microvolt = <1000000>;
  57                 regulator-max-microvolt = <1000000>;
  58                 regulator-boot-on;
  59                 regulator-always-on;
  60         };
  61
  62         replicator {
  63                 compatible = "arm,coresight-static-replicator";
  64                 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
  65                 clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
  66
  67                 out-ports {
  68                         #address-cells = <1>;
  69                         #size-cells = <0>;
  70
  71                         /* replicator output ports */
  72                         port@0 {
  73                                 reg = <0>;
  74                                 replicator_out_port0: endpoint {
  75                                         remote-endpoint = <&tpiu_in_port>;
  76                                 };
  77                         };
  78                         port@1 {
  79                                 reg = <1>;
  80                                 replicator_out_port1: endpoint {
  81                                         remote-endpoint = <&etb_in_port>;
  82                                 };
  83                         };
  84                 };
  85                 in-ports {
  86                         /* replicator input port */
  87                         port {
  88                                 replicator_in_port0: endpoint {
  89                                         remote-endpoint = <&funnel_out_port>;
  90                                 };
  91                         };
  92                 };
  93         };
  94
  95         amba: axi {
  96                 compatible = "simple-bus";
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 interrupt-parent = <&intc>;
 100                 ranges;
 101
 102                 adc: adc@f8007100 {
 103                         compatible = "xlnx,zynq-xadc-1.00.a";
 104                         reg = <0xf8007100 0x20>;
 105                         interrupts = <0 7 4>;
 106                         interrupt-parent = <&intc>;
 107                         clocks = <&clkc 12>;
 108                 };
 109
 110                 can0: can@e0008000 {
 111                         compatible = "xlnx,zynq-can-1.0";
 112                         status = "disabled";
 113                         clocks = <&clkc 19>, <&clkc 36>;
 114                         clock-names = "can_clk", "pclk";
 115                         reg = <0xe0008000 0x1000>;
 116                         interrupts = <0 28 4>;
 117                         interrupt-parent = <&intc>;
 118                         tx-fifo-depth = <0x40>;
 119                         rx-fifo-depth = <0x40>;
 120                 };
 121
 122                 can1: can@e0009000 {
 123                         compatible = "xlnx,zynq-can-1.0";
 124                         status = "disabled";
 125                         clocks = <&clkc 20>, <&clkc 37>;
 126                         clock-names = "can_clk", "pclk";
 127                         reg = <0xe0009000 0x1000>;
 128                         interrupts = <0 51 4>;
 129                         interrupt-parent = <&intc>;
 130                         tx-fifo-depth = <0x40>;
 131                         rx-fifo-depth = <0x40>;
 132                 };
 133
 134                 gpio0: gpio@e000a000 {
 135                         compatible = "xlnx,zynq-gpio-1.0";
 136                         #gpio-cells = <2>;
 137                         clocks = <&clkc 42>;
 138                         gpio-controller;
 139                         interrupt-controller;
 140                         #interrupt-cells = <2>;
 141                         interrupt-parent = <&intc>;
 142                         interrupts = <0 20 4>;
 143                         reg = <0xe000a000 0x1000>;
 144                 };
 145
 146                 i2c0: i2c@e0004000 {
 147                         compatible = "cdns,i2c-r1p10";
 148                         status = "disabled";
 149                         clocks = <&clkc 38>;
 150                         interrupt-parent = <&intc>;
 151                         interrupts = <0 25 4>;
 152                         reg = <0xe0004000 0x1000>;
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                 };
 156
 157                 i2c1: i2c@e0005000 {
 158                         compatible = "cdns,i2c-r1p10";
 159                         status = "disabled";
 160                         clocks = <&clkc 39>;
 161                         interrupt-parent = <&intc>;
 162                         interrupts = <0 48 4>;
 163                         reg = <0xe0005000 0x1000>;
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                 };
 167
 168                 intc: interrupt-controller@f8f01000 {
 169                         compatible = "arm,cortex-a9-gic";
 170                         #interrupt-cells = <3>;
 171                         interrupt-controller;
 172                         reg = <0xF8F01000 0x1000>,
 173                               <0xF8F00100 0x100>;
 174                 };
 175
 176                 L2: cache-controller@f8f02000 {
 177                         compatible = "arm,pl310-cache";
 178                         reg = <0xF8F02000 0x1000>;
 179                         interrupts = <0 2 4>;
 180                         arm,data-latency = <3 2 2>;
 181                         arm,tag-latency = <2 2 2>;
 182                         cache-unified;
 183                         cache-level = <2>;
 184                 };
 185
 186                 mc: memory-controller@f8006000 {
 187                         compatible = "xlnx,zynq-ddrc-a05";
 188                         reg = <0xf8006000 0x1000>;
 189                 };
 190
 191                 uart0: serial@e0000000 {
 192                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 193                         status = "disabled";
 194                         clocks = <&clkc 23>, <&clkc 40>;
 195                         clock-names = "uart_clk", "pclk";
 196                         reg = <0xE0000000 0x1000>;
 197                         interrupts = <0 27 4>;
 198                 };
 199
 200                 uart1: serial@e0001000 {
 201                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
 202                         status = "disabled";
 203                         clocks = <&clkc 24>, <&clkc 41>;
 204                         clock-names = "uart_clk", "pclk";
 205                         reg = <0xE0001000 0x1000>;
 206                         interrupts = <0 50 4>;
 207                 };
 208
 209                 spi0: spi@e0006000 {
 210                         compatible = "xlnx,zynq-spi-r1p6";
 211                         reg = <0xe0006000 0x1000>;
 212                         status = "disabled";
 213                         interrupt-parent = <&intc>;
 214                         interrupts = <0 26 4>;
 215                         clocks = <&clkc 25>, <&clkc 34>;
 216                         clock-names = "ref_clk", "pclk";
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                 };
 220
 221                 spi1: spi@e0007000 {
 222                         compatible = "xlnx,zynq-spi-r1p6";
 223                         reg = <0xe0007000 0x1000>;
 224                         status = "disabled";
 225                         interrupt-parent = <&intc>;
 226                         interrupts = <0 49 4>;
 227                         clocks = <&clkc 26>, <&clkc 35>;
 228                         clock-names = "ref_clk", "pclk";
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                 };
 232
 233                 qspi: spi@e000d000 {
 234                         compatible = "xlnx,zynq-qspi-1.0";
 235                         reg = <0xe000d000 0x1000>;
 236                         interrupt-parent = <&intc>;
 237                         interrupts = <0 19 4>;
 238                         clocks = <&clkc 10>, <&clkc 43>;
 239                         clock-names = "ref_clk", "pclk";
 240                         status = "disabled";
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                 };
 244
 245                 gem0: ethernet@e000b000 {
 246                         compatible = "xlnx,zynq-gem", "cdns,gem";
 247                         reg = <0xe000b000 0x1000>;
 248                         status = "disabled";
 249                         interrupts = <0 22 4>;
 250                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 251                         clock-names = "pclk", "hclk", "tx_clk";
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                 };
 255
 256                 gem1: ethernet@e000c000 {
 257                         compatible = "xlnx,zynq-gem", "cdns,gem";
 258                         reg = <0xe000c000 0x1000>;
 259                         status = "disabled";
 260                         interrupts = <0 45 4>;
 261                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 262                         clock-names = "pclk", "hclk", "tx_clk";
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                 };
 266
 267                 smcc: memory-controller@e000e000 {
 268                         compatible = "arm,pl353-smc-r2p1", "arm,primecell";
 269                         reg = <0xe000e000 0x0001000>;
 270                         status = "disabled";
 271                         clock-names = "memclk", "apb_pclk";
 272                         clocks = <&clkc 11>, <&clkc 44>;
 273                         ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
 274                                   0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
 275                                   0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
 276                         #address-cells = <2>;
 277                         #size-cells = <1>;
 278
 279                         nfc0: nand-controller@0,0 {
 280                                 compatible = "arm,pl353-nand-r2p1";
 281                                 reg = <0 0 0x1000000>;
 282                                 status = "disabled";
 283                                 #address-cells = <1>;
 284                                 #size-cells = <0>;
 285                         };
 286                 };
 287
 288                 sdhci0: mmc@e0100000 {
 289                         compatible = "arasan,sdhci-8.9a";
 290                         status = "disabled";
 291                         clock-names = "clk_xin", "clk_ahb";
 292                         clocks = <&clkc 21>, <&clkc 32>;
 293                         interrupt-parent = <&intc>;
 294                         interrupts = <0 24 4>;
 295                         reg = <0xe0100000 0x1000>;
 296                 };
 297
 298                 sdhci1: mmc@e0101000 {
 299                         compatible = "arasan,sdhci-8.9a";
 300                         status = "disabled";
 301                         clock-names = "clk_xin", "clk_ahb";
 302                         clocks = <&clkc 22>, <&clkc 33>;
 303                         interrupt-parent = <&intc>;
 304                         interrupts = <0 47 4>;
 305                         reg = <0xe0101000 0x1000>;
 306                 };
 307
 308                 slcr: slcr@f8000000 {
 309                         #address-cells = <1>;
 310                         #size-cells = <1>;
 311                         compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 312                         reg = <0xF8000000 0x1000>;
 313                         ranges;
 314                         clkc: clkc@100 {
 315                                 #clock-cells = <1>;
 316                                 compatible = "xlnx,ps7-clkc";
 317                                 fclk-enable = <0>;
 318                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 319                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 320                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 321                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 322                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 323                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 324                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
 325                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 326                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 327                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 328                                                 "dbg_trc", "dbg_apb";
 329                                 reg = <0x100 0x100>;
 330                         };
 331
 332                         rstc: rstc@200 {
 333                                 compatible = "xlnx,zynq-reset";
 334                                 reg = <0x200 0x48>;
 335                                 #reset-cells = <1>;
 336                                 syscon = <&slcr>;
 337                         };
 338
 339                         pinctrl0: pinctrl@700 {
 340                                 compatible = "xlnx,pinctrl-zynq";
 341                                 reg = <0x700 0x200>;
 342                                 syscon = <&slcr>;
 343                         };
 344                 };
 345
 346                 dmac_s: dma-controller@f8003000 {
 347                         compatible = "arm,pl330", "arm,primecell";
 348                         reg = <0xf8003000 0x1000>;
 349                         interrupt-parent = <&intc>;
 350                         /*
 351                          * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
 352                          * "dma4", "dma5", "dma6", "dma7";
 353                          */
 354                         interrupts = <0 13 4>,
 355                                      <0 14 4>, <0 15 4>,
 356                                      <0 16 4>, <0 17 4>,
 357                                      <0 40 4>, <0 41 4>,
 358                                      <0 42 4>, <0 43 4>;
 359                         #dma-cells = <1>;
 360                         clocks = <&clkc 27>;
 361                         clock-names = "apb_pclk";
 362                 };
 363
 364                 devcfg: devcfg@f8007000 {
 365                         compatible = "xlnx,zynq-devcfg-1.0";
 366                         reg = <0xf8007000 0x100>;
 367                         interrupt-parent = <&intc>;
 368                         interrupts = <0 8 4>;
 369                         clocks = <&clkc 12>;
 370                         clock-names = "ref_clk";
 371                         syscon = <&slcr>;
 372                 };
 373
 374                 global_timer: timer@f8f00200 {
 375                         compatible = "arm,cortex-a9-global-timer";
 376                         reg = <0xf8f00200 0x20>;
 377                         interrupts = <1 11 0x301>;
 378                         interrupt-parent = <&intc>;
 379                         clocks = <&clkc 4>;
 380                 };
 381
 382                 ttc0: timer@f8001000 {
 383                         interrupt-parent = <&intc>;
 384                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
 385                         compatible = "cdns,ttc";
 386                         clocks = <&clkc 6>;
 387                         reg = <0xF8001000 0x1000>;
 388                 };
 389
 390                 ttc1: timer@f8002000 {
 391                         interrupt-parent = <&intc>;
 392                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
 393                         compatible = "cdns,ttc";
 394                         clocks = <&clkc 6>;
 395                         reg = <0xF8002000 0x1000>;
 396                 };
 397
 398                 scutimer: timer@f8f00600 {
 399                         interrupt-parent = <&intc>;
 400                         interrupts = <1 13 0x301>;
 401                         compatible = "arm,cortex-a9-twd-timer";
 402                         reg = <0xf8f00600 0x20>;
 403                         clocks = <&clkc 4>;
 404                 };
 405
 406                 usb0: usb@e0002000 {
 407                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 408                         status = "disabled";
 409                         clocks = <&clkc 28>;
 410                         interrupt-parent = <&intc>;
 411                         interrupts = <0 21 4>;
 412                         reg = <0xe0002000 0x1000>;
 413                         phy_type = "ulpi";
 414                 };
 415
 416                 usb1: usb@e0003000 {
 417                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 418                         status = "disabled";
 419                         clocks = <&clkc 29>;
 420                         interrupt-parent = <&intc>;
 421                         interrupts = <0 44 4>;
 422                         reg = <0xe0003000 0x1000>;
 423                         phy_type = "ulpi";
 424                 };
 425
 426                 watchdog0: watchdog@f8005000 {
 427                         clocks = <&clkc 45>;
 428                         compatible = "cdns,wdt-r1p2";
 429                         interrupt-parent = <&intc>;
 430                         interrupts = <0 9 1>;
 431                         reg = <0xf8005000 0x1000>;
 432                         timeout-sec = <10>;
 433                 };
 434
 435                 etb@f8801000 {
 436                         compatible = "arm,coresight-etb10", "arm,primecell";
 437                         reg = <0xf8801000 0x1000>;
 438                         clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
 439                         clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
 440                         in-ports {
 441                                 port {
 442                                         etb_in_port: endpoint {
 443                                                 remote-endpoint = <&replicator_out_port1>;
 444                                         };
 445                                 };
 446                         };
 447                 };
 448
 449                 tpiu@f8803000 {
 450                         compatible = "arm,coresight-tpiu", "arm,primecell";
 451                         reg = <0xf8803000 0x1000>;
 452                         clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
 453                         clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
 454                         in-ports {
 455                                 port {
 456                                         tpiu_in_port: endpoint {
 457                                                 remote-endpoint = <&replicator_out_port0>;
 458                                         };
 459                                 };
 460                         };
 461                 };
 462
 463                 funnel@f8804000 {
 464                         compatible = "arm,coresight-static-funnel", "arm,primecell";
 465                         reg = <0xf8804000 0x1000>;
 466                         clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
 467                         clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
 468
 469                         /* funnel output ports */
 470                         out-ports {
 471                                 port {
 472                                         funnel_out_port: endpoint {
 473                                                 remote-endpoint =
 474                                                         <&replicator_in_port0>;
 475                                         };
 476                                 };
 477                         };
 478
 479                         in-ports {
 480                                 #address-cells = <1>;
 481                                 #size-cells = <0>;
 482
 483                                 /* funnel input ports */
 484                                 port@0 {
 485                                         reg = <0>;
 486                                         funnel0_in_port0: endpoint {
 487                                                 remote-endpoint = <&ptm0_out_port>;
 488                                         };
 489                                 };
 490
 491                                 port@1 {
 492                                         reg = <1>;
 493                                         funnel0_in_port1: endpoint {
 494                                                 remote-endpoint = <&ptm1_out_port>;
 495                                         };
 496                                 };
 497
 498                                 port@2 {
 499                                         reg = <2>;
 500                                         funnel0_in_port2: endpoint {
 501                                         };
 502                                 };
 503                                 /* The other input ports are not connect to anything */
 504                         };
 505                 };
 506
 507                 ptm@f889c000 {
 508                         compatible = "arm,coresight-etm3x", "arm,primecell";
 509                         reg = <0xf889c000 0x1000>;
 510                         clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
 511                         clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
 512                         cpu = <&cpu0>;
 513                         out-ports {
 514                                 port {
 515                                         ptm0_out_port: endpoint {
 516                                                 remote-endpoint = <&funnel0_in_port0>;
 517                                         };
 518                                 };
 519                         };
 520                 };
 521
 522                 ptm@f889d000 {
 523                         compatible = "arm,coresight-etm3x", "arm,primecell";
 524                         reg = <0xf889d000 0x1000>;
 525                         clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
 526                         clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
 527                         cpu = <&cpu1>;
 528                         out-ports {
 529                                 port {
 530                                         ptm1_out_port: endpoint {
 531                                                 remote-endpoint = <&funnel0_in_port1>;
 532                                         };
 533                                 };
 534                         };
 535                 };
 536         };
 537 };