1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/zx296702-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 enable-method = "zte,zx296702-smp";
16 compatible = "arm,cortex-a9";
18 next-level-cache = <&l2cc>;
23 compatible = "arm,cortex-a9";
25 next-level-cache = <&l2cc>;
34 compatible = "simple-bus";
35 interrupt-parent = <&intc>;
38 matrix: bus-matrix@400000 {
39 compatible = "zte,zx-bus-matrix";
40 reg = <0x00400000 0x1000>;
43 intc: interrupt-controller@801000 {
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
49 reg = <0x00801000 0x1000>,
53 global_timer: timer@8000200 {
54 compatible = "arm,cortex-a9-global-timer";
55 reg = <0x00800200 0x20>;
56 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
57 interrupt-parent = <&intc>;
58 clocks = <&topclk ZX296702_A9_PERIPHCLK>;
61 l2cc: l2-cache-controller@c00000 {
62 compatible = "arm,pl310-cache";
63 reg = <0x00c00000 0x1000>;
66 arm,data-latency = <1 1 1>;
67 arm,tag-latency = <1 1 1>;
68 arm,double-linefill = <1>;
69 arm,double-linefill-incr = <0>;
73 compatible = "zte,zx296702-pcu";
74 reg = <0xa0008000 0x1000>;
77 topclk: topclk@9800000 {
78 compatible = "zte,zx296702-topcrm-clk";
79 reg = <0x09800000 0x1000>;
83 lsp1clk: lsp1clk@9400000 {
84 compatible = "zte,zx296702-lsp1crpm-clk";
85 reg = <0x09400000 0x1000>;
89 lsp0clk: lsp0clk@b000000 {
90 compatible = "zte,zx296702-lsp0crpm-clk";
91 reg = <0x0b000000 0x1000>;
95 uart0: serial@9405000 {
96 compatible = "zte,zx296702-uart";
97 reg = <0x09405000 0x1000>;
98 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&lsp1clk ZX296702_UART0_WCLK>;
103 uart1: serial@9406000 {
104 compatible = "zte,zx296702-uart";
105 reg = <0x09406000 0x1000>;
106 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&lsp1clk ZX296702_UART1_WCLK>;
112 compatible = "snps,dw-mshc";
113 #address-cells = <1>;
115 reg = <0x09408000 0x1000>;
116 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
119 <&lsp1clk ZX296702_SDMMC0_WCLK>;
120 clock-names = "biu", "ciu";
125 compatible = "snps,dw-mshc";
126 #address-cells = <1>;
128 reg = <0x0b003000 0x1000>;
129 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
132 <&lsp0clk ZX296702_SDMMC1_WCLK>;
133 clock-names = "biu", "ciu";
137 sysctrl: sysctrl@a0007000 {
138 compatible = "zte,sysctrl", "syscon";
139 reg = <0xa0007000 0x1000>;