Merge tag 'iio-fixes-for-5.6a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / zx296702.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2
3 #include <dt-bindings/clock/zx296702-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5
6 / {
7         #address-cells = <1>;
8         #size-cells = <1>;
9
10         cpus {
11                 #address-cells = <1>;
12                 #size-cells = <0>;
13                 enable-method = "zte,zx296702-smp";
14
15                 cpu@0 {
16                         compatible = "arm,cortex-a9";
17                         device_type = "cpu";
18                         next-level-cache = <&l2cc>;
19                         reg = <0>;
20                 };
21
22                 cpu@1 {
23                         compatible = "arm,cortex-a9";
24                         device_type = "cpu";
25                         next-level-cache = <&l2cc>;
26                         reg = <1>;
27                 };
28         };
29
30
31         soc {
32                 #address-cells = <1>;
33                 #size-cells = <1>;
34                 compatible = "simple-bus";
35                 interrupt-parent = <&intc>;
36                 ranges;
37
38                 matrix: bus-matrix@400000 {
39                         compatible = "zte,zx-bus-matrix";
40                         reg = <0x00400000 0x1000>;
41                 };
42
43                 intc: interrupt-controller@801000 {
44                         compatible = "arm,cortex-a9-gic";
45                         #interrupt-cells = <3>;
46                         #address-cells = <1>;
47                         #size-cells = <1>;
48                         interrupt-controller;
49                         reg = <0x00801000 0x1000>,
50                               <0x00800100 0x100>;
51                 };
52
53                 global_timer: timer@8000200 {
54                         compatible = "arm,cortex-a9-global-timer";
55                         reg = <0x00800200 0x20>;
56                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
57                         interrupt-parent = <&intc>;
58                         clocks = <&topclk ZX296702_A9_PERIPHCLK>;
59                 };
60
61                 l2cc: l2-cache-controller@c00000 {
62                         compatible = "arm,pl310-cache";
63                         reg = <0x00c00000 0x1000>;
64                         cache-unified;
65                         cache-level = <2>;
66                         arm,data-latency = <1 1 1>;
67                         arm,tag-latency = <1 1 1>;
68                         arm,double-linefill = <1>;
69                         arm,double-linefill-incr = <0>;
70                 };
71
72                 pcu: pcu@a0008000 {
73                         compatible = "zte,zx296702-pcu";
74                         reg = <0xa0008000 0x1000>;
75                 };
76
77                 topclk: topclk@9800000 {
78                         compatible = "zte,zx296702-topcrm-clk";
79                         reg = <0x09800000 0x1000>;
80                         #clock-cells = <1>;
81                 };
82
83                 lsp1clk: lsp1clk@9400000 {
84                         compatible = "zte,zx296702-lsp1crpm-clk";
85                         reg = <0x09400000 0x1000>;
86                         #clock-cells = <1>;
87                 };
88
89                 lsp0clk: lsp0clk@b000000 {
90                         compatible = "zte,zx296702-lsp0crpm-clk";
91                         reg = <0x0b000000 0x1000>;
92                         #clock-cells = <1>;
93                 };
94
95                 uart0: serial@9405000 {
96                         compatible = "zte,zx296702-uart";
97                         reg = <0x09405000 0x1000>;
98                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
99                         clocks = <&lsp1clk ZX296702_UART0_WCLK>;
100                         status = "disabled";
101                 };
102
103                 uart1: serial@9406000 {
104                         compatible = "zte,zx296702-uart";
105                         reg = <0x09406000 0x1000>;
106                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
107                         clocks = <&lsp1clk ZX296702_UART1_WCLK>;
108                         status = "disabled";
109                 };
110
111                 mmc0: mmc@9408000 {
112                         compatible = "snps,dw-mshc";
113                         #address-cells = <1>;
114                         #size-cells = <0>;
115                         reg = <0x09408000 0x1000>;
116                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
117                         fifo-depth = <32>;
118                         clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
119                                  <&lsp1clk ZX296702_SDMMC0_WCLK>;
120                         clock-names = "biu", "ciu";
121                         status = "disabled";
122                 };
123
124                 mmc1: mmc@b003000 {
125                         compatible = "snps,dw-mshc";
126                         #address-cells = <1>;
127                         #size-cells = <0>;
128                         reg = <0x0b003000 0x1000>;
129                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
130                         fifo-depth = <32>;
131                         clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
132                                  <&lsp0clk ZX296702_SDMMC1_WCLK>;
133                         clock-names = "biu", "ciu";
134                         status = "disabled";
135                 };
136
137                 sysctrl: sysctrl@a0007000 {
138                         compatible = "zte,sysctrl", "syscon";
139                         reg = <0xa0007000 0x1000>;
140                 };
141         };
142 };