arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB SPU3 board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * SPU - Seat Power Unit
   8  *
   9  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB SPU3 Board";
  20         compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 reg = <0x80000000 0x20000000>;
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-0 = <&pinctrl_leds_debug>;
  34                 pinctrl-names = "default";
  35
  36                 led-debug {
  37                         label = "zii:green:debug1";
  38                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  39                         linux,default-trigger = "heartbeat";
  40                 };
  41         };
  42
  43         reg_vcc_3v3_mcu: regulator {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "vcc_3v3_mcu";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48         };
  49
  50         supply-voltage-monitor {
  51                 compatible = "iio-hwmon";
  52                 io-channels = <&adc0 8>, /* 12V_MAIN */
  53                               <&adc0 9>, /* +3.3V    */
  54                               <&adc1 8>, /* VCC_1V5  */
  55                               <&adc1 9>; /* VCC_1V2  */
  56         };
  57 };
  58
  59 &adc0 {
  60         vref-supply = <&reg_vcc_3v3_mcu>;
  61         status = "okay";
  62 };
  63
  64 &adc1 {
  65         vref-supply = <&reg_vcc_3v3_mcu>;
  66         status = "okay";
  67 };
  68
  69 &dspi1 {
  70         bus-num = <1>;
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_dspi1>;
  73         /*
  74          * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
  75          * node disabled by default and rely on bootloader to enable
  76          * it when appropriate.
  77          */
  78         status = "disabled";
  79
  80         flash@0 {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "m25p128", "jedec,spi-nor";
  84                 reg = <0>;
  85                 spi-max-frequency = <50000000>;
  86
  87                 partition@0 {
  88                         label = "m25p128-0";
  89                         reg = <0x0 0x01000000>;
  90                 };
  91         };
  92 };
  93
  94 &edma0 {
  95         status = "okay";
  96 };
  97
  98 &edma1 {
  99         status = "okay";
 100 };
 101
 102 &esdhc0 {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_esdhc0>;
 105         bus-width = <8>;
 106         non-removable;
 107         no-1-8-v;
 108         keep-power-in-suspend;
 109         no-sdio;
 110         no-sd;
 111         status = "okay";
 112 };
 113
 114 &esdhc1 {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_esdhc1>;
 117         bus-width = <4>;
 118         no-sdio;
 119         status = "okay";
 120 };
 121
 122 &fec1 {
 123         phy-mode = "rmii";
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_fec1>;
 126         status = "okay";
 127
 128         fixed-link {
 129                 speed = <100>;
 130                 full-duplex;
 131         };
 132
 133         mdio1: mdio {
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 status = "okay";
 137
 138                 switch0: switch0@0 {
 139                         compatible = "marvell,mv88e6190";
 140                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 141                         pinctrl-names = "default";
 142                         reg = <0>;
 143                         eeprom-length = <65536>;
 144                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 145                         interrupt-parent = <&gpio3>;
 146                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 147                         interrupt-controller;
 148                         #interrupt-cells = <2>;
 149
 150                         ports {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153
 154                                 port@0 {
 155                                         reg = <0>;
 156                                         label = "cpu";
 157                                         ethernet = <&fec1>;
 158
 159                                         fixed-link {
 160                                                 speed = <100>;
 161                                                 full-duplex;
 162                                         };
 163                                 };
 164
 165                                 port@1 {
 166                                         reg = <1>;
 167                                         label = "eth_cu_1000_1";
 168                                 };
 169
 170                                 port@2 {
 171                                         reg = <2>;
 172                                         label = "eth_cu_1000_2";
 173                                 };
 174
 175                                 port@3 {
 176                                         reg = <3>;
 177                                         label = "eth_cu_1000_3";
 178                                 };
 179
 180                                 port@4 {
 181                                         reg = <4>;
 182                                         label = "eth_cu_1000_4";
 183                                 };
 184
 185                                 port@5 {
 186                                         reg = <5>;
 187                                         label = "eth_cu_1000_5";
 188                                 };
 189
 190                                 port@6 {
 191                                         reg = <6>;
 192                                         label = "eth_cu_1000_6";
 193                                 };
 194                         };
 195                 };
 196         };
 197 };
 198
 199 &i2c0 {
 200         clock-frequency = <100000>;
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_i2c0>;
 203         status = "okay";
 204
 205         gpio6: io-expander@22 {
 206                 compatible = "nxp,pca9554";
 207                 reg = <0x22>;
 208                 gpio-controller;
 209                 #gpio-cells = <2>;
 210         };
 211
 212         lm75@48 {
 213                 compatible = "national,lm75";
 214                 reg = <0x48>;
 215         };
 216
 217         eeprom@50 {
 218                 compatible = "atmel,24c04";
 219                 reg = <0x50>;
 220                 label = "nameplate";
 221         };
 222
 223         eeprom@52 {
 224                 compatible = "atmel,24c04";
 225                 reg = <0x52>;
 226         };
 227 };
 228
 229 &snvsrtc {
 230         status = "disabled";
 231 };
 232
 233 &uart0 {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_uart0>;
 236         status = "okay";
 237 };
 238
 239 &uart1 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_uart1>;
 242         status = "okay";
 243
 244         rave-sp {
 245                 compatible = "zii,rave-sp-rdu2";
 246                 current-speed = <1000000>;
 247                 #address-cells = <1>;
 248                 #size-cells = <1>;
 249
 250                 watchdog {
 251                         compatible = "zii,rave-sp-watchdog";
 252                 };
 253
 254                 eeprom@a3 {
 255                         compatible = "zii,rave-sp-eeprom";
 256                         reg = <0xa3 0x4000>;
 257                         #address-cells = <1>;
 258                         #size-cells = <1>;
 259                         zii,eeprom-name = "main-eeprom";
 260                 };
 261         };
 262 };
 263
 264 &wdoga5 {
 265         status = "disabled";
 266 };
 267
 268 &iomuxc {
 269         pinctrl_dspi1: dspi1grp {
 270                 fsl,pins = <
 271                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 272                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 273                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 274                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 275                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 276                 >;
 277         };
 278
 279         pinctrl_esdhc0: esdhc0grp {
 280                 fsl,pins = <
 281                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 282                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 283                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 284                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 285                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 286                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 287                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 288                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 289                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 290                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 291                 >;
 292         };
 293
 294         pinctrl_esdhc1: esdhc1grp {
 295                 fsl,pins = <
 296                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 297                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 298                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 299                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 300                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 301                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 302                 >;
 303         };
 304
 305         pinctrl_fec1: fec1grp {
 306                 fsl,pins = <
 307                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 308                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 309                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 310                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 311                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 312                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 313                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 314                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 315                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 316                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 317                 >;
 318         };
 319
 320         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 321                 fsl,pins = <
 322                         VF610_PAD_PTE2__GPIO_107                0x31c2
 323                         VF610_PAD_PTB28__GPIO_98                0x219d
 324                 >;
 325         };
 326
 327         pinctrl_i2c0: i2c0grp {
 328                 fsl,pins = <
 329                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 330                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 331                 >;
 332         };
 333
 334         pinctrl_i2c1: i2c1grp {
 335                 fsl,pins = <
 336                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 337                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 338                 >;
 339         };
 340
 341         pinctrl_leds_debug: pinctrl-leds-debug {
 342                 fsl,pins = <
 343                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 344                 >;
 345         };
 346
 347         pinctrl_uart0: uart0grp {
 348                 fsl,pins = <
 349                         VF610_PAD_PTB10__UART0_TX               0x21a2
 350                         VF610_PAD_PTB11__UART0_RX               0x21a1
 351                 >;
 352         };
 353
 354         pinctrl_uart1: uart1grp {
 355                 fsl,pins = <
 356                         VF610_PAD_PTB23__UART1_TX               0x21a2
 357                         VF610_PAD_PTB24__UART1_RX               0x21a1
 358                 >;
 359         };
 360 };