arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB DTU board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * DTU - Digital Tapping Unit
   8  *
   9  * Copyright (C) 2015-2019 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB DTU Board";
  20         compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 reg = <0x80000000 0x20000000>;
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-0 = <&pinctrl_leds_debug>;
  34                 pinctrl-names = "default";
  35
  36                 led-debug {
  37                         label = "zii:green:debug1";
  38                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  39                         linux,default-trigger = "heartbeat";
  40                 };
  41         };
  42
  43         reg_vcc_3v3_mcu: regulator {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "vcc_3v3_mcu";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48         };
  49 };
  50
  51 &adc0 {
  52         vref-supply = <&reg_vcc_3v3_mcu>;
  53         status = "okay";
  54 };
  55
  56 &adc1 {
  57         vref-supply = <&reg_vcc_3v3_mcu>;
  58         status = "okay";
  59 };
  60
  61 &edma0 {
  62         status = "okay";
  63 };
  64
  65 &edma1 {
  66         status = "okay";
  67 };
  68
  69 &esdhc0 {
  70         pinctrl-names = "default";
  71         pinctrl-0 = <&pinctrl_esdhc0>;
  72         bus-width = <8>;
  73         non-removable;
  74         no-1-8-v;
  75         keep-power-in-suspend;
  76         status = "okay";
  77 };
  78
  79 &esdhc1 {
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_esdhc1>;
  82         bus-width = <4>;
  83         status = "okay";
  84 };
  85
  86 &fec1 {
  87         phy-mode = "rmii";
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_fec1>;
  90         status = "okay";
  91
  92         fixed-link {
  93                 speed = <100>;
  94                 full-duplex;
  95         };
  96
  97         mdio1: mdio {
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100                 status = "okay";
 101
 102                 switch0: switch0@0 {
 103                         compatible = "marvell,mv88e6190";
 104                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 105                         pinctrl-names = "default";
 106                         reg = <0>;
 107                         eeprom-length = <65536>;
 108                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 109                         interrupt-parent = <&gpio3>;
 110                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 111                         interrupt-controller;
 112                         #interrupt-cells = <2>;
 113
 114                         ports {
 115                                 #address-cells = <1>;
 116                                 #size-cells = <0>;
 117
 118                                 port@0 {
 119                                         reg = <0>;
 120                                         label = "cpu";
 121                                         ethernet = <&fec1>;
 122
 123                                         fixed-link {
 124                                                 speed = <100>;
 125                                                 full-duplex;
 126                                         };
 127                                 };
 128
 129                                 port@1 {
 130                                         reg = <1>;
 131                                         label = "eth_cu_100_3";
 132                                 };
 133
 134                                 port@5 {
 135                                         reg = <5>;
 136                                         label = "eth_cu_1000_4";
 137                                 };
 138
 139                                 port@6 {
 140                                         reg = <6>;
 141                                         label = "eth_cu_1000_5";
 142                                 };
 143
 144                                 port@8 {
 145                                         reg = <8>;
 146                                         label = "eth_cu_1000_1";
 147                                 };
 148
 149                                 port@9 {
 150                                         reg = <9>;
 151                                         label = "eth_cu_1000_2";
 152                                         phy-handle = <&phy9>;
 153                                         phy-mode = "sgmii";
 154                                         managed = "in-band-status";
 155                                 };
 156                         };
 157
 158                         mdio1 {
 159                                 compatible = "marvell,mv88e6xxx-mdio-external";
 160                                 #address-cells = <1>;
 161                                 #size-cells = <0>;
 162
 163                                 phy9: phy9@0 {
 164                                         compatible = "ethernet-phy-ieee802.3-c45";
 165                                         pinctrl-0 = <&pinctrl_gpio_phy9>;
 166                                         pinctrl-names = "default";
 167                                         interrupt-parent = <&gpio2>;
 168                                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 169                                         reg = <0>;
 170                                 };
 171                         };
 172                 };
 173         };
 174 };
 175
 176 &i2c0 {
 177         clock-frequency = <100000>;
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_i2c0>;
 180         status = "okay";
 181
 182         gpio6: gpio-expander@22 {
 183                 compatible = "nxp,pca9554";
 184                 reg = <0x22>;
 185                 gpio-controller;
 186                 #gpio-cells = <2>;
 187         };
 188
 189         /* On SSMB */
 190         temperature-sensor@48 {
 191                 compatible = "national,lm75";
 192                 reg = <0x48>;
 193         };
 194
 195         /* On DSB */
 196         temperature-sensor@4d {
 197                 compatible = "national,lm75";
 198                 reg = <0x4d>;
 199         };
 200
 201         eeprom@50 {
 202                 compatible = "atmel,24c04";
 203                 reg = <0x50>;
 204                 label = "nameplate";
 205         };
 206
 207         eeprom@52 {
 208                 compatible = "atmel,24c04";
 209                 reg = <0x52>;
 210         };
 211 };
 212
 213 &snvsrtc {
 214         status = "disabled";
 215 };
 216
 217 &uart0 {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_uart0>;
 220         status = "okay";
 221 };
 222
 223 &iomuxc {
 224         pinctrl_dspi1: dspi1grp {
 225                 fsl,pins = <
 226                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 227                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 228                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 229                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 230                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 231                 >;
 232         };
 233
 234         pinctrl_esdhc0: esdhc0grp {
 235                 fsl,pins = <
 236                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 237                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 238                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 239                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 240                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 241                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 242                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 243                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 244                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 245                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 246                 >;
 247         };
 248
 249         pinctrl_esdhc1: esdhc1grp {
 250                 fsl,pins = <
 251                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 252                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 253                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 254                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 255                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 256                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 257                 >;
 258         };
 259
 260         pinctrl_fec1: fec1grp {
 261                 fsl,pins = <
 262                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 263                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 264                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 265                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 266                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 267                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 268                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 269                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 270                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 271                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 272                 >;
 273         };
 274
 275         pinctrl_gpio_phy9: pinctrl-gpio-phy9 {
 276                 fsl,pins = <
 277                         VF610_PAD_PTB24__GPIO_94                0x219d
 278                 >;
 279         };
 280
 281         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 282                 fsl,pins = <
 283                         VF610_PAD_PTE2__GPIO_107                0x31c2
 284                         VF610_PAD_PTB28__GPIO_98                0x219d
 285                 >;
 286         };
 287
 288         pinctrl_i2c0: i2c0grp {
 289                 fsl,pins = <
 290                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 291                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 292                 >;
 293         };
 294
 295         pinctrl_i2c1: i2c1grp {
 296                 fsl,pins = <
 297                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 298                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 299                 >;
 300         };
 301
 302         pinctrl_leds_debug: pinctrl-leds-debug {
 303                 fsl,pins = <
 304                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 305                 >;
 306         };
 307
 308         pinctrl_uart0: uart0grp {
 309                 fsl,pins = <
 310                         VF610_PAD_PTB10__UART0_TX               0x21a2
 311                         VF610_PAD_PTB11__UART0_RX               0x21a1
 312                 >;
 313         };
 314 };