arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB DTU board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * DTU - Digital Tapping Unit
   8  *
   9  * Copyright (C) 2015-2019 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB DTU Board";
  20         compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 reg = <0x80000000 0x20000000>;
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-0 = <&pinctrl_leds_debug>;
  34                 pinctrl-names = "default";
  35
  36                 led-debug {
  37                         label = "zii:green:debug1";
  38                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  39                         linux,default-trigger = "heartbeat";
  40                 };
  41         };
  42
  43         reg_vcc_3v3_mcu: regulator {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "vcc_3v3_mcu";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48         };
  49
  50         supply-voltage-monitor {
  51                 compatible = "iio-hwmon";
  52                 io-channels = <&adc0 8>, /* 12V_MAIN */
  53                               <&adc0 9>, /* +3.3V    */
  54                               <&adc1 8>, /* VCC_1V5  */
  55                               <&adc1 9>; /* VCC_1V2  */
  56         };
  57 };
  58
  59 &adc0 {
  60         vref-supply = <&reg_vcc_3v3_mcu>;
  61         status = "okay";
  62 };
  63
  64 &adc1 {
  65         vref-supply = <&reg_vcc_3v3_mcu>;
  66         status = "okay";
  67 };
  68
  69 &edma0 {
  70         status = "okay";
  71 };
  72
  73 &edma1 {
  74         status = "okay";
  75 };
  76
  77 &esdhc0 {
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_esdhc0>;
  80         bus-width = <8>;
  81         non-removable;
  82         no-1-8-v;
  83         keep-power-in-suspend;
  84         status = "okay";
  85 };
  86
  87 &esdhc1 {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_esdhc1>;
  90         bus-width = <4>;
  91         status = "okay";
  92 };
  93
  94 &fec1 {
  95         phy-mode = "rmii";
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_fec1>;
  98         status = "okay";
  99
 100         fixed-link {
 101                 speed = <100>;
 102                 full-duplex;
 103         };
 104
 105         mdio1: mdio {
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108                 status = "okay";
 109
 110                 switch0: switch0@0 {
 111                         compatible = "marvell,mv88e6190";
 112                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 113                         pinctrl-names = "default";
 114                         reg = <0>;
 115                         eeprom-length = <65536>;
 116                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 117                         interrupt-parent = <&gpio3>;
 118                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 119                         interrupt-controller;
 120                         #interrupt-cells = <2>;
 121
 122                         ports {
 123                                 #address-cells = <1>;
 124                                 #size-cells = <0>;
 125
 126                                 port@0 {
 127                                         reg = <0>;
 128                                         label = "cpu";
 129                                         ethernet = <&fec1>;
 130
 131                                         fixed-link {
 132                                                 speed = <100>;
 133                                                 full-duplex;
 134                                         };
 135                                 };
 136
 137                                 port@1 {
 138                                         reg = <1>;
 139                                         label = "eth_cu_100_3";
 140                                 };
 141
 142                                 port@5 {
 143                                         reg = <5>;
 144                                         label = "eth_cu_1000_4";
 145                                 };
 146
 147                                 port@6 {
 148                                         reg = <6>;
 149                                         label = "eth_cu_1000_5";
 150                                 };
 151
 152                                 port@8 {
 153                                         reg = <8>;
 154                                         label = "eth_cu_1000_1";
 155                                 };
 156
 157                                 port@9 {
 158                                         reg = <9>;
 159                                         label = "eth_cu_1000_2";
 160                                         phy-handle = <&phy9>;
 161                                         phy-mode = "sgmii";
 162                                         managed = "in-band-status";
 163                                 };
 164                         };
 165
 166                         mdio1 {
 167                                 compatible = "marvell,mv88e6xxx-mdio-external";
 168                                 #address-cells = <1>;
 169                                 #size-cells = <0>;
 170
 171                                 phy9: phy9@0 {
 172                                         compatible = "ethernet-phy-ieee802.3-c45";
 173                                         pinctrl-0 = <&pinctrl_gpio_phy9>;
 174                                         pinctrl-names = "default";
 175                                         interrupt-parent = <&gpio2>;
 176                                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 177                                         reg = <0>;
 178                                 };
 179                         };
 180                 };
 181         };
 182 };
 183
 184 &i2c0 {
 185         clock-frequency = <100000>;
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_i2c0>;
 188         status = "okay";
 189
 190         gpio6: gpio-expander@22 {
 191                 compatible = "nxp,pca9554";
 192                 reg = <0x22>;
 193                 gpio-controller;
 194                 #gpio-cells = <2>;
 195         };
 196
 197         /* On SSMB */
 198         temperature-sensor@48 {
 199                 compatible = "national,lm75";
 200                 reg = <0x48>;
 201         };
 202
 203         /* On DSB */
 204         temperature-sensor@4d {
 205                 compatible = "national,lm75";
 206                 reg = <0x4d>;
 207         };
 208
 209         eeprom@50 {
 210                 compatible = "atmel,24c04";
 211                 reg = <0x50>;
 212                 label = "nameplate";
 213         };
 214
 215         eeprom@52 {
 216                 compatible = "atmel,24c04";
 217                 reg = <0x52>;
 218         };
 219 };
 220
 221 &snvsrtc {
 222         status = "disabled";
 223 };
 224
 225 &uart0 {
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_uart0>;
 228         status = "okay";
 229 };
 230
 231 &iomuxc {
 232         pinctrl_dspi1: dspi1grp {
 233                 fsl,pins = <
 234                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 235                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 236                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 237                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 238                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 239                 >;
 240         };
 241
 242         pinctrl_esdhc0: esdhc0grp {
 243                 fsl,pins = <
 244                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 245                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 246                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 247                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 248                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 249                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 250                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 251                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 252                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 253                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 254                 >;
 255         };
 256
 257         pinctrl_esdhc1: esdhc1grp {
 258                 fsl,pins = <
 259                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 260                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 261                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 262                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 263                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 264                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 265                 >;
 266         };
 267
 268         pinctrl_fec1: fec1grp {
 269                 fsl,pins = <
 270                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 271                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 272                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 273                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 274                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 275                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 276                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 277                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 278                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 279                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 280                 >;
 281         };
 282
 283         pinctrl_gpio_phy9: pinctrl-gpio-phy9 {
 284                 fsl,pins = <
 285                         VF610_PAD_PTB24__GPIO_94                0x219d
 286                 >;
 287         };
 288
 289         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 290                 fsl,pins = <
 291                         VF610_PAD_PTE2__GPIO_107                0x31c2
 292                         VF610_PAD_PTB28__GPIO_98                0x219d
 293                 >;
 294         };
 295
 296         pinctrl_i2c0: i2c0grp {
 297                 fsl,pins = <
 298                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 299                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 300                 >;
 301         };
 302
 303         pinctrl_i2c1: i2c1grp {
 304                 fsl,pins = <
 305                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 306                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 307                 >;
 308         };
 309
 310         pinctrl_leds_debug: pinctrl-leds-debug {
 311                 fsl,pins = <
 312                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 313                 >;
 314         };
 315
 316         pinctrl_uart0: uart0grp {
 317                 fsl,pins = <
 318                         VF610_PAD_PTB10__UART0_TX               0x21a2
 319                         VF610_PAD_PTB11__UART0_RX               0x21a1
 320                 >;
 321         };
 322 };