arch/arm/boot/dts/vf610-zii-scu4-aib.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 //
   3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
   4
   5 /dts-v1/;
   6 #include "vf610.dtsi"
   7
   8 / {
   9         model = "ZII VF610 SCU4 AIB";
  10         compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
  11
  12         chosen {
  13                 stdout-path = &uart0;
  14         };
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0x20000000>;
  19         };
  20
  21         gpio-leds {
  22                 compatible = "gpio-leds";
  23                 pinctrl-0 = <&pinctrl_leds_debug>;
  24                 pinctrl-names = "default";
  25
  26                 debug {
  27                         label = "zii:green:debug1";
  28                         gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
  29                         linux,default-trigger = "heartbeat";
  30                 };
  31         };
  32
  33         mdio-mux {
  34                 compatible = "mdio-mux-gpio";
  35                 pinctrl-0 = <&pinctrl_mdio_mux>;
  36                 pinctrl-names = "default";
  37                 gpios = <&gpio4 4  GPIO_ACTIVE_HIGH
  38                          &gpio4 5  GPIO_ACTIVE_HIGH
  39                          &gpio3 30 GPIO_ACTIVE_HIGH
  40                          &gpio3 31 GPIO_ACTIVE_HIGH>;
  41                 mdio-parent-bus = <&mdio1>;
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 mdio_mux_1: mdio@1 {
  46                         reg = <1>;
  47                         #address-cells = <1>;
  48                         #size-cells = <0>;
  49
  50                         switch0: switch0@0 {
  51                                 compatible = "marvell,mv88e6190";
  52                                 reg = <0>;
  53                                 dsa,member = <0 0>;
  54                                 eeprom-length = <65536>;
  55
  56                                 ports {
  57                                         #address-cells = <1>;
  58                                         #size-cells = <0>;
  59
  60                                         port@0 {
  61                                                 reg = <0>;
  62                                                 label = "cpu";
  63                                                 ethernet = <&fec1>;
  64
  65                                                 fixed-link {
  66                                                         speed = <100>;
  67                                                         full-duplex;
  68                                                 };
  69                                         };
  70
  71                                         port@1 {
  72                                                 reg = <1>;
  73                                                 label = "aib2main_1";
  74                                         };
  75
  76                                         port@2 {
  77                                                 reg = <2>;
  78                                                 label = "aib2main_2";
  79                                         };
  80
  81                                         port@3 {
  82                                                 reg = <3>;
  83                                                 label = "eth_cu_1000_5";
  84                                         };
  85
  86                                         port@4 {
  87                                                 reg = <4>;
  88                                                 label = "eth_cu_1000_6";
  89                                         };
  90
  91                                         port@5 {
  92                                                 reg = <5>;
  93                                                 label = "eth_cu_1000_4";
  94                                         };
  95
  96                                         port@6 {
  97                                                 reg = <6>;
  98                                                 label = "eth_cu_1000_7";
  99                                         };
 100
 101                                         port@7 {
 102                                                 reg = <7>;
 103                                                 label = "modem_pic";
 104
 105                                                 fixed-link {
 106                                                         speed = <100>;
 107                                                         full-duplex;
 108                                                 };
 109                                         };
 110
 111                                         switch0port10: port@10 {
 112                                                 reg = <10>;
 113                                                 label = "dsa";
 114                                                 phy-mode = "xgmii";
 115                                                 link = <&switch1port10
 116                                                         &switch3port10
 117                                                         &switch2port10>;
 118                                         };
 119                                 };
 120                         };
 121                 };
 122
 123                 mdio_mux_2: mdio@2 {
 124                         reg = <2>;
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127
 128                         switch1: switch1@0 {
 129                                 compatible = "marvell,mv88e6190";
 130                                 reg = <0>;
 131                                 dsa,member = <0 1>;
 132                                 eeprom-length = <65536>;
 133
 134                                 ports {
 135                                         #address-cells = <1>;
 136                                         #size-cells = <0>;
 137
 138                                         port@1 {
 139                                                 reg = <1>;
 140                                                 label = "eth_cu_1000_3";
 141                                         };
 142
 143                                         port@2 {
 144                                                 reg = <2>;
 145                                                 label = "eth_cu_100_2";
 146                                         };
 147
 148                                         port@3 {
 149                                                 reg = <3>;
 150                                                 label = "eth_cu_100_3";
 151                                         };
 152
 153                                         switch1port9: port@9 {
 154                                                 reg = <9>;
 155                                                 label = "dsa";
 156                                                 phy-mode = "xgmii";
 157                                                 link = <&switch3port10
 158                                                         &switch2port10>;
 159                                         };
 160
 161                                         switch1port10: port@10 {
 162                                                 reg = <10>;
 163                                                 label = "dsa";
 164                                                 phy-mode = "xgmii";
 165                                                 link = <&switch0port10>;
 166                                         };
 167                                 };
 168                         };
 169                 };
 170
 171                 mdio_mux_4: mdio@4 {
 172                         reg = <4>;
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175
 176                         switch2: switch2@0 {
 177                                 compatible = "marvell,mv88e6190";
 178                                 reg = <0>;
 179                                 dsa,member = <0 2>;
 180                                 eeprom-length = <65536>;
 181
 182                                 ports {
 183                                         #address-cells = <1>;
 184                                         #size-cells = <0>;
 185
 186                                         port@1 {
 187                                                 reg = <1>;
 188                                                 label = "internal_j9";
 189                                         };
 190
 191                                         port@2 {
 192                                                 reg = <2>;
 193                                                 label = "eth_fc_1000_2";
 194                                                 phy-mode = "sgmii";
 195                                                 managed = "in-band-status";
 196                                                 sfp = <&sff1>;
 197                                         };
 198
 199                                         port@3 {
 200                                                 reg = <3>;
 201                                                 label = "eth_fc_1000_3";
 202                                                 phy-mode = "sgmii";
 203                                                 managed = "in-band-status";
 204                                                 sfp = <&sff2>;
 205                                         };
 206
 207                                         port@4 {
 208                                                 reg = <4>;
 209                                                 label = "eth_fc_1000_4";
 210                                                 phy-mode = "sgmii";
 211                                                 managed = "in-band-status";
 212                                                 sfp = <&sff3>;
 213                                         };
 214
 215                                         port@5 {
 216                                                 reg = <5>;
 217                                                 label = "eth_fc_1000_5";
 218                                                 phy-mode = "sgmii";
 219                                                 managed = "in-band-status";
 220                                                 sfp = <&sff4>;
 221                                         };
 222
 223                                         port@6 {
 224                                                 reg = <6>;
 225                                                 label = "eth_fc_1000_6";
 226                                                 phy-mode = "sgmii";
 227                                                 managed = "in-band-status";
 228                                                 sfp = <&sff5>;
 229                                         };
 230
 231                                         port@7 {
 232                                                 reg = <7>;
 233                                                 label = "eth_fc_1000_7";
 234                                                 phy-mode = "sgmii";
 235                                                 managed = "in-band-status";
 236                                                 sfp = <&sff6>;
 237                                         };
 238
 239                                         port@9 {
 240                                                 reg = <9>;
 241                                                 label = "eth_fc_1000_1";
 242                                                 phy-mode = "sgmii";
 243                                                 managed = "in-band-status";
 244                                                 sfp = <&sff0>;
 245                                         };
 246
 247                                         switch2port10: port@10 {
 248                                                 reg = <10>;
 249                                                 label = "dsa";
 250                                                 phy-mode = "2500base-x";
 251                                                 link = <&switch3port9
 252                                                         &switch1port9
 253                                                         &switch0port10>;
 254                                         };
 255                                 };
 256                         };
 257                 };
 258
 259                 mdio_mux_8: mdio@8 {
 260                         reg = <8>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263
 264                         switch3: switch3@0 {
 265                                 compatible = "marvell,mv88e6190";
 266                                 reg = <0>;
 267                                 dsa,member = <0 3>;
 268                                 eeprom-length = <65536>;
 269
 270                                 ports {
 271                                         #address-cells = <1>;
 272                                         #size-cells = <0>;
 273
 274                                         port@1 {
 275                                                 reg = <1>;
 276                                                 label = "internal_j8";
 277                                         };
 278
 279                                         port@2 {
 280                                                 reg = <2>;
 281                                                 label = "eth_fc_1000_8";
 282                                                 phy-mode = "sgmii";
 283                                                 managed = "in-band-status";
 284                                                 sfp = <&sff7>;
 285                                         };
 286
 287                                         port@3 {
 288                                                 reg = <3>;
 289                                                 label = "eth_fc_1000_9";
 290                                                 phy-mode = "sgmii";
 291                                                 managed = "in-band-status";
 292                                                 sfp = <&sff8>;
 293                                         };
 294
 295                                         port@4 {
 296                                                 reg = <4>;
 297                                                 label = "eth_fc_1000_10";
 298                                                 phy-mode = "sgmii";
 299                                                 managed = "in-band-status";
 300                                                 sfp = <&sff9>;
 301                                         };
 302
 303                                         switch3port9: port@9 {
 304                                                 reg = <9>;
 305                                                 label = "dsa";
 306                                                 phy-mode = "2500base-x";
 307                                                 link = <&switch2port10>;
 308                                         };
 309
 310                                         switch3port10: port@10 {
 311                                                 reg = <10>;
 312                                                 label = "dsa";
 313                                                 phy-mode = "xgmii";
 314                                                 link = <&switch1port9
 315                                                         &switch0port10>;
 316                                         };
 317                                 };
 318                         };
 319                 };
 320         };
 321
 322         sff0: sff0 {
 323                 compatible = "sff,sff";
 324                 i2c-bus = <&sff0_i2c>;
 325                 los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
 326                 tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
 327         };
 328
 329         sff1: sff1 {
 330                 compatible = "sff,sff";
 331                 i2c-bus = <&sff1_i2c>;
 332                 los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
 333                 tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 334         };
 335
 336         sff2: sff2 {
 337                 compatible = "sff,sff";
 338                 i2c-bus = <&sff2_i2c>;
 339                 los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
 340                 tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
 341         };
 342
 343         sff3: sff3 {
 344                 compatible = "sff,sff";
 345                 i2c-bus = <&sff3_i2c>;
 346                 los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
 347                 tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
 348         };
 349
 350         sff4: sff4 {
 351                 compatible = "sff,sff";
 352                 i2c-bus = <&sff4_i2c>;
 353                 los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
 354                 tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
 355         };
 356
 357         sff5: sff5 {
 358                 compatible = "sff,sff";
 359                 i2c-bus = <&sff5_i2c>;
 360                 los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
 361                 tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>;
 362         };
 363
 364         sff6: sff6 {
 365                 compatible = "sff,sff";
 366                 i2c-bus = <&sff6_i2c>;
 367                 los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
 368                 tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 369         };
 370
 371         sff7: sff7 {
 372                 compatible = "sff,sff";
 373                 i2c-bus = <&sff7_i2c>;
 374                 los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>;
 375                 tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
 376         };
 377
 378         sff8: sff8 {
 379                 compatible = "sff,sff";
 380                 i2c-bus = <&sff8_i2c>;
 381                 los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>;
 382                 tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 383         };
 384
 385         sff9: sff9 {
 386                 compatible = "sff,sff";
 387                 i2c-bus = <&sff9_i2c>;
 388                 los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>;
 389                 tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
 390         };
 391
 392         reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
 393                 compatible = "regulator-fixed";
 394                 regulator-name = "vcc_3v3_mcu";
 395                 regulator-min-microvolt = <3300000>;
 396                 regulator-max-microvolt = <3300000>;
 397         };
 398 };
 399
 400 &dspi0 {
 401         pinctrl-0 = <&pinctrl_dspi0>;
 402         pinctrl-names = "default";
 403         bus-num = <0>;
 404         status = "okay";
 405
 406         adc@5 {
 407                 compatible = "holt,hi8435";
 408                 reg = <5>;
 409                 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
 410                 spi-max-frequency = <1000000>;
 411         };
 412 };
 413
 414 &dspi1 {
 415         bus-num = <1>;
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&pinctrl_dspi1>;
 418         status = "okay";
 419
 420         spi-flash@0 {
 421                 #address-cells = <1>;
 422                 #size-cells = <1>;
 423                 compatible = "jedec,spi-nor";
 424                 reg = <0>;
 425                 spi-max-frequency = <50000000>;
 426
 427                 partition@0 {
 428                         label = "m25p128-0";
 429                         reg = <0x0 0x01000000>;
 430                 };
 431         };
 432
 433         spi-flash@1 {
 434                 #address-cells = <1>;
 435                 #size-cells = <1>;
 436                 compatible = "jedec,spi-nor";
 437                 reg = <1>;
 438                 spi-max-frequency = <50000000>;
 439
 440                 partition@0 {
 441                         label = "m25p128-1";
 442                         reg = <0x0 0x01000000>;
 443                 };
 444         };
 445 };
 446
 447 &adc0 {
 448         vref-supply = <&reg_vcc_3v3_mcu>;
 449         status = "okay";
 450 };
 451
 452 &adc1 {
 453         vref-supply = <&reg_vcc_3v3_mcu>;
 454         status = "okay";
 455 };
 456
 457 &edma0 {
 458         status = "okay";
 459 };
 460
 461 &edma1 {
 462         status = "okay";
 463 };
 464
 465 &esdhc0 {
 466         pinctrl-names = "default";
 467         pinctrl-0 = <&pinctrl_esdhc0>;
 468         bus-width = <8>;
 469         non-removable;
 470         no-1-8-v;
 471         no-sd;
 472         no-sdio;
 473         keep-power-in-suspend;
 474         status = "okay";
 475 };
 476
 477 &esdhc1 {
 478         pinctrl-names = "default";
 479         pinctrl-0 = <&pinctrl_esdhc1>;
 480         bus-width = <4>;
 481         no-sdio;
 482         status = "okay";
 483 };
 484
 485 &fec1 {
 486         phy-mode = "rmii";
 487         pinctrl-names = "default";
 488         pinctrl-0 = <&pinctrl_fec1>;
 489         status = "okay";
 490
 491         fixed-link {
 492                    speed = <100>;
 493                    full-duplex;
 494         };
 495
 496         mdio1: mdio {
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499         };
 500 };
 501
 502 &i2c0 {
 503         clock-frequency = <100000>;
 504         pinctrl-names = "default";
 505         pinctrl-0 = <&pinctrl_i2c0>;
 506         status = "okay";
 507
 508         gpio5: io-expander@20 {
 509                 compatible = "nxp,pca9554";
 510                 reg = <0x20>;
 511                 gpio-controller;
 512                 #gpio-cells = <2>;
 513         };
 514
 515         gpio6: io-expander@22 {
 516                 compatible = "nxp,pca9554";
 517                 reg = <0x22>;
 518                 gpio-controller;
 519                 #gpio-cells = <2>;
 520         };
 521
 522         lm75@48 {
 523                 compatible = "national,lm75";
 524                 reg = <0x48>;
 525         };
 526
 527         eeprom@50 {
 528                 compatible = "atmel,24c04";
 529                 reg = <0x50>;
 530         };
 531
 532         eeprom@52 {
 533                 compatible = "atmel,24c04";
 534                 reg = <0x52>;
 535         };
 536
 537         ds1682@6b {
 538                 compatible = "dallas,ds1682";
 539                 reg = <0x6b>;
 540         };
 541 };
 542
 543 &i2c1 {
 544         clock-frequency = <100000>;
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&pinctrl_i2c1>;
 547         status = "okay";
 548
 549         adt7411@4a {
 550                 compatible = "adi,adt7411";
 551                 reg = <0x4a>;
 552         };
 553 };
 554
 555 &i2c2 {
 556         clock-frequency = <100000>;
 557         pinctrl-names = "default";
 558         pinctrl-0 = <&pinctrl_i2c2>;
 559         status = "okay";
 560
 561         gpio9: sx1503q@20 {
 562                 compatible = "semtech,sx1503q";
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&pinctrl_sx1503_20>;
 565                 #gpio-cells = <2>;
 566                 reg = <0x20>;
 567                 gpio-controller;
 568                 interrupt-parent = <&gpio1>;
 569                 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
 570         };
 571
 572         lm75@4e {
 573                 compatible = "national,lm75";
 574                 reg = <0x4e>;
 575         };
 576
 577         lm75@4f {
 578                 compatible = "national,lm75";
 579                 reg = <0x4f>;
 580         };
 581
 582         gpio7: io-expander@23 {
 583                 compatible = "nxp,pca9555";
 584                 gpio-controller;
 585                 #gpio-cells = <2>;
 586                 reg = <0x23>;
 587         };
 588
 589         adt7411@4a {
 590                 compatible = "adi,adt7411";
 591                 reg = <0x4a>;
 592         };
 593
 594         at24c08@54 {
 595                 compatible = "atmel,24c08";
 596                 reg = <0x54>;
 597         };
 598
 599         tca9548@70 {
 600                 compatible = "nxp,pca9548";
 601                 pinctrl-names = "default";
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 reg = <0x70>;
 605                 i2c-mux-idle-disconnect;
 606
 607                 sff0_i2c: i2c@1 {
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         reg = <1>;
 611                 };
 612
 613                 sff1_i2c: i2c@2 {
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                         reg = <2>;
 617                 };
 618
 619                 sff2_i2c: i2c@3 {
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                         reg = <3>;
 623                 };
 624
 625                 sff3_i2c: i2c@4 {
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628                         reg = <4>;
 629                 };
 630
 631                 sff4_i2c: i2c@5 {
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634                         reg = <5>;
 635                 };
 636         };
 637
 638         tca9548@71 {
 639                 compatible = "nxp,pca9548";
 640                 pinctrl-names = "default";
 641                 reg = <0x71>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 i2c-mux-idle-disconnect;
 645
 646                 sff5_i2c: i2c@1 {
 647                         #address-cells = <1>;
 648                         #size-cells = <0>;
 649                         reg = <1>;
 650                 };
 651
 652                 sff6_i2c: i2c@2 {
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         reg = <2>;
 656                 };
 657
 658                 sff7_i2c: i2c@3 {
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                         reg = <3>;
 662                 };
 663
 664                 sff8_i2c: i2c@4 {
 665                         #address-cells = <1>;
 666                         #size-cells = <0>;
 667                         reg = <4>;
 668                 };
 669
 670                 sff9_i2c: i2c@5 {
 671                         #address-cells = <1>;
 672                         #size-cells = <0>;
 673                         reg = <5>;
 674                 };
 675         };
 676 };
 677
 678 &snvsrtc {
 679         status = "disabled";
 680 };
 681
 682 &uart0 {
 683         pinctrl-names = "default";
 684         pinctrl-0 = <&pinctrl_uart0>;
 685         status = "okay";
 686 };
 687
 688 &uart1 {
 689         linux,rs485-enabled-at-boot-time;
 690         pinctrl-names = "default";
 691         pinctrl-0 = <&pinctrl_uart1>;
 692         rs485-rts-delay = <0 200>;
 693         status = "okay";
 694 };
 695
 696 &uart2 {
 697         linux,rs485-enabled-at-boot-time;
 698         pinctrl-names = "default";
 699         pinctrl-0 = <&pinctrl_uart2>;
 700         rs485-rts-delay = <0 200>;
 701         status = "okay";
 702 };
 703
 704 &iomuxc {
 705         pinctrl_dspi0: dspi0grp {
 706                 fsl,pins = <
 707                         VF610_PAD_PTB19__DSPI0_CS0              0x1182
 708                         VF610_PAD_PTB18__DSPI0_CS1              0x1182
 709                         VF610_PAD_PTB13__DSPI0_CS4              0x1182
 710                         VF610_PAD_PTB12__DSPI0_CS5              0x1182
 711                         VF610_PAD_PTB20__DSPI0_SIN              0x1181
 712                         VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 713                         VF610_PAD_PTB22__DSPI0_SCK              0x1182
 714                 >;
 715         };
 716
 717         pinctrl_dspi1: dspi1grp {
 718                 fsl,pins = <
 719                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 720                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 721                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 722                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 723                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 724                 >;
 725         };
 726
 727         pinctrl_dspi2: dspi2gpio {
 728                 fsl,pins = <
 729                         VF610_PAD_PTD30__GPIO_64                0x33e2
 730                         VF610_PAD_PTD29__GPIO_65                0x33e1
 731                         VF610_PAD_PTD28__GPIO_66                0x33e2
 732                         VF610_PAD_PTD27__GPIO_67                0x33e2
 733                         VF610_PAD_PTD26__GPIO_68                0x31c2
 734                 >;
 735         };
 736
 737         pinctrl_esdhc0: esdhc0grp {
 738                 fsl,pins = <
 739                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 740                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 741                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 742                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 743                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 744                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 745                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 746                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 747                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 748                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 749                 >;
 750         };
 751
 752         pinctrl_esdhc1: esdhc1grp {
 753                 fsl,pins = <
 754                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 755                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 756                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 757                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 758                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 759                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 760                 >;
 761         };
 762
 763         pinctrl_fec1: fec1grp {
 764                 fsl,pins = <
 765                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 766                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 767                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 768                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 769                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 770                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 771                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 772                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 773                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 774                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 775                 >;
 776         };
 777
 778         pinctrl_i2c0: i2c0grp {
 779                 fsl,pins = <
 780                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 781                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 782                 >;
 783         };
 784
 785         pinctrl_i2c1: i2c1grp {
 786                 fsl,pins = <
 787                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 788                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 789                 >;
 790         };
 791
 792         pinctrl_i2c2: i2c2grp {
 793                 fsl,pins = <
 794                         VF610_PAD_PTA22__I2C2_SCL               0x37ff
 795                         VF610_PAD_PTA23__I2C2_SDA               0x37ff
 796                 >;
 797         };
 798
 799         pinctrl_leds_debug: pinctrl-leds-debug {
 800                 fsl,pins = <
 801                          VF610_PAD_PTB26__GPIO_96               0x31c2
 802                    >;
 803         };
 804
 805         pinctrl_mdio_mux: pinctrl-mdio-mux {
 806                 fsl,pins = <
 807                         VF610_PAD_PTE27__GPIO_132               0x31c2
 808                         VF610_PAD_PTE28__GPIO_133               0x31c2
 809                         VF610_PAD_PTE21__GPIO_126               0x31c2
 810                         VF610_PAD_PTE22__GPIO_127               0x31c2
 811                 >;
 812         };
 813
 814         pinctrl_qspi0: qspi0grp {
 815                 fsl,pins = <
 816                         VF610_PAD_PTD7__QSPI0_B_QSCK            0x31c3
 817                         VF610_PAD_PTD8__QSPI0_B_CS0             0x31ff
 818                         VF610_PAD_PTD9__QSPI0_B_DATA3           0x31c3
 819                         VF610_PAD_PTD10__QSPI0_B_DATA2          0x31c3
 820                         VF610_PAD_PTD11__QSPI0_B_DATA1          0x31c3
 821                         VF610_PAD_PTD12__QSPI0_B_DATA0          0x31c3
 822                 >;
 823         };
 824
 825         pinctrl_sx1503_20: pinctrl-sx1503-20 {
 826                 fsl,pins = <
 827                         VF610_PAD_PTD31__GPIO_63                0x219d
 828                         >;
 829         };
 830
 831         pinctrl_uart0: uart0grp {
 832                 fsl,pins = <
 833                         VF610_PAD_PTB10__UART0_TX               0x21a2
 834                         VF610_PAD_PTB11__UART0_RX               0x21a1
 835                 >;
 836         };
 837
 838         pinctrl_uart1: uart1grp {
 839                 fsl,pins = <
 840                         VF610_PAD_PTB23__UART1_TX               0x21a2
 841                         VF610_PAD_PTB24__UART1_RX               0x21a1
 842                         VF610_PAD_PTB25__UART1_RTS              0x21a2  /* Used as DE signal for the RS-485 transceiver */
 843                 >;
 844         };
 845
 846         pinctrl_uart2: uart2grp {
 847                 fsl,pins = <
 848                         VF610_PAD_PTD0__UART2_TX                0x21a2
 849                         VF610_PAD_PTD1__UART2_RX                0x21a1
 850                         VF610_PAD_PTD2__UART2_RTS               0x21a2 /* Used as DE signal for the RS-485 transceiver */
 851                 >;
 852         };
 853 };