1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2018 Zodiac Inflight Innovations
11 model = "ZII VF610 CFU1 Board";
12 compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610";
19 device_type = "memory";
20 reg = <0x80000000 0x20000000>;
24 compatible = "gpio-leds";
25 pinctrl-0 = <&pinctrl_leds_debug>;
26 pinctrl-names = "default";
29 label = "zii:green:debug1";
30 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
31 linux,default-trigger = "heartbeat";
35 label = "zii:red:fail";
36 gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
37 default-state = "off";
41 label = "zii:green:status";
42 gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
43 default-state = "off";
47 label = "zii:green:debug_a";
48 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
49 default-state = "off";
53 label = "zii:green:debug_b";
54 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
55 default-state = "off";
59 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
60 compatible = "regulator-fixed";
61 regulator-name = "vcc_3v3_mcu";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
67 compatible = "sff,sff";
68 pinctrl-0 = <&pinctrl_optical>;
69 pinctrl-names = "default";
71 los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
72 tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
75 supply-voltage-monitor {
76 compatible = "iio-hwmon";
77 io-channels = <&adc0 8>, /* 28VDC_IN */
78 <&adc0 9>, /* +3.3V */
79 <&adc1 8>, /* VCC_1V5 */
80 <&adc1 9>; /* VCC_1V2 */
85 vref-supply = <®_vcc_3v3_mcu>;
90 vref-supply = <®_vcc_3v3_mcu>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_dspi1>;
99 * Some CFU1s come with SPI-NOR chip DNPed, so we leave this
100 * node disabled by default and rely on bootloader to enable
101 * it when appropriate.
106 #address-cells = <1>;
108 compatible = "m25p128", "jedec,spi-nor";
110 spi-max-frequency = <50000000>;
114 reg = <0x0 0x01000000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_esdhc0>;
133 keep-power-in-suspend;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_esdhc1>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_fec1>;
159 #address-cells = <1>;
164 compatible = "marvell,mv88e6085";
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_switch>;
168 eeprom-length = <512>;
169 interrupt-parent = <&gpio3>;
170 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
176 #address-cells = <1>;
181 label = "eth_cu_1000_1";
186 label = "eth_cu_1000_2";
191 label = "eth_cu_1000_3";
196 label = "eth_fc_1000_1";
197 phy-mode = "1000base-x";
198 managed = "in-band-status";
218 clock-frequency = <100000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c0>;
224 compatible = "nxp,pca9554";
230 compatible = "national,lm75";
235 compatible = "atmel,24c04";
241 compatible = "atmel,24c04";
248 clock-frequency = <100000>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_i2c1>;
254 compatible = "zii,rave-wdt";
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_uart0>;
270 pinctrl_dspi1: dspi1grp {
272 VF610_PAD_PTD5__DSPI1_CS0 0x1182
273 VF610_PAD_PTC6__DSPI1_SIN 0x1181
274 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
275 VF610_PAD_PTC8__DSPI1_SCK 0x1182
279 pinctrl_esdhc0: esdhc0grp {
281 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
282 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
283 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
284 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
285 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
286 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
287 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
288 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
289 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
290 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
294 pinctrl_esdhc1: esdhc1grp {
296 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
297 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
298 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
299 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
300 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
301 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
305 pinctrl_fec1: fec1grp {
307 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
308 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe
309 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
310 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
311 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
312 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
313 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
314 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
315 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
316 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
320 pinctrl_i2c0: i2c0grp {
322 VF610_PAD_PTB14__I2C0_SCL 0x37ff
323 VF610_PAD_PTB15__I2C0_SDA 0x37ff
327 pinctrl_i2c1: i2c1grp {
329 VF610_PAD_PTB16__I2C1_SCL 0x37ff
330 VF610_PAD_PTB17__I2C1_SDA 0x37ff
334 pinctrl_leds_debug: pinctrl-leds-debug {
336 VF610_PAD_PTD3__GPIO_82 0x31c2
337 VF610_PAD_PTE3__GPIO_108 0x31c2
338 VF610_PAD_PTE4__GPIO_109 0x31c2
339 VF610_PAD_PTE5__GPIO_110 0x31c2
340 VF610_PAD_PTE6__GPIO_111 0x31c2
344 pinctrl_optical: optical-grp {
347 VF610_PAD_PTE27__GPIO_132 0x3061
349 /* SFF Transmit disable output */
350 VF610_PAD_PTE13__GPIO_118 0x3043
354 pinctrl_switch: switch-grp {
356 VF610_PAD_PTB28__GPIO_98 0x3061
357 VF610_PAD_PTE2__GPIO_107 0x1042
361 pinctrl_uart0: uart0grp {
363 VF610_PAD_PTB10__UART0_TX 0x21a2
364 VF610_PAD_PTB11__UART0_RX 0x21a1