arch/arm/boot/dts/vf610-zii-cfu1.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Copyright (C) 2018 Zodiac Inflight Innovations
   5  */
   6
   7 /dts-v1/;
   8 #include "vf610.dtsi"
   9
  10 / {
  11         model = "ZII VF610 CFU1 Board";
  12         compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610";
  13
  14         chosen {
  15                 stdout-path = &uart0;
  16         };
  17
  18         memory@80000000 {
  19                 device_type = "memory";
  20                 reg = <0x80000000 0x20000000>;
  21         };
  22
  23         gpio-leds {
  24                 compatible = "gpio-leds";
  25                 pinctrl-0 = <&pinctrl_leds_debug>;
  26                 pinctrl-names = "default";
  27
  28                 led-debug {
  29                         label = "zii:green:debug1";
  30                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  31                         linux,default-trigger = "heartbeat";
  32                 };
  33
  34                 led-fail {
  35                         label = "zii:red:fail";
  36                         gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
  37                         default-state = "off";
  38                 };
  39
  40                 led-status {
  41                         label = "zii:green:status";
  42                         gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  43                         default-state = "off";
  44                 };
  45
  46                 led-debug-a {
  47                         label = "zii:green:debug_a";
  48                         gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
  49                         default-state = "off";
  50                 };
  51
  52                 led-debug-b {
  53                         label = "zii:green:debug_b";
  54                         gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
  55                         default-state = "off";
  56                 };
  57         };
  58
  59         reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
  60                  compatible = "regulator-fixed";
  61                  regulator-name = "vcc_3v3_mcu";
  62                  regulator-min-microvolt = <3300000>;
  63                  regulator-max-microvolt = <3300000>;
  64         };
  65
  66         sff: sfp {
  67                 compatible = "sff,sff";
  68                 pinctrl-0 = <&pinctrl_optical>;
  69                 pinctrl-names = "default";
  70                 i2c-bus = <&i2c0>;
  71                 los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
  72                 tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  73         };
  74
  75         supply-voltage-monitor {
  76                 compatible = "iio-hwmon";
  77                 io-channels = <&adc0 8>, /* 28VDC_IN */
  78                               <&adc0 9>, /* +3.3V    */
  79                               <&adc1 8>, /* VCC_1V5  */
  80                               <&adc1 9>; /* VCC_1V2  */
  81         };
  82 };
  83
  84 &adc0 {
  85         vref-supply = <&reg_vcc_3v3_mcu>;
  86         status = "okay";
  87 };
  88
  89 &adc1 {
  90         vref-supply = <&reg_vcc_3v3_mcu>;
  91         status = "okay";
  92 };
  93
  94 &dspi1 {
  95         bus-num = <1>;
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_dspi1>;
  98         /*
  99          * Some CFU1s come with SPI-NOR chip DNPed, so we leave this
 100          * node disabled by default and rely on bootloader to enable
 101          * it when appropriate.
 102          */
 103         status = "disabled";
 104
 105         flash@0 {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 compatible = "m25p128", "jedec,spi-nor";
 109                 reg = <0>;
 110                 spi-max-frequency = <50000000>;
 111
 112                 partition@0 {
 113                         label = "m25p128-0";
 114                         reg = <0x0 0x01000000>;
 115                 };
 116         };
 117 };
 118
 119 &edma0 {
 120         status = "okay";
 121 };
 122
 123 &edma1 {
 124         status = "okay";
 125 };
 126
 127 &esdhc0 {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_esdhc0>;
 130         bus-width = <8>;
 131         non-removable;
 132         no-1-8-v;
 133         keep-power-in-suspend;
 134         no-sdio;
 135         no-sd;
 136         status = "okay";
 137 };
 138
 139 &esdhc1 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_esdhc1>;
 142         bus-width = <4>;
 143         no-sdio;
 144         status = "okay";
 145 };
 146
 147 &fec1 {
 148         phy-mode = "rmii";
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_fec1>;
 151         status = "okay";
 152
 153         fixed-link {
 154                 speed = <100>;
 155                 full-duplex;
 156         };
 157
 158         mdio1: mdio {
 159                 #address-cells = <1>;
 160                 #size-cells = <0>;
 161                 status = "okay";
 162
 163                 switch0: switch0@0 {
 164                         compatible = "marvell,mv88e6085";
 165                         pinctrl-names = "default";
 166                         pinctrl-0 = <&pinctrl_switch>;
 167                         reg = <0>;
 168                         eeprom-length = <512>;
 169                         interrupt-parent = <&gpio3>;
 170                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 174
 175                         ports {
 176                                 #address-cells = <1>;
 177                                 #size-cells = <0>;
 178
 179                                 port@0 {
 180                                         reg = <0>;
 181                                         label = "eth_cu_1000_1";
 182                                 };
 183
 184                                 port@1 {
 185                                         reg = <1>;
 186                                         label = "eth_cu_1000_2";
 187                                 };
 188
 189                                 port@2 {
 190                                         reg = <2>;
 191                                         label = "eth_cu_1000_3";
 192                                 };
 193
 194                                 port@5 {
 195                                         reg = <5>;
 196                                         label = "eth_fc_1000_1";
 197                                         phy-mode = "1000base-x";
 198                                         managed = "in-band-status";
 199                                         sfp = <&sff>;
 200                                 };
 201
 202                                 port@6 {
 203                                         reg = <6>;
 204                                         label = "cpu";
 205                                         ethernet = <&fec1>;
 206
 207                                         fixed-link {
 208                                                 speed = <100>;
 209                                                 full-duplex;
 210                                         };
 211                                 };
 212                         };
 213                 };
 214         };
 215 };
 216
 217 &i2c0 {
 218         clock-frequency = <100000>;
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_i2c0>;
 221         status = "okay";
 222
 223         io-expander@22 {
 224                 compatible = "nxp,pca9554";
 225                 reg = <0x22>;
 226                 gpio-controller;
 227         };
 228
 229         lm75@48 {
 230                 compatible = "national,lm75";
 231                 reg = <0x48>;
 232         };
 233
 234         eeprom@52 {
 235                 compatible = "atmel,24c04";
 236                 reg = <0x52>;
 237                 label = "nvm";
 238         };
 239
 240         eeprom@54 {
 241                 compatible = "atmel,24c04";
 242                 reg = <0x54>;
 243                 label = "nameplate";
 244         };
 245 };
 246
 247 &i2c1 {
 248         clock-frequency = <100000>;
 249         pinctrl-names = "default";
 250         pinctrl-0 = <&pinctrl_i2c1>;
 251         status = "okay";
 252
 253         watchdog@38 {
 254                 compatible = "zii,rave-wdt";
 255                 reg = <0x38>;
 256         };
 257 };
 258
 259 &snvsrtc {
 260         status = "disabled";
 261 };
 262
 263 &uart0 {
 264         pinctrl-names = "default";
 265         pinctrl-0 = <&pinctrl_uart0>;
 266         status = "okay";
 267 };
 268
 269 &iomuxc {
 270         pinctrl_dspi1: dspi1grp {
 271                 fsl,pins = <
 272                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 273                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 274                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 275                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 276                 >;
 277         };
 278
 279         pinctrl_esdhc0: esdhc0grp {
 280                 fsl,pins = <
 281                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 282                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 283                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 284                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 285                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 286                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 287                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 288                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 289                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 290                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 291                 >;
 292         };
 293
 294         pinctrl_esdhc1: esdhc1grp {
 295                 fsl,pins = <
 296                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 297                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 298                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 299                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 300                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 301                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 302                 >;
 303         };
 304
 305         pinctrl_fec1: fec1grp {
 306                 fsl,pins = <
 307                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 308                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30fe
 309                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 310                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 311                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 312                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 313                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 314                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 315                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 316                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 317                 >;
 318         };
 319
 320         pinctrl_i2c0: i2c0grp {
 321                 fsl,pins = <
 322                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 323                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 324                 >;
 325         };
 326
 327         pinctrl_i2c1: i2c1grp {
 328                 fsl,pins = <
 329                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 330                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 331                 >;
 332         };
 333
 334         pinctrl_leds_debug: pinctrl-leds-debug {
 335                 fsl,pins = <
 336                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 337                         VF610_PAD_PTE3__GPIO_108                0x31c2
 338                         VF610_PAD_PTE4__GPIO_109                0x31c2
 339                         VF610_PAD_PTE5__GPIO_110                0x31c2
 340                         VF610_PAD_PTE6__GPIO_111                0x31c2
 341                 >;
 342         };
 343
 344         pinctrl_optical: optical-grp {
 345                 fsl,pins = <
 346                 /* SFF SD input */
 347                 VF610_PAD_PTE27__GPIO_132       0x3061
 348
 349                 /* SFF Transmit disable output */
 350                 VF610_PAD_PTE13__GPIO_118       0x3043
 351                 >;
 352         };
 353
 354         pinctrl_switch: switch-grp {
 355                 fsl,pins = <
 356                         VF610_PAD_PTB28__GPIO_98                0x3061
 357                         VF610_PAD_PTE2__GPIO_107                0x1042
 358                 >;
 359         };
 360
 361         pinctrl_uart0: uart0grp {
 362                 fsl,pins = <
 363                         VF610_PAD_PTB10__UART0_TX               0x21a2
 364                         VF610_PAD_PTB11__UART0_RX               0x21a1
 365                 >;
 366         };
 367 };