1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
11 model = "Liebherr BK4 controller";
12 compatible = "lwn,bk4", "fsl,vf610";
19 device_type = "memory";
20 reg = <0x80000000 0x8000000>;
23 audio_ext: oscillator-audio {
24 compatible = "fixed-clock";
26 clock-frequency = <24576000>;
29 enet_ext: oscillator-ethernet {
30 compatible = "fixed-clock";
32 clock-frequency = <50000000>;
36 compatible = "gpio-leds";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_gpio_leds>;
43 gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
45 linux,default-trigger = "heartbeat";
49 reg_3p3v: regulator-3p3v {
50 compatible = "regulator-fixed";
51 regulator-name = "3P3V";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
57 reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
58 compatible = "regulator-fixed";
59 regulator-name = "vcc_3v3_mcu";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
66 vref-supply = <®_vcc_3v3_mcu>;
71 vref-supply = <®_vcc_3v3_mcu>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_can0>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_can1>;
88 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
89 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_dspi0>;
99 compatible = "lwn,bk4";
100 spi-max-frequency = <30000000>;
102 fsl,spi-cs-sck-delay = <200>;
103 fsl,spi-sck-cs-delay = <400>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_dspi3>;
115 compatible = "lwn,bk4";
116 spi-max-frequency = <30000000>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_esdhc1>;
133 cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
139 phy-handle = <ðphy0>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_fec0>;
145 #address-cells = <1>;
148 ethphy0: ethernet-phy@1 {
150 clocks = <&clks VF610_CLK_ENET_50M>;
151 clock-names = "rmii-ref";
158 phy-handle = <ðphy1>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_fec1>;
164 #address-cells = <1>;
167 ethphy1: ethernet-phy@1 {
169 clocks = <&clks VF610_CLK_ENET_50M>;
170 clock-names = "rmii-ref";
176 clock-frequency = <400000>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c2>;
181 at24c256: eeprom@50 {
182 compatible = "atmel,24c256";
187 compatible = "st,m41t62";
193 assigned-clocks = <&clks VF610_CLK_NFC>;
194 assigned-clock-rates = <33000000>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_nfc>;
200 compatible = "fsl,vf610-nfc-nandcs";
202 #address-cells = <1>;
204 nand-bus-width = <16>;
205 nand-ecc-mode = "hw";
206 nand-ecc-strength = <24>;
207 nand-ecc-step-size = <2048>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_qspi0>;
217 n25q128a13_4: flash@0 {
218 compatible = "n25q128a13", "jedec,spi-nor";
219 #address-cells = <1>;
221 spi-max-frequency = <66000000>;
222 spi-rx-bus-width = <4>;
226 n25q128a13_2: flash@1 {
227 compatible = "n25q128a13", "jedec,spi-nor";
228 #address-cells = <1>;
230 spi-max-frequency = <66000000>;
231 spi-rx-bus-width = <2>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_uart0>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_uart2>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart3>;
261 disable-over-current;
266 disable-over-current;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_hog>;
290 pinctrl_hog: hoggrp {
292 /* One_Wire_PSU_EN */
293 VF610_PAD_PTC29__GPIO_102 0x1183
295 VF610_PAD_PTB26__GPIO_96 0x1183
297 VF610_PAD_PTE14__GPIO_119 0x1183
298 VF610_PAD_PTE4__GPIO_109 0x1181
300 VF610_PAD_PTC31__GPIO_104 0x1181
301 VF610_PAD_PTA7__GPIO_134 0x1181
302 VF610_PAD_PTD9__GPIO_88 0x1181
303 VF610_PAD_PTE1__GPIO_106 0x1183
304 VF610_PAD_PTB2__GPIO_24 0x1181
305 VF610_PAD_PTB3__GPIO_25 0x1181
306 VF610_PAD_PTB1__GPIO_23 0x1181
308 VF610_PAD_PTE19__GPIO_124 0x1183
309 /* SDHC Overcurrent */
310 VF610_PAD_PTB23__GPIO_93 0x1181
312 VF610_PAD_PTE2__GPIO_107 0x1181
313 VF610_PAD_PTE3__GPIO_108 0x1181
314 VF610_PAD_PTE5__GPIO_110 0x1181
315 VF610_PAD_PTE6__GPIO_111 0x1181
317 VF610_PAD_PTE0__GPIO_105 0x1183
318 VF610_PAD_PTE7__GPIO_112 0x1183
320 VF610_PAD_PTB8__GPIO_30 0x1183
321 VF610_PAD_PTB9__GPIO_31 0x1183
322 VF610_PAD_PTE8__GPIO_113 0x1183
324 VF610_PAD_PTE28__GPIO_133 0x1183
326 VF610_PAD_PTE10__GPIO_115 0x1183
327 VF610_PAD_PTE11__GPIO_116 0x1183
328 VF610_PAD_PTE17__GPIO_122 0x1183
329 VF610_PAD_PTC30__GPIO_103 0x1183
330 VF610_PAD_PTB0__GPIO_22 0x1181
332 VF610_PAD_PTE26__GPIO_131 0x1183
333 VF610_PAD_PTD6__GPIO_85 0x1181
334 VF610_PAD_PTE27__GPIO_132 0x1181
335 VF610_PAD_PTE13__GPIO_118 0x1181
336 VF610_PAD_PTE21__GPIO_126 0x1181
337 VF610_PAD_PTE22__GPIO_127 0x1181
339 VF610_PAD_PTE18__GPIO_123 0x1183
341 VF610_PAD_PTE25__GPIO_130 0x1181
345 pinctrl_can0: can0grp {
347 VF610_PAD_PTB14__CAN0_RX 0x1181
348 VF610_PAD_PTB15__CAN0_TX 0x1182
352 pinctrl_can1: can1grp {
354 VF610_PAD_PTB16__CAN1_RX 0x1181
355 VF610_PAD_PTB17__CAN1_TX 0x1182
359 pinctrl_dspi0: dspi0grp {
361 VF610_PAD_PTB18__DSPI0_CS1 0x1182
362 VF610_PAD_PTB19__DSPI0_CS0 0x1182
363 VF610_PAD_PTB20__DSPI0_SIN 0x1181
364 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
365 VF610_PAD_PTB22__DSPI0_SCK 0x1182
369 pinctrl_dspi3: dspi3grp {
371 VF610_PAD_PTD10__DSPI3_CS0 0x1181
372 VF610_PAD_PTD11__DSPI3_SIN 0x1181
373 VF610_PAD_PTD12__DSPI3_SOUT 0x1182
374 VF610_PAD_PTD13__DSPI3_SCK 0x1181
378 pinctrl_esdhc1: esdhc1grp {
380 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
381 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
382 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
383 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
384 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
385 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
386 VF610_PAD_PTB28__GPIO_98 0x219d
390 pinctrl_fec0: fec0grp {
392 VF610_PAD_PTA6__RMII_CLKIN 0x30dd
393 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de
394 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
395 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd
396 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
397 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
398 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
399 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
400 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
401 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
405 pinctrl_fec1: fec1grp {
407 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de
408 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df
409 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd
410 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd
411 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd
412 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd
413 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de
414 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de
415 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de
419 pinctrl_gpio_leds: gpioledsgrp {
422 VF610_PAD_PTE12__GPIO_117 0x1183
424 VF610_PAD_PTE15__GPIO_120 0x1183
425 VF610_PAD_PTA12__GPIO_5 0x1183
426 VF610_PAD_PTA16__GPIO_6 0x1183
427 VF610_PAD_PTE9__GPIO_114 0x1183
428 VF610_PAD_PTE20__GPIO_125 0x1183
429 VF610_PAD_PTE23__GPIO_128 0x1183
430 VF610_PAD_PTE16__GPIO_121 0x1183
434 pinctrl_i2c2: i2c2grp {
436 VF610_PAD_PTA22__I2C2_SCL 0x34df
437 VF610_PAD_PTA23__I2C2_SDA 0x34df
441 pinctrl_nfc: nfcgrp {
443 VF610_PAD_PTD23__NF_IO7 0x28df
444 VF610_PAD_PTD22__NF_IO6 0x28df
445 VF610_PAD_PTD21__NF_IO5 0x28df
446 VF610_PAD_PTD20__NF_IO4 0x28df
447 VF610_PAD_PTD19__NF_IO3 0x28df
448 VF610_PAD_PTD18__NF_IO2 0x28df
449 VF610_PAD_PTD17__NF_IO1 0x28df
450 VF610_PAD_PTD16__NF_IO0 0x28df
451 VF610_PAD_PTB24__NF_WE_B 0x28c2
452 VF610_PAD_PTB25__NF_CE0_B 0x28c2
453 VF610_PAD_PTB27__NF_RE_B 0x28c2
454 VF610_PAD_PTC26__NF_RB_B 0x283d
455 VF610_PAD_PTC27__NF_ALE 0x28c2
456 VF610_PAD_PTC28__NF_CLE 0x28c2
460 pinctrl_qspi0: qspi0grp {
462 VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f
463 VF610_PAD_PTD1__QSPI0_A_CS0 0x397f
464 VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f
465 VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f
466 VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f
467 VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f
468 VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f
469 VF610_PAD_PTD8__QSPI0_B_CS0 0x397f
470 VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f
471 VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f
475 pinctrl_uart0: uart0grp {
477 VF610_PAD_PTB10__UART0_TX 0x21a2
478 VF610_PAD_PTB11__UART0_RX 0x21a1
482 pinctrl_uart1: uart1grp {
484 VF610_PAD_PTB4__UART1_TX 0x21a2
485 VF610_PAD_PTB5__UART1_RX 0x21a1
489 pinctrl_uart2: uart2grp {
491 VF610_PAD_PTB6__UART2_TX 0x21a2
492 VF610_PAD_PTB7__UART2_RX 0x21a1
496 pinctrl_uart3: uart3grp {
498 VF610_PAD_PTA20__UART3_TX 0x21a2
499 VF610_PAD_PTA21__UART3_RX 0x21a1