1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * CoreTile Express A9x4
6 * Cortex-A9 MPCore (V2P-CA9)
16 arm,vexpress,site = <0xf>;
17 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
18 interrupt-parent = <&gic>;
25 serial0 = &v2m_serial0;
26 serial1 = &v2m_serial1;
27 serial2 = &v2m_serial2;
28 serial3 = &v2m_serial3;
39 compatible = "arm,cortex-a9";
41 next-level-cache = <&L2>;
46 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 compatible = "arm,cortex-a9";
55 next-level-cache = <&L2>;
60 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
67 device_type = "memory";
68 reg = <0x60000000 0x40000000>;
72 compatible = "arm,pl111", "arm,primecell";
73 reg = <0x10020000 0x1000>;
74 interrupt-names = "combined";
75 interrupts = <0 44 4>;
76 clocks = <&oscclk1>, <&oscclk2>;
77 clock-names = "clcdclk", "apb_pclk";
78 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
82 remote-endpoint = <&clcd_panel>;
83 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
88 compatible = "panel-dpi";
91 clcd_panel: endpoint {
92 remote-endpoint = <&clcd_pads>;
97 clock-frequency = <63500127>;
110 memory-controller@100e0000 {
111 compatible = "arm,pl341", "arm,primecell";
112 reg = <0x100e0000 0x1000>;
114 clock-names = "apb_pclk";
117 memory-controller@100e1000 {
118 compatible = "arm,pl354", "arm,primecell";
119 reg = <0x100e1000 0x1000>;
120 interrupts = <0 45 4>,
123 clock-names = "apb_pclk";
127 compatible = "arm,sp804", "arm,primecell";
128 reg = <0x100e4000 0x1000>;
129 interrupts = <0 48 4>,
131 clocks = <&oscclk2>, <&oscclk2>;
132 clock-names = "timclk", "apb_pclk";
137 compatible = "arm,sp805", "arm,primecell";
138 reg = <0x100e5000 0x1000>;
139 interrupts = <0 51 4>;
140 clocks = <&oscclk2>, <&oscclk2>;
141 clock-names = "wdogclk", "apb_pclk";
145 compatible = "arm,cortex-a9-scu";
146 reg = <0x1e000000 0x58>;
150 compatible = "arm,cortex-a9-twd-timer";
151 reg = <0x1e000600 0x20>;
152 interrupts = <1 13 0xf04>;
156 compatible = "arm,cortex-a9-twd-wdt";
157 reg = <0x1e000620 0x20>;
158 interrupts = <1 14 0xf04>;
161 gic: interrupt-controller@1e001000 {
162 compatible = "arm,cortex-a9-gic";
163 #interrupt-cells = <3>;
164 #address-cells = <0>;
165 interrupt-controller;
166 reg = <0x1e001000 0x1000>,
170 L2: cache-controller@1e00a000 {
171 compatible = "arm,pl310-cache";
172 reg = <0x1e00a000 0x1000>;
173 interrupts = <0 43 4>;
176 arm,data-latency = <1 1 1>;
177 arm,tag-latency = <1 1 1>;
181 compatible = "arm,cortex-a9-pmu";
182 interrupts = <0 60 4>,
186 interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
191 compatible = "arm,vexpress,config-bus";
192 arm,vexpress,config-bridge = <&v2m_sysreg>;
194 oscclk0: extsaxiclk {
195 /* ACLK clock to the AXI master port on the test chip */
196 compatible = "arm,vexpress-osc";
197 arm,vexpress-sysreg,func = <1 0>;
198 freq-range = <30000000 50000000>;
200 clock-output-names = "extsaxiclk";
204 /* Reference clock for the CLCD */
205 compatible = "arm,vexpress-osc";
206 arm,vexpress-sysreg,func = <1 1>;
207 freq-range = <10000000 80000000>;
209 clock-output-names = "clcdclk";
212 smbclk: oscclk2: tcrefclk {
213 /* Reference clock for the test chip internal PLLs */
214 compatible = "arm,vexpress-osc";
215 arm,vexpress-sysreg,func = <1 2>;
216 freq-range = <33000000 100000000>;
218 clock-output-names = "tcrefclk";
222 /* Test Chip internal logic voltage */
223 compatible = "arm,vexpress-volt";
224 arm,vexpress-sysreg,func = <2 0>;
225 regulator-name = "VD10";
231 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
232 compatible = "arm,vexpress-volt";
233 arm,vexpress-sysreg,func = <2 1>;
234 regulator-name = "VD10_S2";
240 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
241 compatible = "arm,vexpress-volt";
242 arm,vexpress-sysreg,func = <2 2>;
243 regulator-name = "VD10_S3";
249 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
250 compatible = "arm,vexpress-volt";
251 arm,vexpress-sysreg,func = <2 3>;
252 regulator-name = "VCC1V8";
258 /* DDR2 SDRAM VTT termination voltage */
259 compatible = "arm,vexpress-volt";
260 arm,vexpress-sysreg,func = <2 4>;
261 regulator-name = "DDR2VTT";
267 /* Local board supply for miscellaneous logic external to the Test Chip */
268 arm,vexpress-sysreg,func = <2 5>;
269 compatible = "arm,vexpress-volt";
270 regulator-name = "VCC3V3";
276 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
277 compatible = "arm,vexpress-amp";
278 arm,vexpress-sysreg,func = <3 0>;
283 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
284 compatible = "arm,vexpress-amp";
285 arm,vexpress-sysreg,func = <3 1>;
290 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
291 compatible = "arm,vexpress-power";
292 arm,vexpress-sysreg,func = <12 0>;
297 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
298 compatible = "arm,vexpress-power";
299 arm,vexpress-sysreg,func = <12 1>;
305 compatible = "simple-bus";
307 #address-cells = <2>;
309 ranges = <0 0 0x40000000 0x04000000>,
310 <1 0 0x44000000 0x04000000>,
311 <2 0 0x48000000 0x04000000>,
312 <3 0 0x4c000000 0x04000000>,
313 <7 0 0x10000000 0x00020000>;
315 #interrupt-cells = <1>;
316 interrupt-map-mask = <0 0 63>;
317 interrupt-map = <0 0 0 &gic 0 0 4>,
327 <0 0 10 &gic 0 10 4>,
328 <0 0 11 &gic 0 11 4>,
329 <0 0 12 &gic 0 12 4>,
330 <0 0 13 &gic 0 13 4>,
331 <0 0 14 &gic 0 14 4>,
332 <0 0 15 &gic 0 15 4>,
333 <0 0 16 &gic 0 16 4>,
334 <0 0 17 &gic 0 17 4>,
335 <0 0 18 &gic 0 18 4>,
336 <0 0 19 &gic 0 19 4>,
337 <0 0 20 &gic 0 20 4>,
338 <0 0 21 &gic 0 21 4>,
339 <0 0 22 &gic 0 22 4>,
340 <0 0 23 &gic 0 23 4>,
341 <0 0 24 &gic 0 24 4>,
342 <0 0 25 &gic 0 25 4>,
343 <0 0 26 &gic 0 26 4>,
344 <0 0 27 &gic 0 27 4>,
345 <0 0 28 &gic 0 28 4>,
346 <0 0 29 &gic 0 29 4>,
347 <0 0 30 &gic 0 30 4>,
348 <0 0 31 &gic 0 31 4>,
349 <0 0 32 &gic 0 32 4>,
350 <0 0 33 &gic 0 33 4>,
351 <0 0 34 &gic 0 34 4>,
352 <0 0 35 &gic 0 35 4>,
353 <0 0 36 &gic 0 36 4>,
354 <0 0 37 &gic 0 37 4>,
355 <0 0 38 &gic 0 38 4>,
356 <0 0 39 &gic 0 39 4>,
357 <0 0 40 &gic 0 40 4>,
358 <0 0 41 &gic 0 41 4>,
359 <0 0 42 &gic 0 42 4>;
361 /include/ "vexpress-v2m.dtsi"
364 site2: hsb@e0000000 {
365 compatible = "simple-bus";
366 #address-cells = <1>;
368 ranges = <0 0xe0000000 0x20000000>;
369 #interrupt-cells = <1>;
370 interrupt-map-mask = <0 3>;
371 interrupt-map = <0 0 &gic 0 36 4>,