1 // SPDX-License-Identifier: GPL-2.0
5 model = "ARM Versatile AB";
6 compatible = "arm,versatile-ab";
9 interrupt-parent = <&vic>;
23 device_type = "memory";
24 reg = <0x0 0x08000000>;
27 xtal24mhz: xtal24mhz@24M {
29 compatible = "fixed-clock";
30 clock-frequency = <24000000>;
34 compatible = "ti,ths8134b", "ti,ths8134";
45 vga_bridge_in: endpoint {
46 remote-endpoint = <&clcd_pads_vga_dac>;
53 vga_bridge_out: endpoint {
54 remote-endpoint = <&vga_con_in>;
61 compatible = "vga-connector";
64 vga_con_in: endpoint {
65 remote-endpoint = <&vga_bridge_out>;
70 core-module@10000000 {
71 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
72 reg = <0x10000000 0x200>;
73 ranges = <0x0 0x10000000 0x200>;
78 compatible = "register-bit-led";
82 label = "versatile:0";
83 linux,default-trigger = "heartbeat";
87 compatible = "register-bit-led";
91 label = "versatile:1";
92 linux,default-trigger = "mmc0";
93 default-state = "off";
96 compatible = "register-bit-led";
100 label = "versatile:2";
101 linux,default-trigger = "cpu0";
102 default-state = "off";
105 compatible = "register-bit-led";
109 label = "versatile:3";
110 default-state = "off";
113 compatible = "register-bit-led";
117 label = "versatile:4";
118 default-state = "off";
121 compatible = "register-bit-led";
125 label = "versatile:5";
126 default-state = "off";
129 compatible = "register-bit-led";
133 label = "versatile:6";
134 default-state = "off";
137 compatible = "register-bit-led";
141 label = "versatile:7";
142 default-state = "off";
145 /* OSC1 on AB, OSC4 on PB */
146 osc1: cm_aux_osc@24M {
148 compatible = "arm,versatile-cm-auxosc";
149 clocks = <&xtal24mhz>;
152 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
155 compatible = "fixed-factor-clock";
158 clocks = <&xtal24mhz>;
163 compatible = "fixed-factor-clock";
166 clocks = <&xtal24mhz>;
171 /* 64 MiB NOR flash in non-interleaved chips */
172 compatible = "arm,versatile-flash", "cfi-flash";
173 reg = <0x34000000 0x04000000>;
176 compatible = "arm,arm-firmware-suite";
181 #address-cells = <1>;
183 compatible = "arm,versatile-i2c";
184 reg = <0x10002000 0x1000>;
187 compatible = "dallas,ds1338";
193 compatible = "smsc,lan91c111";
194 reg = <0x10010000 0x10000>;
199 compatible = "arm,versatile-lcd";
200 reg = <0x10008000 0x1000>;
204 compatible = "simple-bus";
205 #address-cells = <1>;
209 vic: interrupt-controller@10140000 {
210 compatible = "arm,versatile-vic";
211 interrupt-controller;
212 #interrupt-cells = <1>;
213 reg = <0x10140000 0x1000>;
214 valid-mask = <0xffffffff>;
217 sic: interrupt-controller@10003000 {
218 compatible = "arm,versatile-sic";
219 interrupt-controller;
220 #interrupt-cells = <1>;
221 reg = <0x10003000 0x1000>;
222 interrupt-parent = <&vic>;
223 interrupts = <31>; /* Cascaded to vic */
224 clear-mask = <0xffffffff>;
226 * Valid interrupt lines mask according to
227 * table 4-36 page 4-50 of ARM DUI 0225D
229 valid-mask = <0x0760031b>;
233 compatible = "arm,pl081", "arm,primecell";
234 reg = <0x10130000 0x1000>;
237 clock-names = "apb_pclk";
240 uart0: uart@101f1000 {
241 compatible = "arm,pl011", "arm,primecell";
242 reg = <0x101f1000 0x1000>;
244 clocks = <&xtal24mhz>, <&pclk>;
245 clock-names = "uartclk", "apb_pclk";
248 uart1: uart@101f2000 {
249 compatible = "arm,pl011", "arm,primecell";
250 reg = <0x101f2000 0x1000>;
252 clocks = <&xtal24mhz>, <&pclk>;
253 clock-names = "uartclk", "apb_pclk";
256 uart2: uart@101f3000 {
257 compatible = "arm,pl011", "arm,primecell";
258 reg = <0x101f3000 0x1000>;
260 clocks = <&xtal24mhz>, <&pclk>;
261 clock-names = "uartclk", "apb_pclk";
265 compatible = "arm,primecell";
266 reg = <0x10100000 0x1000>;
268 clock-names = "apb_pclk";
272 compatible = "arm,primecell";
273 reg = <0x10110000 0x1000>;
275 clock-names = "apb_pclk";
279 compatible = "arm,pl110", "arm,primecell";
280 reg = <0x10120000 0x1000>;
282 clocks = <&osc1>, <&pclk>;
283 clock-names = "clcdclk", "apb_pclk";
284 /* 800x600 16bpp @ 36MHz works fine */
285 max-memory-bandwidth = <54000000>;
288 * This port is routed through a PLD (Programmable
289 * Logic Device) that routes the output from the CLCD
290 * (after transformations) to the VGA DAC and also an
291 * external panel connector. The PLD is essential for
292 * supporting RGB565/BGR565.
294 * The signals from the port thus reaches two endpoints.
295 * The PLD is managed through a few special bits in the
298 * This arrangement can be clearly seen in
299 * ARM DUI 0225D, page 3-41, figure 3-19.
302 #address-cells = <1>;
305 clcd_pads_panel: endpoint@0 {
307 remote-endpoint = <&panel_in>;
308 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
310 clcd_pads_vga_dac: endpoint@1 {
312 remote-endpoint = <&vga_bridge_in>;
313 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
319 compatible = "arm,primecell";
320 reg = <0x101e0000 0x1000>;
322 clock-names = "apb_pclk";
326 compatible = "arm,primecell";
327 reg = <0x101e1000 0x1000>;
330 clock-names = "apb_pclk";
334 compatible = "arm,sp804", "arm,primecell";
335 reg = <0x101e2000 0x1000>;
337 clocks = <&timclk>, <&timclk>, <&pclk>;
338 clock-names = "timer0", "timer1", "apb_pclk";
342 compatible = "arm,sp804", "arm,primecell";
343 reg = <0x101e3000 0x1000>;
345 clocks = <&timclk>, <&timclk>, <&pclk>;
346 clock-names = "timer0", "timer1", "apb_pclk";
349 gpio0: gpio@101e4000 {
350 compatible = "arm,pl061", "arm,primecell";
351 reg = <0x101e4000 0x1000>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
358 clock-names = "apb_pclk";
361 gpio1: gpio@101e5000 {
362 compatible = "arm,pl061", "arm,primecell";
363 reg = <0x101e5000 0x1000>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
370 clock-names = "apb_pclk";
374 compatible = "arm,pl030", "arm,primecell";
375 reg = <0x101e8000 0x1000>;
378 clock-names = "apb_pclk";
382 compatible = "arm,primecell";
383 reg = <0x101f0000 0x1000>;
386 clock-names = "apb_pclk";
390 compatible = "arm,pl022", "arm,primecell";
391 reg = <0x101f4000 0x1000>;
393 clocks = <&xtal24mhz>, <&pclk>;
394 clock-names = "SSPCLK", "apb_pclk";
398 compatible = "arm,versatile-fpga", "simple-bus";
399 #address-cells = <1>;
401 ranges = <0 0x10000000 0x10000>;
404 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
405 reg = <0x00000 0x1000>;
408 compatible = "arm,versatile-tft-panel";
412 remote-endpoint = <&clcd_pads_panel>;
419 compatible = "arm,primecell";
420 reg = <0x4000 0x1000>;
423 clock-names = "apb_pclk";
426 compatible = "arm,pl180", "arm,primecell";
427 reg = <0x5000 0x1000>;
428 interrupts-extended = <&vic 22 &sic 1>;
429 clocks = <&xtal24mhz>, <&pclk>;
430 clock-names = "mclk", "apb_pclk";
433 compatible = "arm,pl050", "arm,primecell";
434 reg = <0x6000 0x1000>;
435 interrupt-parent = <&sic>;
437 clocks = <&xtal24mhz>, <&pclk>;
438 clock-names = "KMIREFCLK", "apb_pclk";
441 compatible = "arm,pl050", "arm,primecell";
442 reg = <0x7000 0x1000>;
443 interrupt-parent = <&sic>;
445 clocks = <&xtal24mhz>, <&pclk>;
446 clock-names = "KMIREFCLK", "apb_pclk";