1 // SPDX-License-Identifier: GPL-2.0
3 /include/ "skeleton.dtsi"
6 model = "ARM Versatile AB";
7 compatible = "arm,versatile-ab";
10 interrupt-parent = <&vic>;
24 reg = <0x0 0x08000000>;
27 xtal24mhz: xtal24mhz@24M {
29 compatible = "fixed-clock";
30 clock-frequency = <24000000>;
34 compatible = "ti,ths8134b", "ti,ths8134";
45 vga_bridge_in: endpoint {
46 remote-endpoint = <&clcd_pads_vga_dac>;
53 vga_bridge_out: endpoint {
54 remote-endpoint = <&vga_con_in>;
61 compatible = "vga-connector";
64 vga_con_in: endpoint {
65 remote-endpoint = <&vga_bridge_out>;
70 core-module@10000000 {
71 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
72 reg = <0x10000000 0x200>;
75 compatible = "register-bit-led";
78 label = "versatile:0";
79 linux,default-trigger = "heartbeat";
83 compatible = "register-bit-led";
86 label = "versatile:1";
87 linux,default-trigger = "mmc0";
88 default-state = "off";
91 compatible = "register-bit-led";
94 label = "versatile:2";
95 linux,default-trigger = "cpu0";
96 default-state = "off";
99 compatible = "register-bit-led";
102 label = "versatile:3";
103 default-state = "off";
106 compatible = "register-bit-led";
109 label = "versatile:4";
110 default-state = "off";
113 compatible = "register-bit-led";
116 label = "versatile:5";
117 default-state = "off";
120 compatible = "register-bit-led";
123 label = "versatile:6";
124 default-state = "off";
127 compatible = "register-bit-led";
130 label = "versatile:7";
131 default-state = "off";
134 /* OSC1 on AB, OSC4 on PB */
135 osc1: cm_aux_osc@24M {
137 compatible = "arm,versatile-cm-auxosc";
138 clocks = <&xtal24mhz>;
141 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
144 compatible = "fixed-factor-clock";
147 clocks = <&xtal24mhz>;
152 compatible = "fixed-factor-clock";
155 clocks = <&xtal24mhz>;
160 /* 64 MiB NOR flash in non-interleaved chips */
161 compatible = "arm,versatile-flash", "cfi-flash";
162 reg = <0x34000000 0x04000000>;
167 #address-cells = <1>;
169 compatible = "arm,versatile-i2c";
170 reg = <0x10002000 0x1000>;
173 compatible = "dallas,ds1338";
179 compatible = "smsc,lan91c111";
180 reg = <0x10010000 0x10000>;
185 compatible = "arm,versatile-lcd";
186 reg = <0x10008000 0x1000>;
190 compatible = "simple-bus";
191 #address-cells = <1>;
196 compatible = "arm,versatile-vic";
197 interrupt-controller;
198 #interrupt-cells = <1>;
199 reg = <0x10140000 0x1000>;
200 clear-mask = <0xffffffff>;
201 valid-mask = <0xffffffff>;
205 compatible = "arm,versatile-sic";
206 interrupt-controller;
207 #interrupt-cells = <1>;
208 reg = <0x10003000 0x1000>;
209 interrupt-parent = <&vic>;
210 interrupts = <31>; /* Cascaded to vic */
211 clear-mask = <0xffffffff>;
213 * Valid interrupt lines mask according to
214 * table 4-36 page 4-50 of ARM DUI 0225D
216 valid-mask = <0x0760031b>;
220 compatible = "arm,pl081", "arm,primecell";
221 reg = <0x10130000 0x1000>;
224 clock-names = "apb_pclk";
227 uart0: uart@101f1000 {
228 compatible = "arm,pl011", "arm,primecell";
229 reg = <0x101f1000 0x1000>;
231 clocks = <&xtal24mhz>, <&pclk>;
232 clock-names = "uartclk", "apb_pclk";
235 uart1: uart@101f2000 {
236 compatible = "arm,pl011", "arm,primecell";
237 reg = <0x101f2000 0x1000>;
239 clocks = <&xtal24mhz>, <&pclk>;
240 clock-names = "uartclk", "apb_pclk";
243 uart2: uart@101f3000 {
244 compatible = "arm,pl011", "arm,primecell";
245 reg = <0x101f3000 0x1000>;
247 clocks = <&xtal24mhz>, <&pclk>;
248 clock-names = "uartclk", "apb_pclk";
252 compatible = "arm,primecell";
253 reg = <0x10100000 0x1000>;
255 clock-names = "apb_pclk";
259 compatible = "arm,primecell";
260 reg = <0x10110000 0x1000>;
262 clock-names = "apb_pclk";
266 compatible = "arm,pl110", "arm,primecell";
267 reg = <0x10120000 0x1000>;
269 clocks = <&osc1>, <&pclk>;
270 clock-names = "clcdclk", "apb_pclk";
271 /* 800x600 16bpp @ 36MHz works fine */
272 max-memory-bandwidth = <54000000>;
275 * This port is routed through a PLD (Programmable
276 * Logic Device) that routes the output from the CLCD
277 * (after transformations) to the VGA DAC and also an
278 * external panel connector. The PLD is essential for
279 * supporting RGB565/BGR565.
281 * The signals from the port thus reaches two endpoints.
282 * The PLD is managed through a few special bits in the
285 * This arrangement can be clearly seen in
286 * ARM DUI 0225D, page 3-41, figure 3-19.
289 #address-cells = <1>;
292 clcd_pads_panel: endpoint@0 {
294 remote-endpoint = <&panel_in>;
295 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
297 clcd_pads_vga_dac: endpoint@1 {
299 remote-endpoint = <&vga_bridge_in>;
300 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
306 compatible = "arm,primecell";
307 reg = <0x101e0000 0x1000>;
309 clock-names = "apb_pclk";
313 compatible = "arm,primecell";
314 reg = <0x101e1000 0x1000>;
317 clock-names = "apb_pclk";
321 compatible = "arm,sp804", "arm,primecell";
322 reg = <0x101e2000 0x1000>;
324 clocks = <&timclk>, <&timclk>, <&pclk>;
325 clock-names = "timer0", "timer1", "apb_pclk";
329 compatible = "arm,sp804", "arm,primecell";
330 reg = <0x101e3000 0x1000>;
332 clocks = <&timclk>, <&timclk>, <&pclk>;
333 clock-names = "timer0", "timer1", "apb_pclk";
336 gpio0: gpio@101e4000 {
337 compatible = "arm,pl061", "arm,primecell";
338 reg = <0x101e4000 0x1000>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
345 clock-names = "apb_pclk";
348 gpio1: gpio@101e5000 {
349 compatible = "arm,pl061", "arm,primecell";
350 reg = <0x101e5000 0x1000>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
357 clock-names = "apb_pclk";
361 compatible = "arm,pl030", "arm,primecell";
362 reg = <0x101e8000 0x1000>;
365 clock-names = "apb_pclk";
369 compatible = "arm,primecell";
370 reg = <0x101f0000 0x1000>;
373 clock-names = "apb_pclk";
377 compatible = "arm,pl022", "arm,primecell";
378 reg = <0x101f4000 0x1000>;
380 clocks = <&xtal24mhz>, <&pclk>;
381 clock-names = "SSPCLK", "apb_pclk";
385 compatible = "arm,versatile-fpga", "simple-bus";
386 #address-cells = <1>;
388 ranges = <0 0x10000000 0x10000>;
391 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
392 reg = <0x00000 0x1000>;
395 compatible = "arm,versatile-tft-panel";
399 remote-endpoint = <&clcd_pads_panel>;
406 compatible = "arm,primecell";
407 reg = <0x4000 0x1000>;
410 clock-names = "apb_pclk";
413 compatible = "arm,pl180", "arm,primecell";
414 reg = <0x5000 0x1000>;
415 interrupts-extended = <&vic 22 &sic 1>;
416 clocks = <&xtal24mhz>, <&pclk>;
417 clock-names = "mclk", "apb_pclk";
420 compatible = "arm,pl050", "arm,primecell";
421 reg = <0x6000 0x1000>;
422 interrupt-parent = <&sic>;
424 clocks = <&xtal24mhz>, <&pclk>;
425 clock-names = "KMIREFCLK", "apb_pclk";
428 compatible = "arm,pl050", "arm,primecell";
429 reg = <0x7000 0x1000>;
430 interrupt-parent = <&sic>;
432 clocks = <&xtal24mhz>, <&pclk>;
433 clock-names = "KMIREFCLK", "apb_pclk";