arch/arm/boot/dts/uniphier-pxs2.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier PXs2 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/uniphier-gpio.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 / {
  12         compatible = "socionext,uniphier-pxs2";
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a9";
  23                         reg = <0>;
  24                         clocks = <&sys_clk 32>;
  25                         enable-method = "psci";
  26                         next-level-cache = <&l2>;
  27                         operating-points-v2 = <&cpu_opp>;
  28                         #cooling-cells = <2>;
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                         clocks = <&sys_clk 32>;
  36                         enable-method = "psci";
  37                         next-level-cache = <&l2>;
  38                         operating-points-v2 = <&cpu_opp>;
  39                 };
  40
  41                 cpu2: cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <2>;
  45                         clocks = <&sys_clk 32>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                         operating-points-v2 = <&cpu_opp>;
  49                 };
  50
  51                 cpu3: cpu@3 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         reg = <3>;
  55                         clocks = <&sys_clk 32>;
  56                         enable-method = "psci";
  57                         next-level-cache = <&l2>;
  58                         operating-points-v2 = <&cpu_opp>;
  59                 };
  60         };
  61
  62         cpu_opp: opp-table {
  63                 compatible = "operating-points-v2";
  64                 opp-shared;
  65
  66                 opp-100000000 {
  67                         opp-hz = /bits/ 64 <100000000>;
  68                         clock-latency-ns = <300>;
  69                 };
  70                 opp-150000000 {
  71                         opp-hz = /bits/ 64 <150000000>;
  72                         clock-latency-ns = <300>;
  73                 };
  74                 opp-200000000 {
  75                         opp-hz = /bits/ 64 <200000000>;
  76                         clock-latency-ns = <300>;
  77                 };
  78                 opp-300000000 {
  79                         opp-hz = /bits/ 64 <300000000>;
  80                         clock-latency-ns = <300>;
  81                 };
  82                 opp-400000000 {
  83                         opp-hz = /bits/ 64 <400000000>;
  84                         clock-latency-ns = <300>;
  85                 };
  86                 opp-600000000 {
  87                         opp-hz = /bits/ 64 <600000000>;
  88                         clock-latency-ns = <300>;
  89                 };
  90                 opp-800000000 {
  91                         opp-hz = /bits/ 64 <800000000>;
  92                         clock-latency-ns = <300>;
  93                 };
  94                 opp-1200000000 {
  95                         opp-hz = /bits/ 64 <1200000000>;
  96                         clock-latency-ns = <300>;
  97                 };
  98         };
  99
 100         psci {
 101                 compatible = "arm,psci-0.2";
 102                 method = "smc";
 103         };
 104
 105         clocks {
 106                 refclk: ref {
 107                         compatible = "fixed-clock";
 108                         #clock-cells = <0>;
 109                         clock-frequency = <25000000>;
 110                 };
 111
 112                 arm_timer_clk: arm-timer {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-clock";
 115                         clock-frequency = <50000000>;
 116                 };
 117         };
 118
 119         thermal-zones {
 120                 cpu-thermal {
 121                         polling-delay-passive = <250>;  /* 250ms */
 122                         polling-delay = <1000>;         /* 1000ms */
 123                         thermal-sensors = <&pvtctl>;
 124
 125                         trips {
 126                                 cpu_crit: cpu-crit {
 127                                         temperature = <95000>;  /* 95C */
 128                                         hysteresis = <2000>;
 129                                         type = "critical";
 130                                 };
 131                                 cpu_alert: cpu-alert {
 132                                         temperature = <85000>;  /* 85C */
 133                                         hysteresis = <2000>;
 134                                         type = "passive";
 135                                 };
 136                         };
 137
 138                         cooling-maps {
 139                                 map {
 140                                         trip = <&cpu_alert>;
 141                                         cooling-device = <&cpu0
 142                                             THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 143                                 };
 144                         };
 145                 };
 146         };
 147
 148         soc {
 149                 compatible = "simple-bus";
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 ranges;
 153                 interrupt-parent = <&intc>;
 154
 155                 l2: l2-cache@500c0000 {
 156                         compatible = "socionext,uniphier-system-cache";
 157                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 158                               <0x506c0000 0x400>;
 159                         interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
 160                         cache-unified;
 161                         cache-size = <(1280 * 1024)>;
 162                         cache-sets = <512>;
 163                         cache-line-size = <128>;
 164                         cache-level = <2>;
 165                 };
 166
 167                 serial0: serial@54006800 {
 168                         compatible = "socionext,uniphier-uart";
 169                         status = "disabled";
 170                         reg = <0x54006800 0x40>;
 171                         interrupts = <0 33 4>;
 172                         pinctrl-names = "default";
 173                         pinctrl-0 = <&pinctrl_uart0>;
 174                         clocks = <&peri_clk 0>;
 175                         resets = <&peri_rst 0>;
 176                 };
 177
 178                 serial1: serial@54006900 {
 179                         compatible = "socionext,uniphier-uart";
 180                         status = "disabled";
 181                         reg = <0x54006900 0x40>;
 182                         interrupts = <0 35 4>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_uart1>;
 185                         clocks = <&peri_clk 1>;
 186                         resets = <&peri_rst 1>;
 187                 };
 188
 189                 serial2: serial@54006a00 {
 190                         compatible = "socionext,uniphier-uart";
 191                         status = "disabled";
 192                         reg = <0x54006a00 0x40>;
 193                         interrupts = <0 37 4>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_uart2>;
 196                         clocks = <&peri_clk 2>;
 197                         resets = <&peri_rst 2>;
 198                 };
 199
 200                 serial3: serial@54006b00 {
 201                         compatible = "socionext,uniphier-uart";
 202                         status = "disabled";
 203                         reg = <0x54006b00 0x40>;
 204                         interrupts = <0 177 4>;
 205                         pinctrl-names = "default";
 206                         pinctrl-0 = <&pinctrl_uart3>;
 207                         clocks = <&peri_clk 3>;
 208                         resets = <&peri_rst 3>;
 209                 };
 210
 211                 gpio: gpio@55000000 {
 212                         compatible = "socionext,uniphier-gpio";
 213                         reg = <0x55000000 0x200>;
 214                         interrupt-parent = <&aidet>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <2>;
 217                         gpio-controller;
 218                         #gpio-cells = <2>;
 219                         gpio-ranges = <&pinctrl 0 0 0>,
 220                                       <&pinctrl 96 0 0>;
 221                         gpio-ranges-group-names = "gpio_range0",
 222                                                   "gpio_range1";
 223                         ngpios = <232>;
 224                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 225                                                      <21 217 3>;
 226                 };
 227
 228                 i2c0: i2c@58780000 {
 229                         compatible = "socionext,uniphier-fi2c";
 230                         status = "disabled";
 231                         reg = <0x58780000 0x80>;
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         interrupts = <0 41 4>;
 235                         pinctrl-names = "default";
 236                         pinctrl-0 = <&pinctrl_i2c0>;
 237                         clocks = <&peri_clk 4>;
 238                         resets = <&peri_rst 4>;
 239                         clock-frequency = <100000>;
 240                 };
 241
 242                 i2c1: i2c@58781000 {
 243                         compatible = "socionext,uniphier-fi2c";
 244                         status = "disabled";
 245                         reg = <0x58781000 0x80>;
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         interrupts = <0 42 4>;
 249                         pinctrl-names = "default";
 250                         pinctrl-0 = <&pinctrl_i2c1>;
 251                         clocks = <&peri_clk 5>;
 252                         resets = <&peri_rst 5>;
 253                         clock-frequency = <100000>;
 254                 };
 255
 256                 i2c2: i2c@58782000 {
 257                         compatible = "socionext,uniphier-fi2c";
 258                         status = "disabled";
 259                         reg = <0x58782000 0x80>;
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262                         interrupts = <0 43 4>;
 263                         pinctrl-names = "default";
 264                         pinctrl-0 = <&pinctrl_i2c2>;
 265                         clocks = <&peri_clk 6>;
 266                         resets = <&peri_rst 6>;
 267                         clock-frequency = <100000>;
 268                 };
 269
 270                 i2c3: i2c@58783000 {
 271                         compatible = "socionext,uniphier-fi2c";
 272                         status = "disabled";
 273                         reg = <0x58783000 0x80>;
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         interrupts = <0 44 4>;
 277                         pinctrl-names = "default";
 278                         pinctrl-0 = <&pinctrl_i2c3>;
 279                         clocks = <&peri_clk 7>;
 280                         resets = <&peri_rst 7>;
 281                         clock-frequency = <100000>;
 282                 };
 283
 284                 /* chip-internal connection for DMD */
 285                 i2c4: i2c@58784000 {
 286                         compatible = "socionext,uniphier-fi2c";
 287                         reg = <0x58784000 0x80>;
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         interrupts = <0 45 4>;
 291                         clocks = <&peri_clk 8>;
 292                         resets = <&peri_rst 8>;
 293                         clock-frequency = <400000>;
 294                 };
 295
 296                 /* chip-internal connection for STM */
 297                 i2c5: i2c@58785000 {
 298                         compatible = "socionext,uniphier-fi2c";
 299                         reg = <0x58785000 0x80>;
 300                         #address-cells = <1>;
 301                         #size-cells = <0>;
 302                         interrupts = <0 25 4>;
 303                         clocks = <&peri_clk 9>;
 304                         resets = <&peri_rst 9>;
 305                         clock-frequency = <400000>;
 306                 };
 307
 308                 /* chip-internal connection for HDMI */
 309                 i2c6: i2c@58786000 {
 310                         compatible = "socionext,uniphier-fi2c";
 311                         reg = <0x58786000 0x80>;
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                         interrupts = <0 26 4>;
 315                         clocks = <&peri_clk 10>;
 316                         resets = <&peri_rst 10>;
 317                         clock-frequency = <400000>;
 318                 };
 319
 320                 system_bus: system-bus@58c00000 {
 321                         compatible = "socionext,uniphier-system-bus";
 322                         status = "disabled";
 323                         reg = <0x58c00000 0x400>;
 324                         #address-cells = <2>;
 325                         #size-cells = <1>;
 326                         pinctrl-names = "default";
 327                         pinctrl-0 = <&pinctrl_system_bus>;
 328                 };
 329
 330                 smpctrl@59801000 {
 331                         compatible = "socionext,uniphier-smpctrl";
 332                         reg = <0x59801000 0x400>;
 333                 };
 334
 335                 sdctrl@59810000 {
 336                         compatible = "socionext,uniphier-pxs2-sdctrl",
 337                                      "simple-mfd", "syscon";
 338                         reg = <0x59810000 0x400>;
 339
 340                         sd_clk: clock {
 341                                 compatible = "socionext,uniphier-pxs2-sd-clock";
 342                                 #clock-cells = <1>;
 343                         };
 344
 345                         sd_rst: reset {
 346                                 compatible = "socionext,uniphier-pxs2-sd-reset";
 347                                 #reset-cells = <1>;
 348                         };
 349                 };
 350
 351                 perictrl@59820000 {
 352                         compatible = "socionext,uniphier-pxs2-perictrl",
 353                                      "simple-mfd", "syscon";
 354                         reg = <0x59820000 0x200>;
 355
 356                         peri_clk: clock {
 357                                 compatible = "socionext,uniphier-pxs2-peri-clock";
 358                                 #clock-cells = <1>;
 359                         };
 360
 361                         peri_rst: reset {
 362                                 compatible = "socionext,uniphier-pxs2-peri-reset";
 363                                 #reset-cells = <1>;
 364                         };
 365                 };
 366
 367                 soc-glue@5f800000 {
 368                         compatible = "socionext,uniphier-pxs2-soc-glue",
 369                                      "simple-mfd", "syscon";
 370                         reg = <0x5f800000 0x2000>;
 371
 372                         pinctrl: pinctrl {
 373                                 compatible = "socionext,uniphier-pxs2-pinctrl";
 374                         };
 375                 };
 376
 377                 soc-glue@5f900000 {
 378                         compatible = "socionext,uniphier-pxs2-soc-glue-debug",
 379                                      "simple-mfd";
 380                         #address-cells = <1>;
 381                         #size-cells = <1>;
 382                         ranges = <0 0x5f900000 0x2000>;
 383
 384                         efuse@100 {
 385                                 compatible = "socionext,uniphier-efuse";
 386                                 reg = <0x100 0x28>;
 387                         };
 388
 389                         efuse@200 {
 390                                 compatible = "socionext,uniphier-efuse";
 391                                 reg = <0x200 0x58>;
 392                         };
 393                 };
 394
 395                 aidet: aidet@5fc20000 {
 396                         compatible = "socionext,uniphier-pxs2-aidet";
 397                         reg = <0x5fc20000 0x200>;
 398                         interrupt-controller;
 399                         #interrupt-cells = <2>;
 400                 };
 401
 402                 timer@60000200 {
 403                         compatible = "arm,cortex-a9-global-timer";
 404                         reg = <0x60000200 0x20>;
 405                         interrupts = <1 11 0xf04>;
 406                         clocks = <&arm_timer_clk>;
 407                 };
 408
 409                 timer@60000600 {
 410                         compatible = "arm,cortex-a9-twd-timer";
 411                         reg = <0x60000600 0x20>;
 412                         interrupts = <1 13 0xf04>;
 413                         clocks = <&arm_timer_clk>;
 414                 };
 415
 416                 intc: interrupt-controller@60001000 {
 417                         compatible = "arm,cortex-a9-gic";
 418                         reg = <0x60001000 0x1000>,
 419                               <0x60000100 0x100>;
 420                         #interrupt-cells = <3>;
 421                         interrupt-controller;
 422                 };
 423
 424                 sysctrl@61840000 {
 425                         compatible = "socionext,uniphier-pxs2-sysctrl",
 426                                      "simple-mfd", "syscon";
 427                         reg = <0x61840000 0x10000>;
 428
 429                         sys_clk: clock {
 430                                 compatible = "socionext,uniphier-pxs2-clock";
 431                                 #clock-cells = <1>;
 432                         };
 433
 434                         sys_rst: reset {
 435                                 compatible = "socionext,uniphier-pxs2-reset";
 436                                 #reset-cells = <1>;
 437                         };
 438
 439                         pvtctl: pvtctl {
 440                                 compatible = "socionext,uniphier-pxs2-thermal";
 441                                 interrupts = <0 3 4>;
 442                                 #thermal-sensor-cells = <0>;
 443                                 socionext,tmod-calibration = <0x0f86 0x6844>;
 444                         };
 445                 };
 446
 447                 eth: ethernet@65000000 {
 448                         compatible = "socionext,uniphier-pxs2-ave4";
 449                         status = "disabled";
 450                         reg = <0x65000000 0x8500>;
 451                         interrupts = <0 66 4>;
 452                         pinctrl-names = "default";
 453                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 454                         clocks = <&sys_clk 6>;
 455                         resets = <&sys_rst 6>;
 456                         phy-mode = "rgmii";
 457                         local-mac-address = [00 00 00 00 00 00];
 458
 459                         mdio: mdio {
 460                                 #address-cells = <1>;
 461                                 #size-cells = <0>;
 462                         };
 463                 };
 464
 465                 nand: nand@68000000 {
 466                         compatible = "socionext,uniphier-denali-nand-v5b";
 467                         status = "disabled";
 468                         reg-names = "nand_data", "denali_reg";
 469                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 470                         interrupts = <0 65 4>;
 471                         pinctrl-names = "default";
 472                         pinctrl-0 = <&pinctrl_nand2cs>;
 473                         clocks = <&sys_clk 2>;
 474                         resets = <&sys_rst 2>;
 475                 };
 476         };
 477 };
 478
 479 #include "uniphier-pinctrl.dtsi"