2 * Device Tree Source for UniPhier Pro5 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro5";
21 compatible = "arm,cortex-a9";
23 clocks = <&sys_clk 32>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
33 clocks = <&sys_clk 32>;
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "operating-points-v2";
45 opp-hz = /bits/ 64 <100000000>;
46 clock-latency-ns = <300>;
49 opp-hz = /bits/ 64 <116667000>;
50 clock-latency-ns = <300>;
53 opp-hz = /bits/ 64 <150000000>;
54 clock-latency-ns = <300>;
57 opp-hz = /bits/ 64 <175000000>;
58 clock-latency-ns = <300>;
61 opp-hz = /bits/ 64 <200000000>;
62 clock-latency-ns = <300>;
65 opp-hz = /bits/ 64 <233334000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <300000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <350000000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <400000000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <466667000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <700000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <933334000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <1200000000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <1400000000>;
106 clock-latency-ns = <300>;
111 compatible = "arm,psci-0.2";
117 compatible = "fixed-clock";
119 clock-frequency = <20000000>;
122 arm_timer_clk: arm_timer_clk {
124 compatible = "fixed-clock";
125 clock-frequency = <50000000>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
134 interrupt-parent = <&intc>;
136 l2: l2-cache@500c0000 {
137 compatible = "socionext,uniphier-system-cache";
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
140 interrupts = <0 190 4>, <0 191 4>;
142 cache-size = <(2 * 1024 * 1024)>;
144 cache-line-size = <128>;
146 next-level-cache = <&l3>;
149 l3: l3-cache@500c8000 {
150 compatible = "socionext,uniphier-system-cache";
151 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 interrupts = <0 174 4>, <0 175 4>;
155 cache-size = <(2 * 1024 * 1024)>;
157 cache-line-size = <256>;
161 serial0: serial@54006800 {
162 compatible = "socionext,uniphier-uart";
164 reg = <0x54006800 0x40>;
165 interrupts = <0 33 4>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart0>;
168 clocks = <&peri_clk 0>;
171 serial1: serial@54006900 {
172 compatible = "socionext,uniphier-uart";
174 reg = <0x54006900 0x40>;
175 interrupts = <0 35 4>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_uart1>;
178 clocks = <&peri_clk 1>;
181 serial2: serial@54006a00 {
182 compatible = "socionext,uniphier-uart";
184 reg = <0x54006a00 0x40>;
185 interrupts = <0 37 4>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart2>;
188 clocks = <&peri_clk 2>;
191 serial3: serial@54006b00 {
192 compatible = "socionext,uniphier-uart";
194 reg = <0x54006b00 0x40>;
195 interrupts = <0 177 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart3>;
198 clocks = <&peri_clk 3>;
202 compatible = "socionext,uniphier-fi2c";
204 reg = <0x58780000 0x80>;
205 #address-cells = <1>;
207 interrupts = <0 41 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_i2c0>;
210 clocks = <&peri_clk 4>;
211 clock-frequency = <100000>;
215 compatible = "socionext,uniphier-fi2c";
217 reg = <0x58781000 0x80>;
218 #address-cells = <1>;
220 interrupts = <0 42 4>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c1>;
223 clocks = <&peri_clk 5>;
224 clock-frequency = <100000>;
228 compatible = "socionext,uniphier-fi2c";
230 reg = <0x58782000 0x80>;
231 #address-cells = <1>;
233 interrupts = <0 43 4>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_i2c2>;
236 clocks = <&peri_clk 6>;
237 clock-frequency = <100000>;
241 compatible = "socionext,uniphier-fi2c";
243 reg = <0x58783000 0x80>;
244 #address-cells = <1>;
246 interrupts = <0 44 4>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c3>;
249 clocks = <&peri_clk 7>;
250 clock-frequency = <100000>;
253 /* i2c4 does not exist */
255 /* chip-internal connection for DMD */
257 compatible = "socionext,uniphier-fi2c";
258 reg = <0x58785000 0x80>;
259 #address-cells = <1>;
261 interrupts = <0 25 4>;
262 clocks = <&peri_clk 9>;
263 clock-frequency = <400000>;
266 /* chip-internal connection for HDMI */
268 compatible = "socionext,uniphier-fi2c";
269 reg = <0x58786000 0x80>;
270 #address-cells = <1>;
272 interrupts = <0 26 4>;
273 clocks = <&peri_clk 10>;
274 clock-frequency = <400000>;
277 system_bus: system-bus@58c00000 {
278 compatible = "socionext,uniphier-system-bus";
280 reg = <0x58c00000 0x400>;
281 #address-cells = <2>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_system_bus>;
288 compatible = "socionext,uniphier-smpctrl";
289 reg = <0x59801000 0x400>;
293 compatible = "socionext,uniphier-pro5-sdctrl",
294 "simple-mfd", "syscon";
295 reg = <0x59810000 0x400>;
298 compatible = "socionext,uniphier-pro5-sd-clock";
303 compatible = "socionext,uniphier-pro5-sd-reset";
309 compatible = "socionext,uniphier-pro5-perictrl",
310 "simple-mfd", "syscon";
311 reg = <0x59820000 0x200>;
314 compatible = "socionext,uniphier-pro5-peri-clock";
319 compatible = "socionext,uniphier-pro5-peri-reset";
325 compatible = "socionext,uniphier-pro5-soc-glue",
326 "simple-mfd", "syscon";
327 reg = <0x5f800000 0x2000>;
330 compatible = "socionext,uniphier-pro5-pinctrl";
334 aidet: aidet@5fc20000 {
335 compatible = "socionext,uniphier-pro5-aidet";
336 reg = <0x5fc20000 0x200>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
342 compatible = "arm,cortex-a9-global-timer";
343 reg = <0x60000200 0x20>;
344 interrupts = <1 11 0x304>;
345 clocks = <&arm_timer_clk>;
349 compatible = "arm,cortex-a9-twd-timer";
350 reg = <0x60000600 0x20>;
351 interrupts = <1 13 0x304>;
352 clocks = <&arm_timer_clk>;
355 intc: interrupt-controller@60001000 {
356 compatible = "arm,cortex-a9-gic";
357 reg = <0x60001000 0x1000>,
359 #interrupt-cells = <3>;
360 interrupt-controller;
364 compatible = "socionext,uniphier-pro5-sysctrl",
365 "simple-mfd", "syscon";
366 reg = <0x61840000 0x10000>;
369 compatible = "socionext,uniphier-pro5-clock";
374 compatible = "socionext,uniphier-pro5-reset";
379 nand: nand@68000000 {
380 compatible = "socionext,uniphier-denali-nand-v5b";
382 reg-names = "nand_data", "denali_reg";
383 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
384 interrupts = <0 65 4>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_nand2cs>;
387 clocks = <&sys_clk 2>;
392 #include "uniphier-pinctrl.dtsi"