arch/arm/boot/dts/ti/omap/dra7.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
   4  *
   5  * Based on "omap4.dtsi"
   6  */
   7
   8 #include <dt-bindings/bus/ti-sysc.h>
   9 #include <dt-bindings/clock/dra7.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12 #include <dt-bindings/clock/dra7.h>
  13
  14 #define MAX_SOURCES 400
  15
  16 / {
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         compatible = "ti,dra7xx";
  21         interrupt-parent = <&crossbar_mpu>;
  22         chosen { };
  23
  24         aliases {
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 i2c4 = &i2c5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 serial5 = &uart6;
  36                 serial6 = &uart7;
  37                 serial7 = &uart8;
  38                 serial8 = &uart9;
  39                 serial9 = &uart10;
  40                 ethernet0 = &cpsw_port1;
  41                 ethernet1 = &cpsw_port2;
  42                 d_can0 = &dcan1;
  43                 d_can1 = &dcan2;
  44                 spi0 = &qspi;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv7-timer";
  49                 status = "disabled";    /* See ARM architected timer wrap erratum i940 */
  50                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  53                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  54                 interrupt-parent = <&gic>;
  55         };
  56
  57         gic: interrupt-controller@48211000 {
  58                 compatible = "arm,cortex-a15-gic";
  59                 interrupt-controller;
  60                 #interrupt-cells = <3>;
  61                 reg = <0x0 0x48211000 0x0 0x1000>,
  62                       <0x0 0x48212000 0x0 0x2000>,
  63                       <0x0 0x48214000 0x0 0x2000>,
  64                       <0x0 0x48216000 0x0 0x2000>;
  65                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  66                 interrupt-parent = <&gic>;
  67         };
  68
  69         wakeupgen: interrupt-controller@48281000 {
  70                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  71                 interrupt-controller;
  72                 #interrupt-cells = <3>;
  73                 reg = <0x0 0x48281000 0x0 0x1000>;
  74                 interrupt-parent = <&gic>;
  75         };
  76
  77         cpus {
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80
  81                 cpu0: cpu@0 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a15";
  84                         reg = <0>;
  85
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87
  88                         clocks = <&dpll_mpu_ck>;
  89                         clock-names = "cpu";
  90
  91                         clock-latency = <300000>; /* From omap-cpufreq driver */
  92
  93                         /* cooling options */
  94                         #cooling-cells = <2>; /* min followed by max */
  95
  96                         vbb-supply = <&abb_mpu>;
  97                 };
  98         };
  99
 100         cpu0_opp_table: opp-table {
 101                 compatible = "operating-points-v2-ti-cpu";
 102                 syscon = <&scm_wkup>;
 103
 104                 opp-1000000000 {
 105                         /* OPP NOM */
 106                         opp-hz = /bits/ 64 <1000000000>;
 107                         opp-microvolt = <1060000 850000 1150000>,
 108                                         <1060000 850000 1150000>;
 109                         opp-supported-hw = <0xFF 0x01>;
 110                         opp-suspend;
 111                 };
 112
 113                 opp-1176000000 {
 114                         /* OPP OD */
 115                         opp-hz = /bits/ 64 <1176000000>;
 116                         opp-microvolt = <1160000 885000 1160000>,
 117                                         <1160000 885000 1160000>;
 118
 119                         opp-supported-hw = <0xFF 0x02>;
 120                 };
 121
 122                 opp-1500000000 {
 123                         /* OPP High */
 124                         opp-hz = /bits/ 64 <1500000000>;
 125                         opp-microvolt = <1210000 950000 1250000>,
 126                                         <1210000 950000 1250000>;
 127                         opp-supported-hw = <0xFF 0x04>;
 128                 };
 129         };
 130
 131         /*
 132          * XXX: Use a flat representation of the SOC interconnect.
 133          * The real OMAP interconnect network is quite complex.
 134          * Since it will not bring real advantage to represent that in DT for
 135          * the moment, just use a fake OCP bus entry to represent the whole bus
 136          * hierarchy.
 137          */
 138         ocp: ocp {
 139                 compatible = "simple-pm-bus";
 140                 power-domains = <&prm_core>;
 141                 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
 142                          <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0x0 0x0 0x0 0xc0000000>;
 146                 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
 147
 148                 l3-noc@44000000 {
 149                         compatible = "ti,dra7-l3-noc";
 150                         reg = <0x44000000 0x1000>,
 151                               <0x45000000 0x1000>;
 152                         interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 153                                               <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 154                 };
 155
 156                 l4_cfg: interconnect@4a000000 {
 157                 };
 158                 l4_wkup: interconnect@4ae00000 {
 159                 };
 160                 l4_per1: interconnect@48000000 {
 161                 };
 162
 163                 target-module@48210000 {
 164                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
 165                         power-domains = <&prm_mpu>;
 166                         clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
 167                         clock-names = "fck";
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                         ranges = <0 0x48210000 0x1f0000>;
 171
 172                         mpu {
 173                                 compatible = "ti,omap5-mpu";
 174                         };
 175                 };
 176
 177                 l4_per2: interconnect@48400000 {
 178                 };
 179                 l4_per3: interconnect@48800000 {
 180                 };
 181
 182                 /*
 183                  * Register access seems to have complex dependencies and also
 184                  * seems to need an enabled phy. See the TRM chapter for "Table
 185                  * 26-678. Main Sequence PCIe Controller Global Initialization"
 186                  * and also dra7xx_pcie_probe().
 187                  */
 188                 axi0: target-module@51000000 {
 189                         compatible = "ti,sysc-omap4", "ti,sysc";
 190                         power-domains = <&prm_l3init>;
 191                         resets = <&prm_l3init 0>;
 192                         reset-names = "rstctrl";
 193                         clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
 194                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
 195                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
 196                         clock-names = "fck", "phy-clk", "phy-clk-div";
 197                         #size-cells = <1>;
 198                         #address-cells = <1>;
 199                         ranges = <0x51000000 0x51000000 0x3000>,
 200                                  <0x20000000 0x20000000 0x10000000>;
 201                         dma-ranges;
 202                         /**
 203                          * To enable PCI endpoint mode, disable the pcie1_rc
 204                          * node and enable pcie1_ep mode.
 205                          */
 206                         pcie1_rc: pcie@51000000 {
 207                                 reg = <0x51000000 0x2000>,
 208                                       <0x51002000 0x14c>,
 209                                       <0x20001000 0x2000>;
 210                                 reg-names = "rc_dbics", "ti_conf", "config";
 211                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 212                                 #address-cells = <3>;
 213                                 #size-cells = <2>;
 214                                 device_type = "pci";
 215                                 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
 216                                          <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
 217                                 bus-range = <0x00 0xff>;
 218                                 #interrupt-cells = <1>;
 219                                 num-lanes = <1>;
 220                                 linux,pci-domain = <0>;
 221                                 phys = <&pcie1_phy>;
 222                                 phy-names = "pcie-phy0";
 223                                 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 224                                 interrupt-map-mask = <0 0 0 7>;
 225                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 226                                                 <0 0 0 2 &pcie1_intc 2>,
 227                                                 <0 0 0 3 &pcie1_intc 3>,
 228                                                 <0 0 0 4 &pcie1_intc 4>;
 229                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
 230                                 status = "disabled";
 231                                 pcie1_intc: interrupt-controller {
 232                                         interrupt-controller;
 233                                         #address-cells = <0>;
 234                                         #interrupt-cells = <1>;
 235                                 };
 236                         };
 237
 238                         pcie1_ep: pcie_ep@51000000 {
 239                                 reg = <0x51000000 0x28>,
 240                                       <0x51002000 0x14c>,
 241                                       <0x51001000 0x28>,
 242                                       <0x20001000 0x10000000>;
 243                                 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
 244                                 interrupts = <0 232 0x4>;
 245                                 num-lanes = <1>;
 246                                 num-ib-windows = <4>;
 247                                 num-ob-windows = <16>;
 248                                 phys = <&pcie1_phy>;
 249                                 phy-names = "pcie-phy0";
 250                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
 251                                 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 252                                 status = "disabled";
 253                         };
 254                 };
 255
 256                 /*
 257                  * Register access seems to have complex dependencies and also
 258                  * seems to need an enabled phy. See the TRM chapter for "Table
 259                  * 26-678. Main Sequence PCIe Controller Global Initialization"
 260                  * and also dra7xx_pcie_probe().
 261                  */
 262                 axi1: target-module@51800000 {
 263                         compatible = "ti,sysc-omap4", "ti,sysc";
 264                         clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
 265                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
 266                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
 267                         clock-names = "fck", "phy-clk", "phy-clk-div";
 268                         power-domains = <&prm_l3init>;
 269                         resets = <&prm_l3init 1>;
 270                         reset-names = "rstctrl";
 271                         #size-cells = <1>;
 272                         #address-cells = <1>;
 273                         ranges = <0x51800000 0x51800000 0x3000>,
 274                                  <0x30000000 0x30000000 0x10000000>;
 275                         dma-ranges;
 276                         status = "disabled";
 277                         pcie2_rc: pcie@51800000 {
 278                                 reg = <0x51800000 0x2000>,
 279                                       <0x51802000 0x14c>,
 280                                       <0x30001000 0x2000>;
 281                                 reg-names = "rc_dbics", "ti_conf", "config";
 282                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 283                                 #address-cells = <3>;
 284                                 #size-cells = <2>;
 285                                 device_type = "pci";
 286                                 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
 287                                          <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
 288                                 bus-range = <0x00 0xff>;
 289                                 #interrupt-cells = <1>;
 290                                 num-lanes = <1>;
 291                                 linux,pci-domain = <1>;
 292                                 phys = <&pcie2_phy>;
 293                                 phy-names = "pcie-phy0";
 294                                 interrupt-map-mask = <0 0 0 7>;
 295                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 296                                                 <0 0 0 2 &pcie2_intc 2>,
 297                                                 <0 0 0 3 &pcie2_intc 3>,
 298                                                 <0 0 0 4 &pcie2_intc 4>;
 299                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
 300                                 pcie2_intc: interrupt-controller {
 301                                         interrupt-controller;
 302                                         #address-cells = <0>;
 303                                         #interrupt-cells = <1>;
 304                                 };
 305                         };
 306                 };
 307
 308                 ocmcram1: ocmcram@40300000 {
 309                         compatible = "mmio-sram";
 310                         reg = <0x40300000 0x80000>;
 311                         ranges = <0x0 0x40300000 0x80000>;
 312                         #address-cells = <1>;
 313                         #size-cells = <1>;
 314                         /*
 315                          * This is a placeholder for an optional reserved
 316                          * region for use by secure software. The size
 317                          * of this region is not known until runtime so it
 318                          * is set as zero to either be updated to reserve
 319                          * space or left unchanged to leave all SRAM for use.
 320                          * On HS parts that that require the reserved region
 321                          * either the bootloader can update the size to
 322                          * the required amount or the node can be overridden
 323                          * from the board dts file for the secure platform.
 324                          */
 325                         sram-hs@0 {
 326                                 compatible = "ti,secure-ram";
 327                                 reg = <0x0 0x0>;
 328                         };
 329                 };
 330
 331                 /*
 332                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 333                  * DRA7xx and AM57xx variants. Confirm availability in
 334                  * the data manual for the exact part number in use
 335                  * before enabling these nodes in the board dts file.
 336                  */
 337                 ocmcram2: ocmcram@40400000 {
 338                         status = "disabled";
 339                         compatible = "mmio-sram";
 340                         reg = <0x40400000 0x100000>;
 341                         ranges = <0x0 0x40400000 0x100000>;
 342                         #address-cells = <1>;
 343                         #size-cells = <1>;
 344                 };
 345
 346                 ocmcram3: ocmcram@40500000 {
 347                         status = "disabled";
 348                         compatible = "mmio-sram";
 349                         reg = <0x40500000 0x100000>;
 350                         ranges = <0x0 0x40500000 0x100000>;
 351                         #address-cells = <1>;
 352                         #size-cells = <1>;
 353                 };
 354
 355                 bandgap: bandgap@4a0021e0 {
 356                         reg = <0x4a0021e0 0xc
 357                                 0x4a00232c 0xc
 358                                 0x4a002380 0x2c
 359                                 0x4a0023C0 0x3c
 360                                 0x4a002564 0x8
 361                                 0x4a002574 0x50>;
 362                                 compatible = "ti,dra752-bandgap";
 363                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 364                                 #thermal-sensor-cells = <1>;
 365                 };
 366
 367                 dsp1_system: dsp_system@40d00000 {
 368                         compatible = "syscon";
 369                         reg = <0x40d00000 0x100>;
 370                 };
 371
 372                 dra7_iodelay_core: padconf@4844a000 {
 373                         compatible = "ti,dra7-iodelay";
 374                         reg = <0x4844a000 0x0d1c>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         #pinctrl-cells = <2>;
 378                 };
 379
 380                 target-module@43300000 {
 381                         compatible = "ti,sysc-omap4", "ti,sysc";
 382                         reg = <0x43300000 0x4>,
 383                               <0x43300010 0x4>;
 384                         reg-names = "rev", "sysc";
 385                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 386                                         <SYSC_IDLE_NO>,
 387                                         <SYSC_IDLE_SMART>;
 388                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 389                                         <SYSC_IDLE_NO>,
 390                                         <SYSC_IDLE_SMART>;
 391                         clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
 392                         clock-names = "fck";
 393                         #address-cells = <1>;
 394                         #size-cells = <1>;
 395                         ranges = <0x0 0x43300000 0x100000>;
 396
 397                         edma: dma@0 {
 398                                 compatible = "ti,edma3-tpcc";
 399                                 reg = <0 0x100000>;
 400                                 reg-names = "edma3_cc";
 401                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 402                                              <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 403                                              <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 404                                 interrupt-names = "edma3_ccint", "edma3_mperr",
 405                                                   "edma3_ccerrint";
 406                                 dma-requests = <64>;
 407                                 #dma-cells = <2>;
 408
 409                                 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 410
 411                                 /*
 412                                 * memcpy is disabled, can be enabled with:
 413                                 * ti,edma-memcpy-channels = <20 21>;
 414                                 * for example. Note that these channels need to be
 415                                 * masked in the xbar as well.
 416                                 */
 417                         };
 418                 };
 419
 420                 target-module@43400000 {
 421                         compatible = "ti,sysc-omap4", "ti,sysc";
 422                         reg = <0x43400000 0x4>,
 423                               <0x43400010 0x4>;
 424                         reg-names = "rev", "sysc";
 425                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 426                                         <SYSC_IDLE_NO>,
 427                                         <SYSC_IDLE_SMART>;
 428                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 429                                         <SYSC_IDLE_NO>,
 430                                         <SYSC_IDLE_SMART>;
 431                         clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
 432                         clock-names = "fck";
 433                         #address-cells = <1>;
 434                         #size-cells = <1>;
 435                         ranges = <0x0 0x43400000 0x100000>;
 436
 437                         edma_tptc0: dma@0 {
 438                                 compatible = "ti,edma3-tptc";
 439                                 reg = <0 0x100000>;
 440                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 441                                 interrupt-names = "edma3_tcerrint";
 442                         };
 443                 };
 444
 445                 target-module@43500000 {
 446                         compatible = "ti,sysc-omap4", "ti,sysc";
 447                         reg = <0x43500000 0x4>,
 448                               <0x43500010 0x4>;
 449                         reg-names = "rev", "sysc";
 450                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 451                                         <SYSC_IDLE_NO>,
 452                                         <SYSC_IDLE_SMART>;
 453                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 454                                         <SYSC_IDLE_NO>,
 455                                         <SYSC_IDLE_SMART>;
 456                         clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
 457                         clock-names = "fck";
 458                         #address-cells = <1>;
 459                         #size-cells = <1>;
 460                         ranges = <0x0 0x43500000 0x100000>;
 461
 462                         edma_tptc1: dma@0 {
 463                                 compatible = "ti,edma3-tptc";
 464                                 reg = <0 0x100000>;
 465                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 466                                 interrupt-names = "edma3_tcerrint";
 467                         };
 468                 };
 469
 470                 target-module@4e000000 {
 471                         compatible = "ti,sysc-omap2", "ti,sysc";
 472                         reg = <0x4e000000 0x4>,
 473                               <0x4e000010 0x4>;
 474                         reg-names = "rev", "sysc";
 475                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 476                                         <SYSC_IDLE_NO>,
 477                                         <SYSC_IDLE_SMART>;
 478                         ranges = <0x0 0x4e000000 0x2000000>;
 479                         #size-cells = <1>;
 480                         #address-cells = <1>;
 481
 482                         dmm@0 {
 483                                 compatible = "ti,omap5-dmm";
 484                                 reg = <0 0x800>;
 485                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 486                         };
 487                 };
 488
 489                 ipu1: ipu@58820000 {
 490                         compatible = "ti,dra7-ipu";
 491                         reg = <0x58820000 0x10000>;
 492                         reg-names = "l2ram";
 493                         iommus = <&mmu_ipu1>;
 494                         status = "disabled";
 495                         resets = <&prm_ipu 0>, <&prm_ipu 1>;
 496                         clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
 497                         firmware-name = "dra7-ipu1-fw.xem4";
 498                 };
 499
 500                 ipu2: ipu@55020000 {
 501                         compatible = "ti,dra7-ipu";
 502                         reg = <0x55020000 0x10000>;
 503                         reg-names = "l2ram";
 504                         iommus = <&mmu_ipu2>;
 505                         status = "disabled";
 506                         resets = <&prm_core 0>, <&prm_core 1>;
 507                         clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
 508                         firmware-name = "dra7-ipu2-fw.xem4";
 509                 };
 510
 511                 dsp1: dsp@40800000 {
 512                         compatible = "ti,dra7-dsp";
 513                         reg = <0x40800000 0x48000>,
 514                               <0x40e00000 0x8000>,
 515                               <0x40f00000 0x8000>;
 516                         reg-names = "l2ram", "l1pram", "l1dram";
 517                         ti,bootreg = <&scm_conf 0x55c 10>;
 518                         iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
 519                         status = "disabled";
 520                         resets = <&prm_dsp1 0>;
 521                         clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
 522                         firmware-name = "dra7-dsp1-fw.xe66";
 523                 };
 524
 525                 target-module@40d01000 {
 526                         compatible = "ti,sysc-omap2", "ti,sysc";
 527                         reg = <0x40d01000 0x4>,
 528                               <0x40d01010 0x4>,
 529                               <0x40d01014 0x4>;
 530                         reg-names = "rev", "sysc", "syss";
 531                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 532                                         <SYSC_IDLE_NO>,
 533                                         <SYSC_IDLE_SMART>;
 534                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 535                                          SYSC_OMAP2_SOFTRESET |
 536                                          SYSC_OMAP2_AUTOIDLE)>;
 537                         clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
 538                         clock-names = "fck";
 539                         resets = <&prm_dsp1 1>;
 540                         reset-names = "rstctrl";
 541                         ranges = <0x0 0x40d01000 0x1000>;
 542                         #size-cells = <1>;
 543                         #address-cells = <1>;
 544
 545                         mmu0_dsp1: mmu@0 {
 546                                 compatible = "ti,dra7-dsp-iommu";
 547                                 reg = <0x0 0x100>;
 548                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 549                                 #iommu-cells = <0>;
 550                                 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
 551                         };
 552                 };
 553
 554                 target-module@40d02000 {
 555                         compatible = "ti,sysc-omap2", "ti,sysc";
 556                         reg = <0x40d02000 0x4>,
 557                               <0x40d02010 0x4>,
 558                               <0x40d02014 0x4>;
 559                         reg-names = "rev", "sysc", "syss";
 560                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 561                                         <SYSC_IDLE_NO>,
 562                                         <SYSC_IDLE_SMART>;
 563                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 564                                          SYSC_OMAP2_SOFTRESET |
 565                                          SYSC_OMAP2_AUTOIDLE)>;
 566                         clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
 567                         clock-names = "fck";
 568                         resets = <&prm_dsp1 1>;
 569                         reset-names = "rstctrl";
 570                         ranges = <0x0 0x40d02000 0x1000>;
 571                         #size-cells = <1>;
 572                         #address-cells = <1>;
 573
 574                         mmu1_dsp1: mmu@0 {
 575                                 compatible = "ti,dra7-dsp-iommu";
 576                                 reg = <0x0 0x100>;
 577                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 578                                 #iommu-cells = <0>;
 579                                 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
 580                         };
 581                 };
 582
 583                 target-module@58882000 {
 584                         compatible = "ti,sysc-omap2", "ti,sysc";
 585                         reg = <0x58882000 0x4>,
 586                               <0x58882010 0x4>,
 587                               <0x58882014 0x4>;
 588                         reg-names = "rev", "sysc", "syss";
 589                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 590                                         <SYSC_IDLE_NO>,
 591                                         <SYSC_IDLE_SMART>;
 592                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 593                                          SYSC_OMAP2_SOFTRESET |
 594                                          SYSC_OMAP2_AUTOIDLE)>;
 595                         clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
 596                         clock-names = "fck";
 597                         resets = <&prm_ipu 2>;
 598                         reset-names = "rstctrl";
 599                         #address-cells = <1>;
 600                         #size-cells = <1>;
 601                         ranges = <0x0 0x58882000 0x100>;
 602
 603                         mmu_ipu1: mmu@0 {
 604                                 compatible = "ti,dra7-iommu";
 605                                 reg = <0x0 0x100>;
 606                                 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
 607                                 #iommu-cells = <0>;
 608                                 ti,iommu-bus-err-back;
 609                         };
 610                 };
 611
 612                 target-module@55082000 {
 613                         compatible = "ti,sysc-omap2", "ti,sysc";
 614                         reg = <0x55082000 0x4>,
 615                               <0x55082010 0x4>,
 616                               <0x55082014 0x4>;
 617                         reg-names = "rev", "sysc", "syss";
 618                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 619                                         <SYSC_IDLE_NO>,
 620                                         <SYSC_IDLE_SMART>;
 621                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 622                                          SYSC_OMAP2_SOFTRESET |
 623                                          SYSC_OMAP2_AUTOIDLE)>;
 624                         clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
 625                         clock-names = "fck";
 626                         resets = <&prm_core 2>;
 627                         reset-names = "rstctrl";
 628                         #address-cells = <1>;
 629                         #size-cells = <1>;
 630                         ranges = <0x0 0x55082000 0x100>;
 631
 632                         mmu_ipu2: mmu@0 {
 633                                 compatible = "ti,dra7-iommu";
 634                                 reg = <0x0 0x100>;
 635                                 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 636                                 #iommu-cells = <0>;
 637                                 ti,iommu-bus-err-back;
 638                         };
 639                 };
 640
 641                 abb_mpu: regulator-abb-mpu {
 642                         compatible = "ti,abb-v3";
 643                         regulator-name = "abb_mpu";
 644                         #address-cells = <0>;
 645                         #size-cells = <0>;
 646                         clocks = <&sys_clkin1>;
 647                         ti,settling-time = <50>;
 648                         ti,clock-cycles = <16>;
 649
 650                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 651                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
 652                               <0x4ae0c158 0x4>;
 653                         reg-names = "setup-address", "control-address",
 654                                     "int-address", "efuse-address",
 655                                     "ldo-address";
 656                         ti,tranxdone-status-mask = <0x80>;
 657                         /* LDOVBBMPU_FBB_MUX_CTRL */
 658                         ti,ldovbb-override-mask = <0x400>;
 659                         /* LDOVBBMPU_FBB_VSET_OUT */
 660                         ti,ldovbb-vset-mask = <0x1F>;
 661
 662                         /*
 663                          * NOTE: only FBB mode used but actual vset will
 664                          * determine final biasing
 665                          */
 666                         ti,abb_info = <
 667                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 668                         1060000         0       0x0     0 0x02000000 0x01F00000
 669                         1160000         0       0x4     0 0x02000000 0x01F00000
 670                         1210000         0       0x8     0 0x02000000 0x01F00000
 671                         >;
 672                 };
 673
 674                 abb_ivahd: regulator-abb-ivahd {
 675                         compatible = "ti,abb-v3";
 676                         regulator-name = "abb_ivahd";
 677                         #address-cells = <0>;
 678                         #size-cells = <0>;
 679                         clocks = <&sys_clkin1>;
 680                         ti,settling-time = <50>;
 681                         ti,clock-cycles = <16>;
 682
 683                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 684                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
 685                               <0x4a002470 0x4>;
 686                         reg-names = "setup-address", "control-address",
 687                                     "int-address", "efuse-address",
 688                                     "ldo-address";
 689                         ti,tranxdone-status-mask = <0x40000000>;
 690                         /* LDOVBBIVA_FBB_MUX_CTRL */
 691                         ti,ldovbb-override-mask = <0x400>;
 692                         /* LDOVBBIVA_FBB_VSET_OUT */
 693                         ti,ldovbb-vset-mask = <0x1F>;
 694
 695                         /*
 696                          * NOTE: only FBB mode used but actual vset will
 697                          * determine final biasing
 698                          */
 699                         ti,abb_info = <
 700                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 701                         1055000         0       0x0     0 0x02000000 0x01F00000
 702                         1150000         0       0x4     0 0x02000000 0x01F00000
 703                         1250000         0       0x8     0 0x02000000 0x01F00000
 704                         >;
 705                 };
 706
 707                 abb_dspeve: regulator-abb-dspeve {
 708                         compatible = "ti,abb-v3";
 709                         regulator-name = "abb_dspeve";
 710                         #address-cells = <0>;
 711                         #size-cells = <0>;
 712                         clocks = <&sys_clkin1>;
 713                         ti,settling-time = <50>;
 714                         ti,clock-cycles = <16>;
 715
 716                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 717                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
 718                               <0x4a00246c 0x4>;
 719                         reg-names = "setup-address", "control-address",
 720                                     "int-address", "efuse-address",
 721                                     "ldo-address";
 722                         ti,tranxdone-status-mask = <0x20000000>;
 723                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 724                         ti,ldovbb-override-mask = <0x400>;
 725                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 726                         ti,ldovbb-vset-mask = <0x1F>;
 727
 728                         /*
 729                          * NOTE: only FBB mode used but actual vset will
 730                          * determine final biasing
 731                          */
 732                         ti,abb_info = <
 733                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 734                         1055000         0       0x0     0 0x02000000 0x01F00000
 735                         1150000         0       0x4     0 0x02000000 0x01F00000
 736                         1250000         0       0x8     0 0x02000000 0x01F00000
 737                         >;
 738                 };
 739
 740                 abb_gpu: regulator-abb-gpu {
 741                         compatible = "ti,abb-v3";
 742                         regulator-name = "abb_gpu";
 743                         #address-cells = <0>;
 744                         #size-cells = <0>;
 745                         clocks = <&sys_clkin1>;
 746                         ti,settling-time = <50>;
 747                         ti,clock-cycles = <16>;
 748
 749                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 750                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
 751                               <0x4ae0c154 0x4>;
 752                         reg-names = "setup-address", "control-address",
 753                                     "int-address", "efuse-address",
 754                                     "ldo-address";
 755                         ti,tranxdone-status-mask = <0x10000000>;
 756                         /* LDOVBBGPU_FBB_MUX_CTRL */
 757                         ti,ldovbb-override-mask = <0x400>;
 758                         /* LDOVBBGPU_FBB_VSET_OUT */
 759                         ti,ldovbb-vset-mask = <0x1F>;
 760
 761                         /*
 762                          * NOTE: only FBB mode used but actual vset will
 763                          * determine final biasing
 764                          */
 765                         ti,abb_info = <
 766                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 767                         1090000         0       0x0     0 0x02000000 0x01F00000
 768                         1210000         0       0x4     0 0x02000000 0x01F00000
 769                         1280000         0       0x8     0 0x02000000 0x01F00000
 770                         >;
 771                 };
 772
 773                 target-module@4b300000 {
 774                         compatible = "ti,sysc-omap4", "ti,sysc";
 775                         reg = <0x4b300000 0x4>,
 776                               <0x4b300010 0x4>;
 777                         reg-names = "rev", "sysc";
 778                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 779                                         <SYSC_IDLE_NO>,
 780                                         <SYSC_IDLE_SMART>,
 781                                         <SYSC_IDLE_SMART_WKUP>;
 782                         clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
 783                         clock-names = "fck";
 784                         #address-cells = <1>;
 785                         #size-cells = <1>;
 786                         ranges = <0x0 0x4b300000 0x1000>,
 787                                  <0x5c000000 0x5c000000 0x4000000>;
 788
 789                         qspi: spi@0 {
 790                                 compatible = "ti,dra7xxx-qspi";
 791                                 reg = <0 0x100>,
 792                                       <0x5c000000 0x4000000>;
 793                                 reg-names = "qspi_base", "qspi_mmap";
 794                                 syscon-chipselects = <&scm_conf 0x558>;
 795                                 #address-cells = <1>;
 796                                 #size-cells = <0>;
 797                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
 798                                 clock-names = "fck";
 799                                 num-cs = <4>;
 800                                 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 801                                 status = "disabled";
 802                         };
 803                 };
 804
 805                 /* OCP2SCP1 */
 806                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
 807
 808                 target-module@50000000 {
 809                         compatible = "ti,sysc-omap2", "ti,sysc";
 810                         reg = <0x50000000 4>,
 811                               <0x50000010 4>,
 812                               <0x50000014 4>;
 813                         reg-names = "rev", "sysc", "syss";
 814                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 815                                         <SYSC_IDLE_NO>,
 816                                         <SYSC_IDLE_SMART>;
 817                         ti,syss-mask = <1>;
 818                         clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
 819                         clock-names = "fck";
 820                         #address-cells = <1>;
 821                         #size-cells = <1>;
 822                         ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
 823                                  <0x00000000 0x00000000 0x40000000>; /* data */
 824
 825                         gpmc: gpmc@50000000 {
 826                                 compatible = "ti,am3352-gpmc";
 827                                 reg = <0x50000000 0x37c>;      /* device IO registers */
 828                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 829                                 dmas = <&edma_xbar 4 0>;
 830                                 dma-names = "rxtx";
 831                                 gpmc,num-cs = <8>;
 832                                 gpmc,num-waitpins = <2>;
 833                                 #address-cells = <2>;
 834                                 #size-cells = <1>;
 835                                 interrupt-controller;
 836                                 #interrupt-cells = <2>;
 837                                 gpio-controller;
 838                                 #gpio-cells = <2>;
 839                                 status = "disabled";
 840                         };
 841                 };
 842
 843                 target-module@56000000 {
 844                         compatible = "ti,sysc-omap4", "ti,sysc";
 845                         reg = <0x5600fe00 0x4>,
 846                               <0x5600fe10 0x4>;
 847                         reg-names = "rev", "sysc";
 848                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 849                                         <SYSC_IDLE_NO>,
 850                                         <SYSC_IDLE_SMART>;
 851                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 852                                         <SYSC_IDLE_NO>,
 853                                         <SYSC_IDLE_SMART>;
 854                         clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
 855                         clock-names = "fck";
 856                         #address-cells = <1>;
 857                         #size-cells = <1>;
 858                         ranges = <0 0x56000000 0x2000000>;
 859                 };
 860
 861                 crossbar_mpu: crossbar@4a002a48 {
 862                         compatible = "ti,irq-crossbar";
 863                         reg = <0x4a002a48 0x130>;
 864                         interrupt-controller;
 865                         interrupt-parent = <&wakeupgen>;
 866                         #interrupt-cells = <3>;
 867                         ti,max-irqs = <160>;
 868                         ti,max-crossbar-sources = <MAX_SOURCES>;
 869                         ti,reg-size = <2>;
 870                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
 871                         ti,irqs-skip = <10 133 139 140>;
 872                         ti,irqs-safe-map = <0>;
 873                 };
 874
 875                 target-module@58000000 {
 876                         compatible = "ti,sysc-omap2", "ti,sysc";
 877                         reg = <0x58000000 4>,
 878                               <0x58000014 4>;
 879                         reg-names = "rev", "syss";
 880                         ti,syss-mask = <1>;
 881                         clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
 882                                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
 883                                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>,
 884                                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>;
 885                         clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
 886                         #address-cells = <1>;
 887                         #size-cells = <1>;
 888                         ranges = <0 0x58000000 0x800000>;
 889
 890                         dss: dss@0 {
 891                                 compatible = "ti,dra7-dss";
 892                                 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
 893                                 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
 894                                 status = "disabled";
 895                                 /* CTRL_CORE_DSS_PLL_CONTROL */
 896                                 syscon-pll-ctrl = <&scm_conf 0x538>;
 897                                 #address-cells = <1>;
 898                                 #size-cells = <1>;
 899                                 ranges = <0 0 0x800000>;
 900
 901                                 target-module@1000 {
 902                                         compatible = "ti,sysc-omap2", "ti,sysc";
 903                                         reg = <0x1000 0x4>,
 904                                               <0x1010 0x4>,
 905                                               <0x1014 0x4>;
 906                                         reg-names = "rev", "sysc", "syss";
 907                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 908                                                         <SYSC_IDLE_NO>,
 909                                                         <SYSC_IDLE_SMART>;
 910                                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 911                                                         <SYSC_IDLE_NO>,
 912                                                         <SYSC_IDLE_SMART>;
 913                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 914                                                          SYSC_OMAP2_ENAWAKEUP |
 915                                                          SYSC_OMAP2_SOFTRESET |
 916                                                          SYSC_OMAP2_AUTOIDLE)>;
 917                                         ti,syss-mask = <1>;
 918                                         clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
 919                                         clock-names = "fck";
 920                                         #address-cells = <1>;
 921                                         #size-cells = <1>;
 922                                         ranges = <0 0x1000 0x1000>;
 923
 924                                         dispc@0 {
 925                                                 compatible = "ti,dra7-dispc";
 926                                                 reg = <0 0x1000>;
 927                                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 928                                                 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
 929                                                 clock-names = "fck";
 930                                                 /* CTRL_CORE_SMA_SW_1 */
 931                                                 syscon-pol = <&scm_conf 0x534>;
 932                                         };
 933                                 };
 934
 935                                 target-module@40000 {
 936                                         compatible = "ti,sysc-omap4", "ti,sysc";
 937                                         reg = <0x40000 0x4>,
 938                                               <0x40010 0x4>;
 939                                         reg-names = "rev", "sysc";
 940                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 941                                                         <SYSC_IDLE_NO>,
 942                                                         <SYSC_IDLE_SMART>,
 943                                                         <SYSC_IDLE_SMART_WKUP>;
 944                                         ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
 945                                         clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
 946                                                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
 947                                         clock-names = "fck", "dss_clk";
 948                                         #address-cells = <1>;
 949                                         #size-cells = <1>;
 950                                         ranges = <0 0x40000 0x40000>;
 951
 952                                         hdmi: encoder@0 {
 953                                                 compatible = "ti,dra7-hdmi";
 954                                                 reg = <0 0x200>,
 955                                                       <0x200 0x80>,
 956                                                       <0x300 0x80>,
 957                                                       <0x20000 0x19000>;
 958                                                 reg-names = "wp", "pll", "phy", "core";
 959                                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 960                                                 status = "disabled";
 961                                                 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
 962                                                          <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
 963                                                 clock-names = "fck", "sys_clk";
 964                                                 dmas = <&sdma_xbar 76>;
 965                                                 dma-names = "audio_tx";
 966                                         };
 967                                 };
 968                         };
 969                 };
 970
 971                 target-module@59000000 {
 972                         compatible = "ti,sysc-omap4", "ti,sysc";
 973                         reg = <0x59000020 0x4>;
 974                         reg-names = "rev";
 975                         clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
 976                         clock-names = "fck";
 977                         #address-cells = <1>;
 978                         #size-cells = <1>;
 979                         ranges = <0x0 0x59000000 0x1000>;
 980
 981                         bb2d: gpu@0 {
 982                                 compatible = "vivante,gc";
 983                                 reg = <0x0 0x700>;
 984                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 985                                 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
 986                                 clock-names = "core";
 987                         };
 988                 };
 989
 990                 aes1_target: target-module@4b500000 {
 991                         compatible = "ti,sysc-omap2", "ti,sysc";
 992                         reg = <0x4b500080 0x4>,
 993                               <0x4b500084 0x4>,
 994                               <0x4b500088 0x4>;
 995                         reg-names = "rev", "sysc", "syss";
 996                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 997                                          SYSC_OMAP2_AUTOIDLE)>;
 998                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 999                                         <SYSC_IDLE_NO>,
1000                                         <SYSC_IDLE_SMART>,
1001                                         <SYSC_IDLE_SMART_WKUP>;
1002                         ti,syss-mask = <1>;
1003                         /* Domains (P, C): per_pwrdm, l4sec_clkdm */
1004                         clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
1005                         clock-names = "fck";
1006                         #address-cells = <1>;
1007                         #size-cells = <1>;
1008                         ranges = <0x0 0x4b500000 0x1000>;
1009
1010                         aes1: aes@0 {
1011                                 compatible = "ti,omap4-aes";
1012                                 reg = <0 0xa0>;
1013                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1014                                 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1015                                 dma-names = "tx", "rx";
1016                                 clocks = <&l3_iclk_div>;
1017                                 clock-names = "fck";
1018                         };
1019                 };
1020
1021                 aes2_target: target-module@4b700000 {
1022                         compatible = "ti,sysc-omap2", "ti,sysc";
1023                         reg = <0x4b700080 0x4>,
1024                               <0x4b700084 0x4>,
1025                               <0x4b700088 0x4>;
1026                         reg-names = "rev", "sysc", "syss";
1027                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1028                                          SYSC_OMAP2_AUTOIDLE)>;
1029                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1030                                         <SYSC_IDLE_NO>,
1031                                         <SYSC_IDLE_SMART>,
1032                                         <SYSC_IDLE_SMART_WKUP>;
1033                         ti,syss-mask = <1>;
1034                         /* Domains (P, C): per_pwrdm, l4sec_clkdm */
1035                         clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
1036                         clock-names = "fck";
1037                         #address-cells = <1>;
1038                         #size-cells = <1>;
1039                         ranges = <0x0 0x4b700000 0x1000>;
1040
1041                         aes2: aes@0 {
1042                                 compatible = "ti,omap4-aes";
1043                                 reg = <0 0xa0>;
1044                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1045                                 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1046                                 dma-names = "tx", "rx";
1047                                 clocks = <&l3_iclk_div>;
1048                                 clock-names = "fck";
1049                         };
1050                 };
1051
1052                 sham1_target: target-module@4b101000 {
1053                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
1054                         reg = <0x4b101100 0x4>,
1055                               <0x4b101110 0x4>,
1056                               <0x4b101114 0x4>;
1057                         reg-names = "rev", "sysc", "syss";
1058                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1059                                          SYSC_OMAP2_AUTOIDLE)>;
1060                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1061                                         <SYSC_IDLE_NO>,
1062                                         <SYSC_IDLE_SMART>;
1063                         ti,syss-mask = <1>;
1064                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1065                         clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
1066                         clock-names = "fck";
1067                         #address-cells = <1>;
1068                         #size-cells = <1>;
1069                         ranges = <0x0 0x4b101000 0x1000>;
1070
1071                         sham1: sham@0 {
1072                                 compatible = "ti,omap5-sham";
1073                                 reg = <0 0x300>;
1074                                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1075                                 dmas = <&edma_xbar 119 0>;
1076                                 dma-names = "rx";
1077                                 clocks = <&l3_iclk_div>;
1078                                 clock-names = "fck";
1079                         };
1080                 };
1081
1082                 sham2_target: target-module@42701000 {
1083                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
1084                         reg = <0x42701100 0x4>,
1085                               <0x42701110 0x4>,
1086                               <0x42701114 0x4>;
1087                         reg-names = "rev", "sysc", "syss";
1088                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1089                                          SYSC_OMAP2_AUTOIDLE)>;
1090                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1091                                         <SYSC_IDLE_NO>,
1092                                         <SYSC_IDLE_SMART>;
1093                         ti,syss-mask = <1>;
1094                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1095                         clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
1096                         clock-names = "fck";
1097                         #address-cells = <1>;
1098                         #size-cells = <1>;
1099                         ranges = <0x0 0x42701000 0x1000>;
1100
1101                         sham2: sham@0 {
1102                                 compatible = "ti,omap5-sham";
1103                                 reg = <0 0x300>;
1104                                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
1105                                 dmas = <&edma_xbar 165 0>;
1106                                 dma-names = "rx";
1107                                 clocks = <&l3_iclk_div>;
1108                                 clock-names = "fck";
1109                         };
1110                 };
1111
1112                 iva_hd_target: target-module@5a000000 {
1113                         compatible = "ti,sysc-omap4", "ti,sysc";
1114                         reg = <0x5a05a400 0x4>,
1115                               <0x5a05a410 0x4>;
1116                         reg-names = "rev", "sysc";
1117                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
1118                                         <SYSC_IDLE_NO>,
1119                                         <SYSC_IDLE_SMART>;
1120                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1121                                         <SYSC_IDLE_NO>,
1122                                         <SYSC_IDLE_SMART>;
1123                         power-domains = <&prm_iva>;
1124                         resets = <&prm_iva 2>;
1125                         reset-names = "rstctrl";
1126                         clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1127                         clock-names = "fck";
1128                         #address-cells = <1>;
1129                         #size-cells = <1>;
1130                         ranges = <0x5a000000 0x5a000000 0x1000000>,
1131                                  <0x5b000000 0x5b000000 0x1000000>;
1132
1133                         iva {
1134                                 compatible = "ti,ivahd";
1135                         };
1136                 };
1137
1138                 opp_supply_mpu: opp-supply@4a003b20 {
1139                         compatible = "ti,omap5-opp-supply";
1140                         reg = <0x4a003b20 0xc>;
1141                         ti,efuse-settings = <
1142                         /* uV   offset */
1143                         1060000 0x0
1144                         1160000 0x4
1145                         1210000 0x8
1146                         >;
1147                         ti,absolute-max-voltage-uv = <1500000>;
1148                 };
1149
1150         };
1151
1152         thermal_zones: thermal-zones {
1153                 #include "omap4-cpu-thermal.dtsi"
1154                 #include "omap5-gpu-thermal.dtsi"
1155                 #include "omap5-core-thermal.dtsi"
1156                 #include "dra7-dspeve-thermal.dtsi"
1157                 #include "dra7-iva-thermal.dtsi"
1158         };
1159
1160 };
1161
1162 &cpu_thermal {
1163         polling-delay = <500>; /* milliseconds */
1164         coefficients = <0 2000>;
1165 };
1166
1167 &gpu_thermal {
1168         coefficients = <0 2000>;
1169 };
1170
1171 &core_thermal {
1172         coefficients = <0 2000>;
1173 };
1174
1175 &dspeve_thermal {
1176         coefficients = <0 2000>;
1177 };
1178
1179 &iva_thermal {
1180         coefficients = <0 2000>;
1181 };
1182
1183 &cpu_crit {
1184         temperature = <120000>; /* milli Celsius */
1185 };
1186
1187 &core_crit {
1188         temperature = <120000>; /* milli Celsius */
1189 };
1190
1191 &gpu_crit {
1192         temperature = <120000>; /* milli Celsius */
1193 };
1194
1195 &dspeve_crit {
1196         temperature = <120000>; /* milli Celsius */
1197 };
1198
1199 &iva_crit {
1200         temperature = <120000>; /* milli Celsius */
1201 };
1202
1203 #include "dra7-l4.dtsi"
1204 #include "dra7xx-clocks.dtsi"
1205
1206 &prm {
1207         prm_mpu: prm@300 {
1208                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1209                 reg = <0x300 0x100>;
1210                 #power-domain-cells = <0>;
1211         };
1212
1213         prm_dsp1: prm@400 {
1214                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1215                 reg = <0x400 0x100>;
1216                 #reset-cells = <1>;
1217                 #power-domain-cells = <0>;
1218         };
1219
1220         prm_ipu: prm@500 {
1221                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1222                 reg = <0x500 0x100>;
1223                 #reset-cells = <1>;
1224                 #power-domain-cells = <0>;
1225         };
1226
1227         prm_coreaon: prm@628 {
1228                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1229                 reg = <0x628 0xd8>;
1230                 #power-domain-cells = <0>;
1231         };
1232
1233         prm_core: prm@700 {
1234                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1235                 reg = <0x700 0x100>;
1236                 #reset-cells = <1>;
1237                 #power-domain-cells = <0>;
1238         };
1239
1240         prm_iva: prm@f00 {
1241                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1242                 reg = <0xf00 0x100>;
1243                 #reset-cells = <1>;
1244                 #power-domain-cells = <0>;
1245         };
1246
1247         prm_cam: prm@1000 {
1248                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1249                 reg = <0x1000 0x100>;
1250                 #power-domain-cells = <0>;
1251         };
1252
1253         prm_dss: prm@1100 {
1254                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1255                 reg = <0x1100 0x100>;
1256                 #power-domain-cells = <0>;
1257         };
1258
1259         prm_gpu: prm@1200 {
1260                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1261                 reg = <0x1200 0x100>;
1262                 #power-domain-cells = <0>;
1263         };
1264
1265         prm_l3init: prm@1300 {
1266                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1267                 reg = <0x1300 0x100>;
1268                 #reset-cells = <1>;
1269                 #power-domain-cells = <0>;
1270         };
1271
1272         prm_l4per: prm@1400 {
1273                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1274                 reg = <0x1400 0x100>;
1275                 #power-domain-cells = <0>;
1276         };
1277
1278         prm_custefuse: prm@1600 {
1279                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1280                 reg = <0x1600 0x100>;
1281                 #power-domain-cells = <0>;
1282         };
1283
1284         prm_wkupaon: prm@1724 {
1285                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1286                 reg = <0x1724 0x100>;
1287                 #power-domain-cells = <0>;
1288         };
1289
1290         prm_dsp2: prm@1b00 {
1291                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1292                 reg = <0x1b00 0x40>;
1293                 #reset-cells = <1>;
1294                 #power-domain-cells = <0>;
1295         };
1296
1297         prm_eve1: prm@1b40 {
1298                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1299                 reg = <0x1b40 0x40>;
1300                 #power-domain-cells = <0>;
1301         };
1302
1303         prm_eve2: prm@1b80 {
1304                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1305                 reg = <0x1b80 0x40>;
1306                 #power-domain-cells = <0>;
1307         };
1308
1309         prm_eve3: prm@1bc0 {
1310                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1311                 reg = <0x1bc0 0x40>;
1312                 #power-domain-cells = <0>;
1313         };
1314
1315         prm_eve4: prm@1c00 {
1316                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1317                 reg = <0x1c00 0x60>;
1318                 #power-domain-cells = <0>;
1319         };
1320
1321         prm_rtc: prm@1c60 {
1322                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1323                 reg = <0x1c60 0x20>;
1324                 #power-domain-cells = <0>;
1325         };
1326
1327         prm_vpe: prm@1c80 {
1328                 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1329                 reg = <0x1c80 0x80>;
1330                 #power-domain-cells = <0>;
1331         };
1332 };
1333
1334 /* Preferred always-on timer for clockevent */
1335 &timer1_target {
1336         ti,no-reset-on-init;
1337         ti,no-idle;
1338         timer@0 {
1339                 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
1340                 assigned-clock-parents = <&sys_32k_ck>;
1341         };
1342 };
1343
1344 /* Local timers, see ARM architected timer wrap erratum i940 */
1345 &timer15_target {
1346         ti,no-reset-on-init;
1347         ti,no-idle;
1348         timer@0 {
1349                 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1350                 assigned-clock-parents = <&timer_sys_clk_div>;
1351         };
1352 };
1353
1354 &timer16_target {
1355         ti,no-reset-on-init;
1356         ti,no-idle;
1357         timer@0 {
1358                 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1359                 assigned-clock-parents = <&timer_sys_clk_div>;
1360         };
1361 };