1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra30-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra30";
13 interrupt-parent = <&lic>;
18 device_type = "memory";
19 reg = <0x80000000 0x0>;
23 compatible = "nvidia,tegra30-pcie";
25 reg = <0x00003000 0x00000800>, /* PADS registers */
26 <0x00003800 0x00000200>, /* AFI registers */
27 <0x10000000 0x10000000>; /* configuration space */
28 reg-names = "pads", "afi", "cs";
29 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
30 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
31 interrupt-names = "intr", "msi";
33 #interrupt-cells = <1>;
34 interrupt-map-mask = <0 0 0 0>;
35 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
37 bus-range = <0x00 0xff>;
41 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
42 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
43 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
44 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
45 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
46 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
48 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
49 <&tegra_car TEGRA30_CLK_AFI>,
50 <&tegra_car TEGRA30_CLK_PLL_E>,
51 <&tegra_car TEGRA30_CLK_CML0>;
52 clock-names = "pex", "afi", "pll_e", "cml";
53 resets = <&tegra_car 70>,
56 reset-names = "pex", "afi", "pcie_x";
61 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff>;
70 nvidia,num-lanes = <2>;
75 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff>;
84 nvidia,num-lanes = <2>;
89 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
90 reg = <0x001800 0 0 0 0>;
91 bus-range = <0x00 0xff>;
98 nvidia,num-lanes = <2>;
103 compatible = "mmio-sram";
104 reg = <0x40000000 0x40000>;
105 #address-cells = <1>;
107 ranges = <0 0x40000000 0x40000>;
110 reg = <0x400 0x3fc00>;
116 compatible = "nvidia,tegra30-host1x";
117 reg = <0x50000000 0x00024000>;
118 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
119 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
120 interrupt-names = "syncpt", "host1x";
121 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
122 clock-names = "host1x";
123 resets = <&tegra_car 28>;
124 reset-names = "host1x";
125 iommus = <&mc TEGRA_SWGROUP_HC>;
127 #address-cells = <1>;
130 ranges = <0x54000000 0x54000000 0x04000000>;
133 compatible = "nvidia,tegra30-mpe";
134 reg = <0x54040000 0x00040000>;
135 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&tegra_car TEGRA30_CLK_MPE>;
137 resets = <&tegra_car 60>;
140 iommus = <&mc TEGRA_SWGROUP_MPE>;
144 compatible = "nvidia,tegra30-vi";
145 reg = <0x54080000 0x00040000>;
146 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&tegra_car TEGRA30_CLK_VI>;
148 resets = <&tegra_car 20>;
151 iommus = <&mc TEGRA_SWGROUP_VI>;
155 compatible = "nvidia,tegra30-epp";
156 reg = <0x540c0000 0x00040000>;
157 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&tegra_car TEGRA30_CLK_EPP>;
159 resets = <&tegra_car 19>;
162 iommus = <&mc TEGRA_SWGROUP_EPP>;
166 compatible = "nvidia,tegra30-isp";
167 reg = <0x54100000 0x00040000>;
168 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&tegra_car TEGRA30_CLK_ISP>;
170 resets = <&tegra_car 23>;
173 iommus = <&mc TEGRA_SWGROUP_ISP>;
177 compatible = "nvidia,tegra30-gr2d";
178 reg = <0x54140000 0x00040000>;
179 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
181 resets = <&tegra_car 21>;
184 iommus = <&mc TEGRA_SWGROUP_G2>;
188 compatible = "nvidia,tegra30-gr3d";
189 reg = <0x54180000 0x00040000>;
190 clocks = <&tegra_car TEGRA30_CLK_GR3D>,
191 <&tegra_car TEGRA30_CLK_GR3D2>;
192 clock-names = "3d", "3d2";
193 resets = <&tegra_car 24>,
195 reset-names = "3d", "3d2";
197 iommus = <&mc TEGRA_SWGROUP_NV>,
198 <&mc TEGRA_SWGROUP_NV2>;
202 compatible = "nvidia,tegra30-dc";
203 reg = <0x54200000 0x00040000>;
204 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
206 <&tegra_car TEGRA30_CLK_PLL_P>;
207 clock-names = "dc", "parent";
208 resets = <&tegra_car 27>;
211 iommus = <&mc TEGRA_SWGROUP_DC>;
215 interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
216 <&mc TEGRA30_MC_DISPLAY0B &emc>,
217 <&mc TEGRA30_MC_DISPLAY1B &emc>,
218 <&mc TEGRA30_MC_DISPLAY0C &emc>,
219 <&mc TEGRA30_MC_DISPLAYHC &emc>;
220 interconnect-names = "wina",
232 compatible = "nvidia,tegra30-dc";
233 reg = <0x54240000 0x00040000>;
234 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
236 <&tegra_car TEGRA30_CLK_PLL_P>;
237 clock-names = "dc", "parent";
238 resets = <&tegra_car 26>;
241 iommus = <&mc TEGRA_SWGROUP_DCB>;
245 interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
246 <&mc TEGRA30_MC_DISPLAY0BB &emc>,
247 <&mc TEGRA30_MC_DISPLAY1BB &emc>,
248 <&mc TEGRA30_MC_DISPLAY0CB &emc>,
249 <&mc TEGRA30_MC_DISPLAYHCB &emc>;
250 interconnect-names = "wina",
262 compatible = "nvidia,tegra30-hdmi";
263 reg = <0x54280000 0x00040000>;
264 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
266 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
267 clock-names = "hdmi", "parent";
268 resets = <&tegra_car 51>;
269 reset-names = "hdmi";
274 compatible = "nvidia,tegra30-tvo";
275 reg = <0x542c0000 0x00040000>;
276 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&tegra_car TEGRA30_CLK_TVO>;
282 compatible = "nvidia,tegra30-dsi";
283 reg = <0x54300000 0x00040000>;
284 clocks = <&tegra_car TEGRA30_CLK_DSIA>,
285 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
286 clock-names = "dsi", "parent";
287 resets = <&tegra_car 48>;
293 compatible = "nvidia,tegra30-dsi";
294 reg = <0x54400000 0x00040000>;
295 clocks = <&tegra_car TEGRA30_CLK_DSIB>,
296 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
297 clock-names = "dsi", "parent";
298 resets = <&tegra_car 84>;
305 compatible = "arm,cortex-a9-twd-timer";
306 reg = <0x50040600 0x20>;
307 interrupt-parent = <&intc>;
308 interrupts = <GIC_PPI 13
309 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
310 clocks = <&tegra_car TEGRA30_CLK_TWD>;
313 intc: interrupt-controller@50041000 {
314 compatible = "arm,cortex-a9-gic";
315 reg = <0x50041000 0x1000>,
317 interrupt-controller;
318 #interrupt-cells = <3>;
319 interrupt-parent = <&intc>;
322 cache-controller@50043000 {
323 compatible = "arm,pl310-cache";
324 reg = <0x50043000 0x1000>;
325 arm,data-latency = <6 6 2>;
326 arm,tag-latency = <5 5 2>;
331 lic: interrupt-controller@60004000 {
332 compatible = "nvidia,tegra30-ictlr";
333 reg = <0x60004000 0x100>,
338 interrupt-controller;
339 #interrupt-cells = <3>;
340 interrupt-parent = <&intc>;
344 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
345 reg = <0x60005000 0x400>;
346 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
355 tegra_car: clock@60006000 {
356 compatible = "nvidia,tegra30-car";
357 reg = <0x60006000 0x1000>;
362 flow-controller@60007000 {
363 compatible = "nvidia,tegra30-flowctrl";
364 reg = <0x60007000 0x1000>;
367 apbdma: dma@6000a000 {
368 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
369 reg = <0x6000a000 0x1400>;
370 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
403 resets = <&tegra_car 34>;
409 compatible = "nvidia,tegra30-ahb";
410 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
413 actmon: actmon@6000c800 {
414 compatible = "nvidia,tegra30-actmon";
415 reg = <0x6000c800 0x400>;
416 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
418 <&tegra_car TEGRA30_CLK_EMC>;
419 clock-names = "actmon", "emc";
420 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
421 reset-names = "actmon";
422 operating-points-v2 = <&emc_bw_dfs_opp_table>;
423 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
424 interconnect-names = "cpu-read";
425 #cooling-cells = <2>;
428 gpio: gpio@6000d000 {
429 compatible = "nvidia,tegra30-gpio";
430 reg = <0x6000d000 0x1000>;
431 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
441 #interrupt-cells = <2>;
442 interrupt-controller;
444 gpio-ranges = <&pinmux 0 0 248>;
449 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
450 reg = <0x6001a000 0x1000>, /* Syntax Engine */
451 <0x6001b000 0x1000>, /* Video Bitstream Engine */
452 <0x6001c000 0x100>, /* Macroblock Engine */
453 <0x6001c200 0x100>, /* Post-processing Engine */
454 <0x6001c400 0x100>, /* Motion Compensation Engine */
455 <0x6001c600 0x100>, /* Transform Engine */
456 <0x6001c800 0x100>, /* Pixel prediction block */
457 <0x6001ca00 0x100>, /* Video DMA */
458 <0x6001d800 0x400>; /* Video frame controls */
459 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
460 "tfe", "ppb", "vdma", "frameid";
461 iram = <&vde_pool>; /* IRAM region */
462 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
463 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
464 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
465 interrupt-names = "sync-token", "bsev", "sxe";
466 clocks = <&tegra_car TEGRA30_CLK_VDE>;
467 reset-names = "vde", "mc";
468 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
469 iommus = <&mc TEGRA_SWGROUP_VDE>;
473 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
474 reg = <0x70000800 0x64>, /* Chip revision */
475 <0x70000008 0x04>; /* Strapping options */
478 pinmux: pinmux@70000868 {
479 compatible = "nvidia,tegra30-pinmux";
480 reg = <0x70000868 0x0d4>, /* Pad control registers */
481 <0x70003000 0x3e4>; /* Mux registers */
485 * There are two serial driver i.e. 8250 based simple serial
486 * driver and APB DMA based serial driver for higher baudrate
487 * and performace. To enable the 8250 based driver, the compatible
488 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
489 * the APB DMA based serial driver, the compatible is
490 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
492 uarta: serial@70006000 {
493 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
494 reg = <0x70006000 0x40>;
496 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
498 resets = <&tegra_car 6>;
499 reset-names = "serial";
500 dmas = <&apbdma 8>, <&apbdma 8>;
501 dma-names = "rx", "tx";
505 uartb: serial@70006040 {
506 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
507 reg = <0x70006040 0x40>;
509 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
511 resets = <&tegra_car 7>;
512 reset-names = "serial";
513 dmas = <&apbdma 9>, <&apbdma 9>;
514 dma-names = "rx", "tx";
518 uartc: serial@70006200 {
519 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
520 reg = <0x70006200 0x100>;
522 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
524 resets = <&tegra_car 55>;
525 reset-names = "serial";
526 dmas = <&apbdma 10>, <&apbdma 10>;
527 dma-names = "rx", "tx";
531 uartd: serial@70006300 {
532 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
533 reg = <0x70006300 0x100>;
535 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
537 resets = <&tegra_car 65>;
538 reset-names = "serial";
539 dmas = <&apbdma 19>, <&apbdma 19>;
540 dma-names = "rx", "tx";
544 uarte: serial@70006400 {
545 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
546 reg = <0x70006400 0x100>;
548 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
550 resets = <&tegra_car 66>;
551 reset-names = "serial";
552 dmas = <&apbdma 20>, <&apbdma 20>;
553 dma-names = "rx", "tx";
558 compatible = "nvidia,tegra30-gmi";
559 reg = <0x70009000 0x1000>;
560 #address-cells = <2>;
562 ranges = <0 0 0x48000000 0x7ffffff>;
563 clocks = <&tegra_car TEGRA30_CLK_NOR>;
565 resets = <&tegra_car 42>;
571 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
572 reg = <0x7000a000 0x100>;
574 clocks = <&tegra_car TEGRA30_CLK_PWM>;
575 resets = <&tegra_car 17>;
581 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
582 reg = <0x7000e000 0x100>;
583 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&tegra_car TEGRA30_CLK_RTC>;
588 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
589 reg = <0x7000c000 0x100>;
590 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
591 #address-cells = <1>;
593 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
594 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
595 clock-names = "div-clk", "fast-clk";
596 resets = <&tegra_car 12>;
598 dmas = <&apbdma 21>, <&apbdma 21>;
599 dma-names = "rx", "tx";
604 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
605 reg = <0x7000c400 0x100>;
606 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
607 #address-cells = <1>;
609 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
610 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
611 clock-names = "div-clk", "fast-clk";
612 resets = <&tegra_car 54>;
614 dmas = <&apbdma 22>, <&apbdma 22>;
615 dma-names = "rx", "tx";
620 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
621 reg = <0x7000c500 0x100>;
622 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
623 #address-cells = <1>;
625 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
626 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
627 clock-names = "div-clk", "fast-clk";
628 resets = <&tegra_car 67>;
630 dmas = <&apbdma 23>, <&apbdma 23>;
631 dma-names = "rx", "tx";
636 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
637 reg = <0x7000c700 0x100>;
638 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
639 #address-cells = <1>;
641 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
642 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
643 resets = <&tegra_car 103>;
645 clock-names = "div-clk", "fast-clk";
646 dmas = <&apbdma 26>, <&apbdma 26>;
647 dma-names = "rx", "tx";
652 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
653 reg = <0x7000d000 0x100>;
654 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
657 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
658 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
659 clock-names = "div-clk", "fast-clk";
660 resets = <&tegra_car 47>;
662 dmas = <&apbdma 24>, <&apbdma 24>;
663 dma-names = "rx", "tx";
668 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
669 reg = <0x7000d400 0x200>;
670 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
671 #address-cells = <1>;
673 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
674 resets = <&tegra_car 41>;
676 dmas = <&apbdma 15>, <&apbdma 15>;
677 dma-names = "rx", "tx";
682 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
683 reg = <0x7000d600 0x200>;
684 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
687 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
688 resets = <&tegra_car 44>;
690 dmas = <&apbdma 16>, <&apbdma 16>;
691 dma-names = "rx", "tx";
696 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
697 reg = <0x7000d800 0x200>;
698 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
701 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
702 resets = <&tegra_car 46>;
704 dmas = <&apbdma 17>, <&apbdma 17>;
705 dma-names = "rx", "tx";
710 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
711 reg = <0x7000da00 0x200>;
712 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
713 #address-cells = <1>;
715 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
716 resets = <&tegra_car 68>;
718 dmas = <&apbdma 18>, <&apbdma 18>;
719 dma-names = "rx", "tx";
724 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
725 reg = <0x7000dc00 0x200>;
726 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
727 #address-cells = <1>;
729 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
730 resets = <&tegra_car 104>;
732 dmas = <&apbdma 27>, <&apbdma 27>;
733 dma-names = "rx", "tx";
738 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
739 reg = <0x7000de00 0x200>;
740 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
741 #address-cells = <1>;
743 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
744 resets = <&tegra_car 106>;
746 dmas = <&apbdma 28>, <&apbdma 28>;
747 dma-names = "rx", "tx";
752 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
753 reg = <0x7000e200 0x100>;
754 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&tegra_car TEGRA30_CLK_KBC>;
756 resets = <&tegra_car 36>;
761 tegra_pmc: pmc@7000e400 {
762 compatible = "nvidia,tegra30-pmc";
763 reg = <0x7000e400 0x400>;
764 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
765 clock-names = "pclk", "clk32k_in";
769 mc: memory-controller@7000f000 {
770 compatible = "nvidia,tegra30-mc";
771 reg = <0x7000f000 0x400>;
772 clocks = <&tegra_car TEGRA30_CLK_MC>;
775 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
779 #interconnect-cells = <1>;
782 emc: memory-controller@7000f400 {
783 compatible = "nvidia,tegra30-emc";
784 reg = <0x7000f400 0x400>;
785 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&tegra_car TEGRA30_CLK_EMC>;
788 nvidia,memory-controller = <&mc>;
789 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
791 #interconnect-cells = <0>;
795 compatible = "nvidia,tegra30-efuse";
796 reg = <0x7000f800 0x400>;
797 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
798 clock-names = "fuse";
799 resets = <&tegra_car 39>;
800 reset-names = "fuse";
804 compatible = "nvidia,tegra30-hda";
805 reg = <0x70030000 0x10000>;
806 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&tegra_car TEGRA30_CLK_HDA>,
808 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
809 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
810 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
811 resets = <&tegra_car 125>, /* hda */
812 <&tegra_car 128>, /* hda2hdmi */
813 <&tegra_car 111>; /* hda2codec_2x */
814 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
819 compatible = "nvidia,tegra30-ahub";
820 reg = <0x70080000 0x200>,
822 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
824 <&tegra_car TEGRA30_CLK_APBIF>;
825 clock-names = "d_audio", "apbif";
826 resets = <&tegra_car 106>, /* d_audio */
827 <&tegra_car 107>, /* apbif */
828 <&tegra_car 30>, /* i2s0 */
829 <&tegra_car 11>, /* i2s1 */
830 <&tegra_car 18>, /* i2s2 */
831 <&tegra_car 101>, /* i2s3 */
832 <&tegra_car 102>, /* i2s4 */
833 <&tegra_car 108>, /* dam0 */
834 <&tegra_car 109>, /* dam1 */
835 <&tegra_car 110>, /* dam2 */
836 <&tegra_car 10>; /* spdif */
837 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
838 "i2s3", "i2s4", "dam0", "dam1", "dam2",
840 dmas = <&apbdma 1>, <&apbdma 1>,
841 <&apbdma 2>, <&apbdma 2>,
842 <&apbdma 3>, <&apbdma 3>,
843 <&apbdma 4>, <&apbdma 4>;
844 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
847 #address-cells = <1>;
850 tegra_i2s0: i2s@70080300 {
851 compatible = "nvidia,tegra30-i2s";
852 reg = <0x70080300 0x100>;
853 nvidia,ahub-cif-ids = <4 4>;
854 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
855 resets = <&tegra_car 30>;
860 tegra_i2s1: i2s@70080400 {
861 compatible = "nvidia,tegra30-i2s";
862 reg = <0x70080400 0x100>;
863 nvidia,ahub-cif-ids = <5 5>;
864 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
865 resets = <&tegra_car 11>;
870 tegra_i2s2: i2s@70080500 {
871 compatible = "nvidia,tegra30-i2s";
872 reg = <0x70080500 0x100>;
873 nvidia,ahub-cif-ids = <6 6>;
874 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
875 resets = <&tegra_car 18>;
880 tegra_i2s3: i2s@70080600 {
881 compatible = "nvidia,tegra30-i2s";
882 reg = <0x70080600 0x100>;
883 nvidia,ahub-cif-ids = <7 7>;
884 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
885 resets = <&tegra_car 101>;
890 tegra_i2s4: i2s@70080700 {
891 compatible = "nvidia,tegra30-i2s";
892 reg = <0x70080700 0x100>;
893 nvidia,ahub-cif-ids = <8 8>;
894 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
895 resets = <&tegra_car 102>;
902 compatible = "nvidia,tegra30-sdhci";
903 reg = <0x78000000 0x200>;
904 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
906 clock-names = "sdhci";
907 resets = <&tegra_car 14>;
908 reset-names = "sdhci";
913 compatible = "nvidia,tegra30-sdhci";
914 reg = <0x78000200 0x200>;
915 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
917 clock-names = "sdhci";
918 resets = <&tegra_car 9>;
919 reset-names = "sdhci";
924 compatible = "nvidia,tegra30-sdhci";
925 reg = <0x78000400 0x200>;
926 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
928 clock-names = "sdhci";
929 resets = <&tegra_car 69>;
930 reset-names = "sdhci";
935 compatible = "nvidia,tegra30-sdhci";
936 reg = <0x78000600 0x200>;
937 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
939 clock-names = "sdhci";
940 resets = <&tegra_car 15>;
941 reset-names = "sdhci";
946 compatible = "nvidia,tegra30-ehci", "usb-ehci";
947 reg = <0x7d000000 0x4000>;
948 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&tegra_car TEGRA30_CLK_USBD>;
951 resets = <&tegra_car 22>;
953 nvidia,needs-double-reset;
954 nvidia,phy = <&phy1>;
958 phy1: usb-phy@7d000000 {
959 compatible = "nvidia,tegra30-usb-phy";
960 reg = <0x7d000000 0x4000>,
963 clocks = <&tegra_car TEGRA30_CLK_USBD>,
964 <&tegra_car TEGRA30_CLK_PLL_U>,
965 <&tegra_car TEGRA30_CLK_USBD>;
966 clock-names = "reg", "pll_u", "utmi-pads";
967 resets = <&tegra_car 22>, <&tegra_car 22>;
968 reset-names = "usb", "utmi-pads";
970 nvidia,hssync-start-delay = <9>;
971 nvidia,idle-wait-delay = <17>;
972 nvidia,elastic-limit = <16>;
973 nvidia,term-range-adj = <6>;
974 nvidia,xcvr-setup = <51>;
975 nvidia,xcvr-setup-use-fuses;
976 nvidia,xcvr-lsfslew = <1>;
977 nvidia,xcvr-lsrslew = <1>;
978 nvidia,xcvr-hsslew = <32>;
979 nvidia,hssquelch-level = <2>;
980 nvidia,hsdiscon-level = <5>;
981 nvidia,has-utmi-pad-registers;
986 compatible = "nvidia,tegra30-ehci", "usb-ehci";
987 reg = <0x7d004000 0x4000>;
988 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&tegra_car TEGRA30_CLK_USB2>;
991 resets = <&tegra_car 58>;
993 nvidia,phy = <&phy2>;
997 phy2: usb-phy@7d004000 {
998 compatible = "nvidia,tegra30-usb-phy";
999 reg = <0x7d004000 0x4000>,
1000 <0x7d000000 0x4000>;
1002 clocks = <&tegra_car TEGRA30_CLK_USB2>,
1003 <&tegra_car TEGRA30_CLK_PLL_U>,
1004 <&tegra_car TEGRA30_CLK_USBD>;
1005 clock-names = "reg", "pll_u", "utmi-pads";
1006 resets = <&tegra_car 58>, <&tegra_car 22>;
1007 reset-names = "usb", "utmi-pads";
1009 nvidia,hssync-start-delay = <9>;
1010 nvidia,idle-wait-delay = <17>;
1011 nvidia,elastic-limit = <16>;
1012 nvidia,term-range-adj = <6>;
1013 nvidia,xcvr-setup = <51>;
1014 nvidia,xcvr-setup-use-fuses;
1015 nvidia,xcvr-lsfslew = <2>;
1016 nvidia,xcvr-lsrslew = <2>;
1017 nvidia,xcvr-hsslew = <32>;
1018 nvidia,hssquelch-level = <2>;
1019 nvidia,hsdiscon-level = <5>;
1020 status = "disabled";
1024 compatible = "nvidia,tegra30-ehci", "usb-ehci";
1025 reg = <0x7d008000 0x4000>;
1026 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&tegra_car TEGRA30_CLK_USB3>;
1029 resets = <&tegra_car 59>;
1030 reset-names = "usb";
1031 nvidia,phy = <&phy3>;
1032 status = "disabled";
1035 phy3: usb-phy@7d008000 {
1036 compatible = "nvidia,tegra30-usb-phy";
1037 reg = <0x7d008000 0x4000>,
1038 <0x7d000000 0x4000>;
1040 clocks = <&tegra_car TEGRA30_CLK_USB3>,
1041 <&tegra_car TEGRA30_CLK_PLL_U>,
1042 <&tegra_car TEGRA30_CLK_USBD>;
1043 clock-names = "reg", "pll_u", "utmi-pads";
1044 resets = <&tegra_car 59>, <&tegra_car 22>;
1045 reset-names = "usb", "utmi-pads";
1047 nvidia,hssync-start-delay = <0>;
1048 nvidia,idle-wait-delay = <17>;
1049 nvidia,elastic-limit = <16>;
1050 nvidia,term-range-adj = <6>;
1051 nvidia,xcvr-setup = <51>;
1052 nvidia,xcvr-setup-use-fuses;
1053 nvidia,xcvr-lsfslew = <2>;
1054 nvidia,xcvr-lsrslew = <2>;
1055 nvidia,xcvr-hsslew = <32>;
1056 nvidia,hssquelch-level = <2>;
1057 nvidia,hsdiscon-level = <5>;
1058 status = "disabled";
1062 #address-cells = <1>;
1066 device_type = "cpu";
1067 compatible = "arm,cortex-a9";
1069 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1073 device_type = "cpu";
1074 compatible = "arm,cortex-a9";
1076 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1080 device_type = "cpu";
1081 compatible = "arm,cortex-a9";
1083 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1087 device_type = "cpu";
1088 compatible = "arm,cortex-a9";
1090 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1095 compatible = "arm,cortex-a9-pmu";
1096 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1100 interrupt-affinity = <&{/cpus/cpu@0}>,