arch/arm/boot/dts/tegra30.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra30-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra30-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8
   9 / {
  10         compatible = "nvidia,tegra30";
  11         interrupt-parent = <&lic>;
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x80000000 0x0>;
  18         };
  19
  20         pcie@3000 {
  21                 compatible = "nvidia,tegra30-pcie";
  22                 device_type = "pci";
  23                 reg = <0x00003000 0x00000800   /* PADS registers */
  24                        0x00003800 0x00000200   /* AFI registers */
  25                        0x10000000 0x10000000>; /* configuration space */
  26                 reg-names = "pads", "afi", "cs";
  27                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  28                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  29                 interrupt-names = "intr", "msi";
  30
  31                 #interrupt-cells = <1>;
  32                 interrupt-map-mask = <0 0 0 0>;
  33                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  34
  35                 bus-range = <0x00 0xff>;
  36                 #address-cells = <3>;
  37                 #size-cells = <2>;
  38
  39                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  40                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  41                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  42                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  43                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  44                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  45
  46                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  47                          <&tegra_car TEGRA30_CLK_AFI>,
  48                          <&tegra_car TEGRA30_CLK_PLL_E>,
  49                          <&tegra_car TEGRA30_CLK_CML0>;
  50                 clock-names = "pex", "afi", "pll_e", "cml";
  51                 resets = <&tegra_car 70>,
  52                          <&tegra_car 72>,
  53                          <&tegra_car 74>;
  54                 reset-names = "pex", "afi", "pcie_x";
  55                 status = "disabled";
  56
  57                 pci@1,0 {
  58                         device_type = "pci";
  59                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  60                         reg = <0x000800 0 0 0 0>;
  61                         bus-range = <0x00 0xff>;
  62                         status = "disabled";
  63
  64                         #address-cells = <3>;
  65                         #size-cells = <2>;
  66                         ranges;
  67
  68                         nvidia,num-lanes = <2>;
  69                 };
  70
  71                 pci@2,0 {
  72                         device_type = "pci";
  73                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  74                         reg = <0x001000 0 0 0 0>;
  75                         bus-range = <0x00 0xff>;
  76                         status = "disabled";
  77
  78                         #address-cells = <3>;
  79                         #size-cells = <2>;
  80                         ranges;
  81
  82                         nvidia,num-lanes = <2>;
  83                 };
  84
  85                 pci@3,0 {
  86                         device_type = "pci";
  87                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  88                         reg = <0x001800 0 0 0 0>;
  89                         bus-range = <0x00 0xff>;
  90                         status = "disabled";
  91
  92                         #address-cells = <3>;
  93                         #size-cells = <2>;
  94                         ranges;
  95
  96                         nvidia,num-lanes = <2>;
  97                 };
  98         };
  99
 100         iram@40000000 {
 101                 compatible = "mmio-sram";
 102                 reg = <0x40000000 0x40000>;
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105                 ranges = <0 0x40000000 0x40000>;
 106
 107                 vde_pool: vde@400 {
 108                         reg = <0x400 0x3fc00>;
 109                         pool;
 110                 };
 111         };
 112
 113         host1x@50000000 {
 114                 compatible = "nvidia,tegra30-host1x", "simple-bus";
 115                 reg = <0x50000000 0x00024000>;
 116                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 117                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 118                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 119                 resets = <&tegra_car 28>;
 120                 reset-names = "host1x";
 121                 iommus = <&mc TEGRA_SWGROUP_HC>;
 122
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125
 126                 ranges = <0x54000000 0x54000000 0x04000000>;
 127
 128                 mpe@54040000 {
 129                         compatible = "nvidia,tegra30-mpe";
 130                         reg = <0x54040000 0x00040000>;
 131                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 133                         resets = <&tegra_car 60>;
 134                         reset-names = "mpe";
 135
 136                         iommus = <&mc TEGRA_SWGROUP_MPE>;
 137                 };
 138
 139                 vi@54080000 {
 140                         compatible = "nvidia,tegra30-vi";
 141                         reg = <0x54080000 0x00040000>;
 142                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 144                         resets = <&tegra_car 20>;
 145                         reset-names = "vi";
 146
 147                         iommus = <&mc TEGRA_SWGROUP_VI>;
 148                 };
 149
 150                 epp@540c0000 {
 151                         compatible = "nvidia,tegra30-epp";
 152                         reg = <0x540c0000 0x00040000>;
 153                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 154                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 155                         resets = <&tegra_car 19>;
 156                         reset-names = "epp";
 157
 158                         iommus = <&mc TEGRA_SWGROUP_EPP>;
 159                 };
 160
 161                 isp@54100000 {
 162                         compatible = "nvidia,tegra30-isp";
 163                         reg = <0x54100000 0x00040000>;
 164                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 165                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 166                         resets = <&tegra_car 23>;
 167                         reset-names = "isp";
 168
 169                         iommus = <&mc TEGRA_SWGROUP_ISP>;
 170                 };
 171
 172                 gr2d@54140000 {
 173                         compatible = "nvidia,tegra30-gr2d";
 174                         reg = <0x54140000 0x00040000>;
 175                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 176                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 177                         resets = <&tegra_car 21>;
 178                         reset-names = "2d";
 179
 180                         iommus = <&mc TEGRA_SWGROUP_G2>;
 181                 };
 182
 183                 gr3d@54180000 {
 184                         compatible = "nvidia,tegra30-gr3d";
 185                         reg = <0x54180000 0x00040000>;
 186                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 187                                   &tegra_car TEGRA30_CLK_GR3D2>;
 188                         clock-names = "3d", "3d2";
 189                         resets = <&tegra_car 24>,
 190                                  <&tegra_car 98>;
 191                         reset-names = "3d", "3d2";
 192
 193                         iommus = <&mc TEGRA_SWGROUP_NV>,
 194                                  <&mc TEGRA_SWGROUP_NV2>;
 195                 };
 196
 197                 dc@54200000 {
 198                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 199                         reg = <0x54200000 0x00040000>;
 200                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 202                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 203                         clock-names = "dc", "parent";
 204                         resets = <&tegra_car 27>;
 205                         reset-names = "dc";
 206
 207                         iommus = <&mc TEGRA_SWGROUP_DC>;
 208
 209                         nvidia,head = <0>;
 210
 211                         rgb {
 212                                 status = "disabled";
 213                         };
 214                 };
 215
 216                 dc@54240000 {
 217                         compatible = "nvidia,tegra30-dc";
 218                         reg = <0x54240000 0x00040000>;
 219                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 221                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 222                         clock-names = "dc", "parent";
 223                         resets = <&tegra_car 26>;
 224                         reset-names = "dc";
 225
 226                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 227
 228                         nvidia,head = <1>;
 229
 230                         rgb {
 231                                 status = "disabled";
 232                         };
 233                 };
 234
 235                 hdmi@54280000 {
 236                         compatible = "nvidia,tegra30-hdmi";
 237                         reg = <0x54280000 0x00040000>;
 238                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 239                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 240                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 241                         clock-names = "hdmi", "parent";
 242                         resets = <&tegra_car 51>;
 243                         reset-names = "hdmi";
 244                         status = "disabled";
 245                 };
 246
 247                 tvo@542c0000 {
 248                         compatible = "nvidia,tegra30-tvo";
 249                         reg = <0x542c0000 0x00040000>;
 250                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 251                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 252                         status = "disabled";
 253                 };
 254
 255                 dsi@54300000 {
 256                         compatible = "nvidia,tegra30-dsi";
 257                         reg = <0x54300000 0x00040000>;
 258                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 259                         resets = <&tegra_car 48>;
 260                         reset-names = "dsi";
 261                         status = "disabled";
 262                 };
 263         };
 264
 265         timer@50040600 {
 266                 compatible = "arm,cortex-a9-twd-timer";
 267                 reg = <0x50040600 0x20>;
 268                 interrupt-parent = <&intc>;
 269                 interrupts = <GIC_PPI 13
 270                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 271                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 272         };
 273
 274         intc: interrupt-controller@50041000 {
 275                 compatible = "arm,cortex-a9-gic";
 276                 reg = <0x50041000 0x1000
 277                        0x50040100 0x0100>;
 278                 interrupt-controller;
 279                 #interrupt-cells = <3>;
 280                 interrupt-parent = <&intc>;
 281         };
 282
 283         cache-controller@50043000 {
 284                 compatible = "arm,pl310-cache";
 285                 reg = <0x50043000 0x1000>;
 286                 arm,data-latency = <6 6 2>;
 287                 arm,tag-latency = <5 5 2>;
 288                 cache-unified;
 289                 cache-level = <2>;
 290         };
 291
 292         lic: interrupt-controller@60004000 {
 293                 compatible = "nvidia,tegra30-ictlr";
 294                 reg = <0x60004000 0x100>,
 295                       <0x60004100 0x50>,
 296                       <0x60004200 0x50>,
 297                       <0x60004300 0x50>,
 298                       <0x60004400 0x50>;
 299                 interrupt-controller;
 300                 #interrupt-cells = <3>;
 301                 interrupt-parent = <&intc>;
 302         };
 303
 304         timer@60005000 {
 305                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 306                 reg = <0x60005000 0x400>;
 307                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 314         };
 315
 316         tegra_car: clock@60006000 {
 317                 compatible = "nvidia,tegra30-car";
 318                 reg = <0x60006000 0x1000>;
 319                 #clock-cells = <1>;
 320                 #reset-cells = <1>;
 321         };
 322
 323         flow-controller@60007000 {
 324                 compatible = "nvidia,tegra30-flowctrl";
 325                 reg = <0x60007000 0x1000>;
 326         };
 327
 328         apbdma: dma@6000a000 {
 329                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 330                 reg = <0x6000a000 0x1400>;
 331                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 336                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 337                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 338                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 339                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 340                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 342                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 343                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 344                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 345                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 347                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 350                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 351                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 352                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 353                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 354                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 355                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 356                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 357                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 358                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 359                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 360                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 361                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 362                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 364                 resets = <&tegra_car 34>;
 365                 reset-names = "dma";
 366                 #dma-cells = <1>;
 367         };
 368
 369         ahb: ahb@6000c000 {
 370                 compatible = "nvidia,tegra30-ahb";
 371                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 372         };
 373
 374         actmon@6000c800 {
 375                 compatible = "nvidia,tegra30-actmon";
 376                 reg = <0x6000c800 0x400>;
 377                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 378                 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
 379                          <&tegra_car TEGRA30_CLK_EMC>;
 380                 clock-names = "actmon", "emc";
 381                 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
 382                 reset-names = "actmon";
 383         };
 384
 385         gpio: gpio@6000d000 {
 386                 compatible = "nvidia,tegra30-gpio";
 387                 reg = <0x6000d000 0x1000>;
 388                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 389                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 393                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 394                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 395                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 396                 #gpio-cells = <2>;
 397                 gpio-controller;
 398                 #interrupt-cells = <2>;
 399                 interrupt-controller;
 400                 /*
 401                 gpio-ranges = <&pinmux 0 0 248>;
 402                 */
 403         };
 404
 405         vde@6001a000 {
 406                 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
 407                 reg = <0x6001a000 0x1000   /* Syntax Engine */
 408                        0x6001b000 0x1000   /* Video Bitstream Engine */
 409                        0x6001c000  0x100   /* Macroblock Engine */
 410                        0x6001c200  0x100   /* Post-processing Engine */
 411                        0x6001c400  0x100   /* Motion Compensation Engine */
 412                        0x6001c600  0x100   /* Transform Engine */
 413                        0x6001c800  0x100   /* Pixel prediction block */
 414                        0x6001ca00  0x100   /* Video DMA */
 415                        0x6001d800  0x400>; /* Video frame controls */
 416                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 417                             "tfe", "ppb", "vdma", "frameid";
 418                 iram = <&vde_pool>; /* IRAM region */
 419                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 420                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 421                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 422                 interrupt-names = "sync-token", "bsev", "sxe";
 423                 clocks = <&tegra_car TEGRA30_CLK_VDE>;
 424                 reset-names = "vde", "mc";
 425                 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
 426                 iommus = <&mc TEGRA_SWGROUP_VDE>;
 427         };
 428
 429         apbmisc@70000800 {
 430                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 431                 reg = <0x70000800 0x64   /* Chip revision */
 432                        0x70000008 0x04>; /* Strapping options */
 433         };
 434
 435         pinmux: pinmux@70000868 {
 436                 compatible = "nvidia,tegra30-pinmux";
 437                 reg = <0x70000868 0xd4    /* Pad control registers */
 438                        0x70003000 0x3e4>; /* Mux registers */
 439         };
 440
 441         /*
 442          * There are two serial driver i.e. 8250 based simple serial
 443          * driver and APB DMA based serial driver for higher baudrate
 444          * and performace. To enable the 8250 based driver, the compatible
 445          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 446          * the APB DMA based serial driver, the compatible is
 447          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 448          */
 449         uarta: serial@70006000 {
 450                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 451                 reg = <0x70006000 0x40>;
 452                 reg-shift = <2>;
 453                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 455                 resets = <&tegra_car 6>;
 456                 reset-names = "serial";
 457                 dmas = <&apbdma 8>, <&apbdma 8>;
 458                 dma-names = "rx", "tx";
 459                 status = "disabled";
 460         };
 461
 462         uartb: serial@70006040 {
 463                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 464                 reg = <0x70006040 0x40>;
 465                 reg-shift = <2>;
 466                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 468                 resets = <&tegra_car 7>;
 469                 reset-names = "serial";
 470                 dmas = <&apbdma 9>, <&apbdma 9>;
 471                 dma-names = "rx", "tx";
 472                 status = "disabled";
 473         };
 474
 475         uartc: serial@70006200 {
 476                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 477                 reg = <0x70006200 0x100>;
 478                 reg-shift = <2>;
 479                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 480                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 481                 resets = <&tegra_car 55>;
 482                 reset-names = "serial";
 483                 dmas = <&apbdma 10>, <&apbdma 10>;
 484                 dma-names = "rx", "tx";
 485                 status = "disabled";
 486         };
 487
 488         uartd: serial@70006300 {
 489                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 490                 reg = <0x70006300 0x100>;
 491                 reg-shift = <2>;
 492                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 493                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 494                 resets = <&tegra_car 65>;
 495                 reset-names = "serial";
 496                 dmas = <&apbdma 19>, <&apbdma 19>;
 497                 dma-names = "rx", "tx";
 498                 status = "disabled";
 499         };
 500
 501         uarte: serial@70006400 {
 502                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 503                 reg = <0x70006400 0x100>;
 504                 reg-shift = <2>;
 505                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 506                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 507                 resets = <&tegra_car 66>;
 508                 reset-names = "serial";
 509                 dmas = <&apbdma 20>, <&apbdma 20>;
 510                 dma-names = "rx", "tx";
 511                 status = "disabled";
 512         };
 513
 514         gmi@70009000 {
 515                 compatible = "nvidia,tegra30-gmi";
 516                 reg = <0x70009000 0x1000>;
 517                 #address-cells = <2>;
 518                 #size-cells = <1>;
 519                 ranges = <0 0 0x48000000 0x7ffffff>;
 520                 clocks = <&tegra_car TEGRA30_CLK_NOR>;
 521                 clock-names = "gmi";
 522                 resets = <&tegra_car 42>;
 523                 reset-names = "gmi";
 524                 status = "disabled";
 525         };
 526
 527         pwm: pwm@7000a000 {
 528                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 529                 reg = <0x7000a000 0x100>;
 530                 #pwm-cells = <2>;
 531                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 532                 resets = <&tegra_car 17>;
 533                 reset-names = "pwm";
 534                 status = "disabled";
 535         };
 536
 537         rtc@7000e000 {
 538                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 539                 reg = <0x7000e000 0x100>;
 540                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 542         };
 543
 544         i2c@7000c000 {
 545                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 546                 reg = <0x7000c000 0x100>;
 547                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 551                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 552                 clock-names = "div-clk", "fast-clk";
 553                 resets = <&tegra_car 12>;
 554                 reset-names = "i2c";
 555                 dmas = <&apbdma 21>, <&apbdma 21>;
 556                 dma-names = "rx", "tx";
 557                 status = "disabled";
 558         };
 559
 560         i2c@7000c400 {
 561                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 562                 reg = <0x7000c400 0x100>;
 563                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 567                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 568                 clock-names = "div-clk", "fast-clk";
 569                 resets = <&tegra_car 54>;
 570                 reset-names = "i2c";
 571                 dmas = <&apbdma 22>, <&apbdma 22>;
 572                 dma-names = "rx", "tx";
 573                 status = "disabled";
 574         };
 575
 576         i2c@7000c500 {
 577                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 578                 reg = <0x7000c500 0x100>;
 579                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 583                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 584                 clock-names = "div-clk", "fast-clk";
 585                 resets = <&tegra_car 67>;
 586                 reset-names = "i2c";
 587                 dmas = <&apbdma 23>, <&apbdma 23>;
 588                 dma-names = "rx", "tx";
 589                 status = "disabled";
 590         };
 591
 592         i2c@7000c700 {
 593                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 594                 reg = <0x7000c700 0x100>;
 595                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 599                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 600                 resets = <&tegra_car 103>;
 601                 reset-names = "i2c";
 602                 clock-names = "div-clk", "fast-clk";
 603                 dmas = <&apbdma 26>, <&apbdma 26>;
 604                 dma-names = "rx", "tx";
 605                 status = "disabled";
 606         };
 607
 608         i2c@7000d000 {
 609                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 610                 reg = <0x7000d000 0x100>;
 611                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 612                 #address-cells = <1>;
 613                 #size-cells = <0>;
 614                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 615                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 616                 clock-names = "div-clk", "fast-clk";
 617                 resets = <&tegra_car 47>;
 618                 reset-names = "i2c";
 619                 dmas = <&apbdma 24>, <&apbdma 24>;
 620                 dma-names = "rx", "tx";
 621                 status = "disabled";
 622         };
 623
 624         spi@7000d400 {
 625                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 626                 reg = <0x7000d400 0x200>;
 627                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 631                 resets = <&tegra_car 41>;
 632                 reset-names = "spi";
 633                 dmas = <&apbdma 15>, <&apbdma 15>;
 634                 dma-names = "rx", "tx";
 635                 status = "disabled";
 636         };
 637
 638         spi@7000d600 {
 639                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 640                 reg = <0x7000d600 0x200>;
 641                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 645                 resets = <&tegra_car 44>;
 646                 reset-names = "spi";
 647                 dmas = <&apbdma 16>, <&apbdma 16>;
 648                 dma-names = "rx", "tx";
 649                 status = "disabled";
 650         };
 651
 652         spi@7000d800 {
 653                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 654                 reg = <0x7000d800 0x200>;
 655                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 659                 resets = <&tegra_car 46>;
 660                 reset-names = "spi";
 661                 dmas = <&apbdma 17>, <&apbdma 17>;
 662                 dma-names = "rx", "tx";
 663                 status = "disabled";
 664         };
 665
 666         spi@7000da00 {
 667                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 668                 reg = <0x7000da00 0x200>;
 669                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 673                 resets = <&tegra_car 68>;
 674                 reset-names = "spi";
 675                 dmas = <&apbdma 18>, <&apbdma 18>;
 676                 dma-names = "rx", "tx";
 677                 status = "disabled";
 678         };
 679
 680         spi@7000dc00 {
 681                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 682                 reg = <0x7000dc00 0x200>;
 683                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 684                 #address-cells = <1>;
 685                 #size-cells = <0>;
 686                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 687                 resets = <&tegra_car 104>;
 688                 reset-names = "spi";
 689                 dmas = <&apbdma 27>, <&apbdma 27>;
 690                 dma-names = "rx", "tx";
 691                 status = "disabled";
 692         };
 693
 694         spi@7000de00 {
 695                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 696                 reg = <0x7000de00 0x200>;
 697                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 698                 #address-cells = <1>;
 699                 #size-cells = <0>;
 700                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 701                 resets = <&tegra_car 106>;
 702                 reset-names = "spi";
 703                 dmas = <&apbdma 28>, <&apbdma 28>;
 704                 dma-names = "rx", "tx";
 705                 status = "disabled";
 706         };
 707
 708         kbc@7000e200 {
 709                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 710                 reg = <0x7000e200 0x100>;
 711                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 713                 resets = <&tegra_car 36>;
 714                 reset-names = "kbc";
 715                 status = "disabled";
 716         };
 717
 718         tegra_pmc: pmc@7000e400 {
 719                 compatible = "nvidia,tegra30-pmc";
 720                 reg = <0x7000e400 0x400>;
 721                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 722                 clock-names = "pclk", "clk32k_in";
 723                 #clock-cells = <1>;
 724         };
 725
 726         mc: memory-controller@7000f000 {
 727                 compatible = "nvidia,tegra30-mc";
 728                 reg = <0x7000f000 0x400>;
 729                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 730                 clock-names = "mc";
 731
 732                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 733
 734                 #iommu-cells = <1>;
 735                 #reset-cells = <1>;
 736         };
 737
 738         memory-controller@7000f400 {
 739                 compatible = "nvidia,tegra30-emc";
 740                 reg = <0x7000f400 0x400>;
 741                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&tegra_car TEGRA30_CLK_EMC>;
 743
 744                 nvidia,memory-controller = <&mc>;
 745         };
 746
 747         fuse@7000f800 {
 748                 compatible = "nvidia,tegra30-efuse";
 749                 reg = <0x7000f800 0x400>;
 750                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 751                 clock-names = "fuse";
 752                 resets = <&tegra_car 39>;
 753                 reset-names = "fuse";
 754         };
 755
 756         hda@70030000 {
 757                 compatible = "nvidia,tegra30-hda";
 758                 reg = <0x70030000 0x10000>;
 759                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 760                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 761                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 762                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 763                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 764                 resets = <&tegra_car 125>, /* hda */
 765                          <&tegra_car 128>, /* hda2hdmi */
 766                          <&tegra_car 111>; /* hda2codec_2x */
 767                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 768                 status = "disabled";
 769         };
 770
 771         ahub@70080000 {
 772                 compatible = "nvidia,tegra30-ahub";
 773                 reg = <0x70080000 0x200
 774                        0x70080200 0x100>;
 775                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 776                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 777                          <&tegra_car TEGRA30_CLK_APBIF>;
 778                 clock-names = "d_audio", "apbif";
 779                 resets = <&tegra_car 106>, /* d_audio */
 780                          <&tegra_car 107>, /* apbif */
 781                          <&tegra_car 30>,  /* i2s0 */
 782                          <&tegra_car 11>,  /* i2s1 */
 783                          <&tegra_car 18>,  /* i2s2 */
 784                          <&tegra_car 101>, /* i2s3 */
 785                          <&tegra_car 102>, /* i2s4 */
 786                          <&tegra_car 108>, /* dam0 */
 787                          <&tegra_car 109>, /* dam1 */
 788                          <&tegra_car 110>, /* dam2 */
 789                          <&tegra_car 10>;  /* spdif */
 790                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 791                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 792                               "spdif";
 793                 dmas = <&apbdma 1>, <&apbdma 1>,
 794                        <&apbdma 2>, <&apbdma 2>,
 795                        <&apbdma 3>, <&apbdma 3>,
 796                        <&apbdma 4>, <&apbdma 4>;
 797                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 798                             "rx3", "tx3";
 799                 ranges;
 800                 #address-cells = <1>;
 801                 #size-cells = <1>;
 802
 803                 tegra_i2s0: i2s@70080300 {
 804                         compatible = "nvidia,tegra30-i2s";
 805                         reg = <0x70080300 0x100>;
 806                         nvidia,ahub-cif-ids = <4 4>;
 807                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 808                         resets = <&tegra_car 30>;
 809                         reset-names = "i2s";
 810                         status = "disabled";
 811                 };
 812
 813                 tegra_i2s1: i2s@70080400 {
 814                         compatible = "nvidia,tegra30-i2s";
 815                         reg = <0x70080400 0x100>;
 816                         nvidia,ahub-cif-ids = <5 5>;
 817                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 818                         resets = <&tegra_car 11>;
 819                         reset-names = "i2s";
 820                         status = "disabled";
 821                 };
 822
 823                 tegra_i2s2: i2s@70080500 {
 824                         compatible = "nvidia,tegra30-i2s";
 825                         reg = <0x70080500 0x100>;
 826                         nvidia,ahub-cif-ids = <6 6>;
 827                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 828                         resets = <&tegra_car 18>;
 829                         reset-names = "i2s";
 830                         status = "disabled";
 831                 };
 832
 833                 tegra_i2s3: i2s@70080600 {
 834                         compatible = "nvidia,tegra30-i2s";
 835                         reg = <0x70080600 0x100>;
 836                         nvidia,ahub-cif-ids = <7 7>;
 837                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 838                         resets = <&tegra_car 101>;
 839                         reset-names = "i2s";
 840                         status = "disabled";
 841                 };
 842
 843                 tegra_i2s4: i2s@70080700 {
 844                         compatible = "nvidia,tegra30-i2s";
 845                         reg = <0x70080700 0x100>;
 846                         nvidia,ahub-cif-ids = <8 8>;
 847                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 848                         resets = <&tegra_car 102>;
 849                         reset-names = "i2s";
 850                         status = "disabled";
 851                 };
 852         };
 853
 854         sdhci@78000000 {
 855                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 856                 reg = <0x78000000 0x200>;
 857                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 859                 resets = <&tegra_car 14>;
 860                 reset-names = "sdhci";
 861                 status = "disabled";
 862         };
 863
 864         sdhci@78000200 {
 865                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 866                 reg = <0x78000200 0x200>;
 867                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 868                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 869                 resets = <&tegra_car 9>;
 870                 reset-names = "sdhci";
 871                 status = "disabled";
 872         };
 873
 874         sdhci@78000400 {
 875                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 876                 reg = <0x78000400 0x200>;
 877                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 878                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 879                 resets = <&tegra_car 69>;
 880                 reset-names = "sdhci";
 881                 status = "disabled";
 882         };
 883
 884         sdhci@78000600 {
 885                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 886                 reg = <0x78000600 0x200>;
 887                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 888                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 889                 resets = <&tegra_car 15>;
 890                 reset-names = "sdhci";
 891                 status = "disabled";
 892         };
 893
 894         usb@7d000000 {
 895                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 896                 reg = <0x7d000000 0x4000>;
 897                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 898                 phy_type = "utmi";
 899                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 900                 resets = <&tegra_car 22>;
 901                 reset-names = "usb";
 902                 nvidia,needs-double-reset;
 903                 nvidia,phy = <&phy1>;
 904                 status = "disabled";
 905         };
 906
 907         phy1: usb-phy@7d000000 {
 908                 compatible = "nvidia,tegra30-usb-phy";
 909                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 910                 phy_type = "utmi";
 911                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 912                          <&tegra_car TEGRA30_CLK_PLL_U>,
 913                          <&tegra_car TEGRA30_CLK_USBD>;
 914                 clock-names = "reg", "pll_u", "utmi-pads";
 915                 resets = <&tegra_car 22>, <&tegra_car 22>;
 916                 reset-names = "usb", "utmi-pads";
 917                 nvidia,hssync-start-delay = <9>;
 918                 nvidia,idle-wait-delay = <17>;
 919                 nvidia,elastic-limit = <16>;
 920                 nvidia,term-range-adj = <6>;
 921                 nvidia,xcvr-setup = <51>;
 922                 nvidia,xcvr-setup-use-fuses;
 923                 nvidia,xcvr-lsfslew = <1>;
 924                 nvidia,xcvr-lsrslew = <1>;
 925                 nvidia,xcvr-hsslew = <32>;
 926                 nvidia,hssquelch-level = <2>;
 927                 nvidia,hsdiscon-level = <5>;
 928                 nvidia,has-utmi-pad-registers;
 929                 status = "disabled";
 930         };
 931
 932         usb@7d004000 {
 933                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 934                 reg = <0x7d004000 0x4000>;
 935                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 936                 phy_type = "utmi";
 937                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 938                 resets = <&tegra_car 58>;
 939                 reset-names = "usb";
 940                 nvidia,phy = <&phy2>;
 941                 status = "disabled";
 942         };
 943
 944         phy2: usb-phy@7d004000 {
 945                 compatible = "nvidia,tegra30-usb-phy";
 946                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 947                 phy_type = "utmi";
 948                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 949                          <&tegra_car TEGRA30_CLK_PLL_U>,
 950                          <&tegra_car TEGRA30_CLK_USBD>;
 951                 clock-names = "reg", "pll_u", "utmi-pads";
 952                 resets = <&tegra_car 58>, <&tegra_car 22>;
 953                 reset-names = "usb", "utmi-pads";
 954                 nvidia,hssync-start-delay = <9>;
 955                 nvidia,idle-wait-delay = <17>;
 956                 nvidia,elastic-limit = <16>;
 957                 nvidia,term-range-adj = <6>;
 958                 nvidia,xcvr-setup = <51>;
 959                 nvidia,xcvr-setup-use-fuses;
 960                 nvidia,xcvr-lsfslew = <2>;
 961                 nvidia,xcvr-lsrslew = <2>;
 962                 nvidia,xcvr-hsslew = <32>;
 963                 nvidia,hssquelch-level = <2>;
 964                 nvidia,hsdiscon-level = <5>;
 965                 status = "disabled";
 966         };
 967
 968         usb@7d008000 {
 969                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 970                 reg = <0x7d008000 0x4000>;
 971                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 972                 phy_type = "utmi";
 973                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 974                 resets = <&tegra_car 59>;
 975                 reset-names = "usb";
 976                 nvidia,phy = <&phy3>;
 977                 status = "disabled";
 978         };
 979
 980         phy3: usb-phy@7d008000 {
 981                 compatible = "nvidia,tegra30-usb-phy";
 982                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 983                 phy_type = "utmi";
 984                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 985                          <&tegra_car TEGRA30_CLK_PLL_U>,
 986                          <&tegra_car TEGRA30_CLK_USBD>;
 987                 clock-names = "reg", "pll_u", "utmi-pads";
 988                 resets = <&tegra_car 59>, <&tegra_car 22>;
 989                 reset-names = "usb", "utmi-pads";
 990                 nvidia,hssync-start-delay = <0>;
 991                 nvidia,idle-wait-delay = <17>;
 992                 nvidia,elastic-limit = <16>;
 993                 nvidia,term-range-adj = <6>;
 994                 nvidia,xcvr-setup = <51>;
 995                 nvidia,xcvr-setup-use-fuses;
 996                 nvidia,xcvr-lsfslew = <2>;
 997                 nvidia,xcvr-lsrslew = <2>;
 998                 nvidia,xcvr-hsslew = <32>;
 999                 nvidia,hssquelch-level = <2>;
1000                 nvidia,hsdiscon-level = <5>;
1001                 status = "disabled";
1002         };
1003
1004         cpus {
1005                 #address-cells = <1>;
1006                 #size-cells = <0>;
1007
1008                 cpu@0 {
1009                         device_type = "cpu";
1010                         compatible = "arm,cortex-a9";
1011                         reg = <0>;
1012                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1013                 };
1014
1015                 cpu@1 {
1016                         device_type = "cpu";
1017                         compatible = "arm,cortex-a9";
1018                         reg = <1>;
1019                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1020                 };
1021
1022                 cpu@2 {
1023                         device_type = "cpu";
1024                         compatible = "arm,cortex-a9";
1025                         reg = <2>;
1026                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1027                 };
1028
1029                 cpu@3 {
1030                         device_type = "cpu";
1031                         compatible = "arm,cortex-a9";
1032                         reg = <3>;
1033                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1034                 };
1035         };
1036
1037         pmu {
1038                 compatible = "arm,cortex-a9-pmu";
1039                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1040                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1041                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1042                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1043                 interrupt-affinity = <&{/cpus/cpu@0}>,
1044                                      <&{/cpus/cpu@1}>,
1045                                      <&{/cpus/cpu@2}>,
1046                                      <&{/cpus/cpu@3}>;
1047         };
1048 };