arch/arm/boot/dts/tegra30.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra30-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra30-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8
   9 / {
  10         compatible = "nvidia,tegra30";
  11         interrupt-parent = <&lic>;
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x80000000 0x0>;
  18         };
  19
  20         pcie@3000 {
  21                 compatible = "nvidia,tegra30-pcie";
  22                 device_type = "pci";
  23                 reg = <0x00003000 0x00000800>, /* PADS registers */
  24                       <0x00003800 0x00000200>, /* AFI registers */
  25                       <0x10000000 0x10000000>; /* configuration space */
  26                 reg-names = "pads", "afi", "cs";
  27                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  28                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  29                 interrupt-names = "intr", "msi";
  30
  31                 #interrupt-cells = <1>;
  32                 interrupt-map-mask = <0 0 0 0>;
  33                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  34
  35                 bus-range = <0x00 0xff>;
  36                 #address-cells = <3>;
  37                 #size-cells = <2>;
  38
  39                 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
  40                          <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
  41                          <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
  42                          <0x01000000 0 0          0x02000000 0 0x00010000>, /* downstream I/O */
  43                          <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
  44                          <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  45
  46                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  47                          <&tegra_car TEGRA30_CLK_AFI>,
  48                          <&tegra_car TEGRA30_CLK_PLL_E>,
  49                          <&tegra_car TEGRA30_CLK_CML0>;
  50                 clock-names = "pex", "afi", "pll_e", "cml";
  51                 resets = <&tegra_car 70>,
  52                          <&tegra_car 72>,
  53                          <&tegra_car 74>;
  54                 reset-names = "pex", "afi", "pcie_x";
  55                 status = "disabled";
  56
  57                 pci@1,0 {
  58                         device_type = "pci";
  59                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  60                         reg = <0x000800 0 0 0 0>;
  61                         bus-range = <0x00 0xff>;
  62                         status = "disabled";
  63
  64                         #address-cells = <3>;
  65                         #size-cells = <2>;
  66                         ranges;
  67
  68                         nvidia,num-lanes = <2>;
  69                 };
  70
  71                 pci@2,0 {
  72                         device_type = "pci";
  73                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  74                         reg = <0x001000 0 0 0 0>;
  75                         bus-range = <0x00 0xff>;
  76                         status = "disabled";
  77
  78                         #address-cells = <3>;
  79                         #size-cells = <2>;
  80                         ranges;
  81
  82                         nvidia,num-lanes = <2>;
  83                 };
  84
  85                 pci@3,0 {
  86                         device_type = "pci";
  87                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  88                         reg = <0x001800 0 0 0 0>;
  89                         bus-range = <0x00 0xff>;
  90                         status = "disabled";
  91
  92                         #address-cells = <3>;
  93                         #size-cells = <2>;
  94                         ranges;
  95
  96                         nvidia,num-lanes = <2>;
  97                 };
  98         };
  99
 100         iram@40000000 {
 101                 compatible = "mmio-sram";
 102                 reg = <0x40000000 0x40000>;
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105                 ranges = <0 0x40000000 0x40000>;
 106
 107                 vde_pool: vde@400 {
 108                         reg = <0x400 0x3fc00>;
 109                         pool;
 110                 };
 111         };
 112
 113         host1x@50000000 {
 114                 compatible = "nvidia,tegra30-host1x";
 115                 reg = <0x50000000 0x00024000>;
 116                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 117                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 118                 interrupt-names = "syncpt", "host1x";
 119                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 120                 clock-names = "host1x";
 121                 resets = <&tegra_car 28>;
 122                 reset-names = "host1x";
 123                 iommus = <&mc TEGRA_SWGROUP_HC>;
 124
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127
 128                 ranges = <0x54000000 0x54000000 0x04000000>;
 129
 130                 mpe@54040000 {
 131                         compatible = "nvidia,tegra30-mpe";
 132                         reg = <0x54040000 0x00040000>;
 133                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 134                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 135                         resets = <&tegra_car 60>;
 136                         reset-names = "mpe";
 137
 138                         iommus = <&mc TEGRA_SWGROUP_MPE>;
 139                 };
 140
 141                 vi@54080000 {
 142                         compatible = "nvidia,tegra30-vi";
 143                         reg = <0x54080000 0x00040000>;
 144                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 145                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 146                         resets = <&tegra_car 20>;
 147                         reset-names = "vi";
 148
 149                         iommus = <&mc TEGRA_SWGROUP_VI>;
 150                 };
 151
 152                 epp@540c0000 {
 153                         compatible = "nvidia,tegra30-epp";
 154                         reg = <0x540c0000 0x00040000>;
 155                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 156                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 157                         resets = <&tegra_car 19>;
 158                         reset-names = "epp";
 159
 160                         iommus = <&mc TEGRA_SWGROUP_EPP>;
 161                 };
 162
 163                 isp@54100000 {
 164                         compatible = "nvidia,tegra30-isp";
 165                         reg = <0x54100000 0x00040000>;
 166                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 167                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 168                         resets = <&tegra_car 23>;
 169                         reset-names = "isp";
 170
 171                         iommus = <&mc TEGRA_SWGROUP_ISP>;
 172                 };
 173
 174                 gr2d@54140000 {
 175                         compatible = "nvidia,tegra30-gr2d";
 176                         reg = <0x54140000 0x00040000>;
 177                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 178                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 179                         resets = <&tegra_car 21>;
 180                         reset-names = "2d";
 181
 182                         iommus = <&mc TEGRA_SWGROUP_G2>;
 183                 };
 184
 185                 gr3d@54180000 {
 186                         compatible = "nvidia,tegra30-gr3d";
 187                         reg = <0x54180000 0x00040000>;
 188                         clocks = <&tegra_car TEGRA30_CLK_GR3D>,
 189                                  <&tegra_car TEGRA30_CLK_GR3D2>;
 190                         clock-names = "3d", "3d2";
 191                         resets = <&tegra_car 24>,
 192                                  <&tegra_car 98>;
 193                         reset-names = "3d", "3d2";
 194
 195                         iommus = <&mc TEGRA_SWGROUP_NV>,
 196                                  <&mc TEGRA_SWGROUP_NV2>;
 197                 };
 198
 199                 dc@54200000 {
 200                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 201                         reg = <0x54200000 0x00040000>;
 202                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 203                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 204                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 205                         clock-names = "dc", "parent";
 206                         resets = <&tegra_car 27>;
 207                         reset-names = "dc";
 208
 209                         iommus = <&mc TEGRA_SWGROUP_DC>;
 210
 211                         nvidia,head = <0>;
 212
 213                         rgb {
 214                                 status = "disabled";
 215                         };
 216                 };
 217
 218                 dc@54240000 {
 219                         compatible = "nvidia,tegra30-dc";
 220                         reg = <0x54240000 0x00040000>;
 221                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 222                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 223                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 224                         clock-names = "dc", "parent";
 225                         resets = <&tegra_car 26>;
 226                         reset-names = "dc";
 227
 228                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 229
 230                         nvidia,head = <1>;
 231
 232                         rgb {
 233                                 status = "disabled";
 234                         };
 235                 };
 236
 237                 hdmi@54280000 {
 238                         compatible = "nvidia,tegra30-hdmi";
 239                         reg = <0x54280000 0x00040000>;
 240                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 242                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 243                         clock-names = "hdmi", "parent";
 244                         resets = <&tegra_car 51>;
 245                         reset-names = "hdmi";
 246                         status = "disabled";
 247                 };
 248
 249                 tvo@542c0000 {
 250                         compatible = "nvidia,tegra30-tvo";
 251                         reg = <0x542c0000 0x00040000>;
 252                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 254                         status = "disabled";
 255                 };
 256
 257                 dsi@54300000 {
 258                         compatible = "nvidia,tegra30-dsi";
 259                         reg = <0x54300000 0x00040000>;
 260                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 261                         resets = <&tegra_car 48>;
 262                         reset-names = "dsi";
 263                         status = "disabled";
 264                 };
 265         };
 266
 267         timer@50040600 {
 268                 compatible = "arm,cortex-a9-twd-timer";
 269                 reg = <0x50040600 0x20>;
 270                 interrupt-parent = <&intc>;
 271                 interrupts = <GIC_PPI 13
 272                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 273                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 274         };
 275
 276         intc: interrupt-controller@50041000 {
 277                 compatible = "arm,cortex-a9-gic";
 278                 reg = <0x50041000 0x1000>,
 279                       <0x50040100 0x0100>;
 280                 interrupt-controller;
 281                 #interrupt-cells = <3>;
 282                 interrupt-parent = <&intc>;
 283         };
 284
 285         cache-controller@50043000 {
 286                 compatible = "arm,pl310-cache";
 287                 reg = <0x50043000 0x1000>;
 288                 arm,data-latency = <6 6 2>;
 289                 arm,tag-latency = <5 5 2>;
 290                 cache-unified;
 291                 cache-level = <2>;
 292         };
 293
 294         lic: interrupt-controller@60004000 {
 295                 compatible = "nvidia,tegra30-ictlr";
 296                 reg = <0x60004000 0x100>,
 297                       <0x60004100 0x50>,
 298                       <0x60004200 0x50>,
 299                       <0x60004300 0x50>,
 300                       <0x60004400 0x50>;
 301                 interrupt-controller;
 302                 #interrupt-cells = <3>;
 303                 interrupt-parent = <&intc>;
 304         };
 305
 306         timer@60005000 {
 307                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 308                 reg = <0x60005000 0x400>;
 309                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 316         };
 317
 318         tegra_car: clock@60006000 {
 319                 compatible = "nvidia,tegra30-car";
 320                 reg = <0x60006000 0x1000>;
 321                 #clock-cells = <1>;
 322                 #reset-cells = <1>;
 323         };
 324
 325         flow-controller@60007000 {
 326                 compatible = "nvidia,tegra30-flowctrl";
 327                 reg = <0x60007000 0x1000>;
 328         };
 329
 330         apbdma: dma@6000a000 {
 331                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 332                 reg = <0x6000a000 0x1400>;
 333                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 336                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 337                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 338                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 339                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 340                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 342                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 343                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 344                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 345                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 347                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 350                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 351                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 352                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 353                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 354                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 355                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 356                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 357                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 358                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 359                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 360                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 361                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 362                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 363                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 364                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 366                 resets = <&tegra_car 34>;
 367                 reset-names = "dma";
 368                 #dma-cells = <1>;
 369         };
 370
 371         ahb: ahb@6000c000 {
 372                 compatible = "nvidia,tegra30-ahb";
 373                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 374         };
 375
 376         actmon@6000c800 {
 377                 compatible = "nvidia,tegra30-actmon";
 378                 reg = <0x6000c800 0x400>;
 379                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
 381                          <&tegra_car TEGRA30_CLK_EMC>;
 382                 clock-names = "actmon", "emc";
 383                 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
 384                 reset-names = "actmon";
 385         };
 386
 387         gpio: gpio@6000d000 {
 388                 compatible = "nvidia,tegra30-gpio";
 389                 reg = <0x6000d000 0x1000>;
 390                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 393                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 394                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 395                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 396                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 397                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 398                 #gpio-cells = <2>;
 399                 gpio-controller;
 400                 #interrupt-cells = <2>;
 401                 interrupt-controller;
 402                 /*
 403                 gpio-ranges = <&pinmux 0 0 248>;
 404                 */
 405         };
 406
 407         vde@6001a000 {
 408                 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
 409                 reg = <0x6001a000 0x1000>, /* Syntax Engine */
 410                       <0x6001b000 0x1000>, /* Video Bitstream Engine */
 411                       <0x6001c000  0x100>, /* Macroblock Engine */
 412                       <0x6001c200  0x100>, /* Post-processing Engine */
 413                       <0x6001c400  0x100>, /* Motion Compensation Engine */
 414                       <0x6001c600  0x100>, /* Transform Engine */
 415                       <0x6001c800  0x100>, /* Pixel prediction block */
 416                       <0x6001ca00  0x100>, /* Video DMA */
 417                       <0x6001d800  0x400>; /* Video frame controls */
 418                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 419                             "tfe", "ppb", "vdma", "frameid";
 420                 iram = <&vde_pool>; /* IRAM region */
 421                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 422                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 423                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 424                 interrupt-names = "sync-token", "bsev", "sxe";
 425                 clocks = <&tegra_car TEGRA30_CLK_VDE>;
 426                 reset-names = "vde", "mc";
 427                 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
 428                 iommus = <&mc TEGRA_SWGROUP_VDE>;
 429         };
 430
 431         apbmisc@70000800 {
 432                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 433                 reg = <0x70000800 0x64>, /* Chip revision */
 434                       <0x70000008 0x04>; /* Strapping options */
 435         };
 436
 437         pinmux: pinmux@70000868 {
 438                 compatible = "nvidia,tegra30-pinmux";
 439                 reg = <0x70000868 0x0d4>, /* Pad control registers */
 440                       <0x70003000 0x3e4>; /* Mux registers */
 441         };
 442
 443         /*
 444          * There are two serial driver i.e. 8250 based simple serial
 445          * driver and APB DMA based serial driver for higher baudrate
 446          * and performace. To enable the 8250 based driver, the compatible
 447          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 448          * the APB DMA based serial driver, the compatible is
 449          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 450          */
 451         uarta: serial@70006000 {
 452                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 453                 reg = <0x70006000 0x40>;
 454                 reg-shift = <2>;
 455                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 456                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 457                 resets = <&tegra_car 6>;
 458                 reset-names = "serial";
 459                 dmas = <&apbdma 8>, <&apbdma 8>;
 460                 dma-names = "rx", "tx";
 461                 status = "disabled";
 462         };
 463
 464         uartb: serial@70006040 {
 465                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 466                 reg = <0x70006040 0x40>;
 467                 reg-shift = <2>;
 468                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 469                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 470                 resets = <&tegra_car 7>;
 471                 reset-names = "serial";
 472                 dmas = <&apbdma 9>, <&apbdma 9>;
 473                 dma-names = "rx", "tx";
 474                 status = "disabled";
 475         };
 476
 477         uartc: serial@70006200 {
 478                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 479                 reg = <0x70006200 0x100>;
 480                 reg-shift = <2>;
 481                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 483                 resets = <&tegra_car 55>;
 484                 reset-names = "serial";
 485                 dmas = <&apbdma 10>, <&apbdma 10>;
 486                 dma-names = "rx", "tx";
 487                 status = "disabled";
 488         };
 489
 490         uartd: serial@70006300 {
 491                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 492                 reg = <0x70006300 0x100>;
 493                 reg-shift = <2>;
 494                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 495                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 496                 resets = <&tegra_car 65>;
 497                 reset-names = "serial";
 498                 dmas = <&apbdma 19>, <&apbdma 19>;
 499                 dma-names = "rx", "tx";
 500                 status = "disabled";
 501         };
 502
 503         uarte: serial@70006400 {
 504                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 505                 reg = <0x70006400 0x100>;
 506                 reg-shift = <2>;
 507                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 509                 resets = <&tegra_car 66>;
 510                 reset-names = "serial";
 511                 dmas = <&apbdma 20>, <&apbdma 20>;
 512                 dma-names = "rx", "tx";
 513                 status = "disabled";
 514         };
 515
 516         gmi@70009000 {
 517                 compatible = "nvidia,tegra30-gmi";
 518                 reg = <0x70009000 0x1000>;
 519                 #address-cells = <2>;
 520                 #size-cells = <1>;
 521                 ranges = <0 0 0x48000000 0x7ffffff>;
 522                 clocks = <&tegra_car TEGRA30_CLK_NOR>;
 523                 clock-names = "gmi";
 524                 resets = <&tegra_car 42>;
 525                 reset-names = "gmi";
 526                 status = "disabled";
 527         };
 528
 529         pwm: pwm@7000a000 {
 530                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 531                 reg = <0x7000a000 0x100>;
 532                 #pwm-cells = <2>;
 533                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 534                 resets = <&tegra_car 17>;
 535                 reset-names = "pwm";
 536                 status = "disabled";
 537         };
 538
 539         rtc@7000e000 {
 540                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 541                 reg = <0x7000e000 0x100>;
 542                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 543                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 544         };
 545
 546         i2c@7000c000 {
 547                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 548                 reg = <0x7000c000 0x100>;
 549                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 553                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 554                 clock-names = "div-clk", "fast-clk";
 555                 resets = <&tegra_car 12>;
 556                 reset-names = "i2c";
 557                 dmas = <&apbdma 21>, <&apbdma 21>;
 558                 dma-names = "rx", "tx";
 559                 status = "disabled";
 560         };
 561
 562         i2c@7000c400 {
 563                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 564                 reg = <0x7000c400 0x100>;
 565                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 569                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 570                 clock-names = "div-clk", "fast-clk";
 571                 resets = <&tegra_car 54>;
 572                 reset-names = "i2c";
 573                 dmas = <&apbdma 22>, <&apbdma 22>;
 574                 dma-names = "rx", "tx";
 575                 status = "disabled";
 576         };
 577
 578         i2c@7000c500 {
 579                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 580                 reg = <0x7000c500 0x100>;
 581                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 585                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 586                 clock-names = "div-clk", "fast-clk";
 587                 resets = <&tegra_car 67>;
 588                 reset-names = "i2c";
 589                 dmas = <&apbdma 23>, <&apbdma 23>;
 590                 dma-names = "rx", "tx";
 591                 status = "disabled";
 592         };
 593
 594         i2c@7000c700 {
 595                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 596                 reg = <0x7000c700 0x100>;
 597                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 601                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 602                 resets = <&tegra_car 103>;
 603                 reset-names = "i2c";
 604                 clock-names = "div-clk", "fast-clk";
 605                 dmas = <&apbdma 26>, <&apbdma 26>;
 606                 dma-names = "rx", "tx";
 607                 status = "disabled";
 608         };
 609
 610         i2c@7000d000 {
 611                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 612                 reg = <0x7000d000 0x100>;
 613                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 617                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 618                 clock-names = "div-clk", "fast-clk";
 619                 resets = <&tegra_car 47>;
 620                 reset-names = "i2c";
 621                 dmas = <&apbdma 24>, <&apbdma 24>;
 622                 dma-names = "rx", "tx";
 623                 status = "disabled";
 624         };
 625
 626         spi@7000d400 {
 627                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 628                 reg = <0x7000d400 0x200>;
 629                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 633                 resets = <&tegra_car 41>;
 634                 reset-names = "spi";
 635                 dmas = <&apbdma 15>, <&apbdma 15>;
 636                 dma-names = "rx", "tx";
 637                 status = "disabled";
 638         };
 639
 640         spi@7000d600 {
 641                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 642                 reg = <0x7000d600 0x200>;
 643                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 647                 resets = <&tegra_car 44>;
 648                 reset-names = "spi";
 649                 dmas = <&apbdma 16>, <&apbdma 16>;
 650                 dma-names = "rx", "tx";
 651                 status = "disabled";
 652         };
 653
 654         spi@7000d800 {
 655                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 656                 reg = <0x7000d800 0x200>;
 657                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 661                 resets = <&tegra_car 46>;
 662                 reset-names = "spi";
 663                 dmas = <&apbdma 17>, <&apbdma 17>;
 664                 dma-names = "rx", "tx";
 665                 status = "disabled";
 666         };
 667
 668         spi@7000da00 {
 669                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 670                 reg = <0x7000da00 0x200>;
 671                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 675                 resets = <&tegra_car 68>;
 676                 reset-names = "spi";
 677                 dmas = <&apbdma 18>, <&apbdma 18>;
 678                 dma-names = "rx", "tx";
 679                 status = "disabled";
 680         };
 681
 682         spi@7000dc00 {
 683                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 684                 reg = <0x7000dc00 0x200>;
 685                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 689                 resets = <&tegra_car 104>;
 690                 reset-names = "spi";
 691                 dmas = <&apbdma 27>, <&apbdma 27>;
 692                 dma-names = "rx", "tx";
 693                 status = "disabled";
 694         };
 695
 696         spi@7000de00 {
 697                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 698                 reg = <0x7000de00 0x200>;
 699                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 703                 resets = <&tegra_car 106>;
 704                 reset-names = "spi";
 705                 dmas = <&apbdma 28>, <&apbdma 28>;
 706                 dma-names = "rx", "tx";
 707                 status = "disabled";
 708         };
 709
 710         kbc@7000e200 {
 711                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 712                 reg = <0x7000e200 0x100>;
 713                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 714                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 715                 resets = <&tegra_car 36>;
 716                 reset-names = "kbc";
 717                 status = "disabled";
 718         };
 719
 720         tegra_pmc: pmc@7000e400 {
 721                 compatible = "nvidia,tegra30-pmc";
 722                 reg = <0x7000e400 0x400>;
 723                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 724                 clock-names = "pclk", "clk32k_in";
 725                 #clock-cells = <1>;
 726         };
 727
 728         mc: memory-controller@7000f000 {
 729                 compatible = "nvidia,tegra30-mc";
 730                 reg = <0x7000f000 0x400>;
 731                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 732                 clock-names = "mc";
 733
 734                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 735
 736                 #iommu-cells = <1>;
 737                 #reset-cells = <1>;
 738         };
 739
 740         memory-controller@7000f400 {
 741                 compatible = "nvidia,tegra30-emc";
 742                 reg = <0x7000f400 0x400>;
 743                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 744                 clocks = <&tegra_car TEGRA30_CLK_EMC>;
 745
 746                 nvidia,memory-controller = <&mc>;
 747         };
 748
 749         fuse@7000f800 {
 750                 compatible = "nvidia,tegra30-efuse";
 751                 reg = <0x7000f800 0x400>;
 752                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 753                 clock-names = "fuse";
 754                 resets = <&tegra_car 39>;
 755                 reset-names = "fuse";
 756         };
 757
 758         hda@70030000 {
 759                 compatible = "nvidia,tegra30-hda";
 760                 reg = <0x70030000 0x10000>;
 761                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 762                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 763                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 764                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 765                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 766                 resets = <&tegra_car 125>, /* hda */
 767                          <&tegra_car 128>, /* hda2hdmi */
 768                          <&tegra_car 111>; /* hda2codec_2x */
 769                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 770                 status = "disabled";
 771         };
 772
 773         ahub@70080000 {
 774                 compatible = "nvidia,tegra30-ahub";
 775                 reg = <0x70080000 0x200>,
 776                       <0x70080200 0x100>;
 777                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 778                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 779                          <&tegra_car TEGRA30_CLK_APBIF>;
 780                 clock-names = "d_audio", "apbif";
 781                 resets = <&tegra_car 106>, /* d_audio */
 782                          <&tegra_car 107>, /* apbif */
 783                          <&tegra_car 30>,  /* i2s0 */
 784                          <&tegra_car 11>,  /* i2s1 */
 785                          <&tegra_car 18>,  /* i2s2 */
 786                          <&tegra_car 101>, /* i2s3 */
 787                          <&tegra_car 102>, /* i2s4 */
 788                          <&tegra_car 108>, /* dam0 */
 789                          <&tegra_car 109>, /* dam1 */
 790                          <&tegra_car 110>, /* dam2 */
 791                          <&tegra_car 10>;  /* spdif */
 792                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 793                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 794                               "spdif";
 795                 dmas = <&apbdma 1>, <&apbdma 1>,
 796                        <&apbdma 2>, <&apbdma 2>,
 797                        <&apbdma 3>, <&apbdma 3>,
 798                        <&apbdma 4>, <&apbdma 4>;
 799                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 800                             "rx3", "tx3";
 801                 ranges;
 802                 #address-cells = <1>;
 803                 #size-cells = <1>;
 804
 805                 tegra_i2s0: i2s@70080300 {
 806                         compatible = "nvidia,tegra30-i2s";
 807                         reg = <0x70080300 0x100>;
 808                         nvidia,ahub-cif-ids = <4 4>;
 809                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 810                         resets = <&tegra_car 30>;
 811                         reset-names = "i2s";
 812                         status = "disabled";
 813                 };
 814
 815                 tegra_i2s1: i2s@70080400 {
 816                         compatible = "nvidia,tegra30-i2s";
 817                         reg = <0x70080400 0x100>;
 818                         nvidia,ahub-cif-ids = <5 5>;
 819                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 820                         resets = <&tegra_car 11>;
 821                         reset-names = "i2s";
 822                         status = "disabled";
 823                 };
 824
 825                 tegra_i2s2: i2s@70080500 {
 826                         compatible = "nvidia,tegra30-i2s";
 827                         reg = <0x70080500 0x100>;
 828                         nvidia,ahub-cif-ids = <6 6>;
 829                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 830                         resets = <&tegra_car 18>;
 831                         reset-names = "i2s";
 832                         status = "disabled";
 833                 };
 834
 835                 tegra_i2s3: i2s@70080600 {
 836                         compatible = "nvidia,tegra30-i2s";
 837                         reg = <0x70080600 0x100>;
 838                         nvidia,ahub-cif-ids = <7 7>;
 839                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 840                         resets = <&tegra_car 101>;
 841                         reset-names = "i2s";
 842                         status = "disabled";
 843                 };
 844
 845                 tegra_i2s4: i2s@70080700 {
 846                         compatible = "nvidia,tegra30-i2s";
 847                         reg = <0x70080700 0x100>;
 848                         nvidia,ahub-cif-ids = <8 8>;
 849                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 850                         resets = <&tegra_car 102>;
 851                         reset-names = "i2s";
 852                         status = "disabled";
 853                 };
 854         };
 855
 856         mmc@78000000 {
 857                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 858                 reg = <0x78000000 0x200>;
 859                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 860                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 861                 resets = <&tegra_car 14>;
 862                 reset-names = "sdhci";
 863                 status = "disabled";
 864         };
 865
 866         mmc@78000200 {
 867                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 868                 reg = <0x78000200 0x200>;
 869                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 870                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 871                 resets = <&tegra_car 9>;
 872                 reset-names = "sdhci";
 873                 status = "disabled";
 874         };
 875
 876         mmc@78000400 {
 877                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 878                 reg = <0x78000400 0x200>;
 879                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 880                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 881                 resets = <&tegra_car 69>;
 882                 reset-names = "sdhci";
 883                 status = "disabled";
 884         };
 885
 886         mmc@78000600 {
 887                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 888                 reg = <0x78000600 0x200>;
 889                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 890                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 891                 resets = <&tegra_car 15>;
 892                 reset-names = "sdhci";
 893                 status = "disabled";
 894         };
 895
 896         usb@7d000000 {
 897                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 898                 reg = <0x7d000000 0x4000>;
 899                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 900                 phy_type = "utmi";
 901                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 902                 resets = <&tegra_car 22>;
 903                 reset-names = "usb";
 904                 nvidia,needs-double-reset;
 905                 nvidia,phy = <&phy1>;
 906                 status = "disabled";
 907         };
 908
 909         phy1: usb-phy@7d000000 {
 910                 compatible = "nvidia,tegra30-usb-phy";
 911                 reg = <0x7d000000 0x4000>,
 912                       <0x7d000000 0x4000>;
 913                 phy_type = "utmi";
 914                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 915                          <&tegra_car TEGRA30_CLK_PLL_U>,
 916                          <&tegra_car TEGRA30_CLK_USBD>;
 917                 clock-names = "reg", "pll_u", "utmi-pads";
 918                 resets = <&tegra_car 22>, <&tegra_car 22>;
 919                 reset-names = "usb", "utmi-pads";
 920                 #phy-cells = <0>;
 921                 nvidia,hssync-start-delay = <9>;
 922                 nvidia,idle-wait-delay = <17>;
 923                 nvidia,elastic-limit = <16>;
 924                 nvidia,term-range-adj = <6>;
 925                 nvidia,xcvr-setup = <51>;
 926                 nvidia,xcvr-setup-use-fuses;
 927                 nvidia,xcvr-lsfslew = <1>;
 928                 nvidia,xcvr-lsrslew = <1>;
 929                 nvidia,xcvr-hsslew = <32>;
 930                 nvidia,hssquelch-level = <2>;
 931                 nvidia,hsdiscon-level = <5>;
 932                 nvidia,has-utmi-pad-registers;
 933                 status = "disabled";
 934         };
 935
 936         usb@7d004000 {
 937                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 938                 reg = <0x7d004000 0x4000>;
 939                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 940                 phy_type = "utmi";
 941                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 942                 resets = <&tegra_car 58>;
 943                 reset-names = "usb";
 944                 nvidia,phy = <&phy2>;
 945                 status = "disabled";
 946         };
 947
 948         phy2: usb-phy@7d004000 {
 949                 compatible = "nvidia,tegra30-usb-phy";
 950                 reg = <0x7d004000 0x4000>,
 951                       <0x7d000000 0x4000>;
 952                 phy_type = "utmi";
 953                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 954                          <&tegra_car TEGRA30_CLK_PLL_U>,
 955                          <&tegra_car TEGRA30_CLK_USBD>;
 956                 clock-names = "reg", "pll_u", "utmi-pads";
 957                 resets = <&tegra_car 58>, <&tegra_car 22>;
 958                 reset-names = "usb", "utmi-pads";
 959                 #phy-cells = <0>;
 960                 nvidia,hssync-start-delay = <9>;
 961                 nvidia,idle-wait-delay = <17>;
 962                 nvidia,elastic-limit = <16>;
 963                 nvidia,term-range-adj = <6>;
 964                 nvidia,xcvr-setup = <51>;
 965                 nvidia,xcvr-setup-use-fuses;
 966                 nvidia,xcvr-lsfslew = <2>;
 967                 nvidia,xcvr-lsrslew = <2>;
 968                 nvidia,xcvr-hsslew = <32>;
 969                 nvidia,hssquelch-level = <2>;
 970                 nvidia,hsdiscon-level = <5>;
 971                 status = "disabled";
 972         };
 973
 974         usb@7d008000 {
 975                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 976                 reg = <0x7d008000 0x4000>;
 977                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 978                 phy_type = "utmi";
 979                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 980                 resets = <&tegra_car 59>;
 981                 reset-names = "usb";
 982                 nvidia,phy = <&phy3>;
 983                 status = "disabled";
 984         };
 985
 986         phy3: usb-phy@7d008000 {
 987                 compatible = "nvidia,tegra30-usb-phy";
 988                 reg = <0x7d008000 0x4000>,
 989                       <0x7d000000 0x4000>;
 990                 phy_type = "utmi";
 991                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 992                          <&tegra_car TEGRA30_CLK_PLL_U>,
 993                          <&tegra_car TEGRA30_CLK_USBD>;
 994                 clock-names = "reg", "pll_u", "utmi-pads";
 995                 resets = <&tegra_car 59>, <&tegra_car 22>;
 996                 reset-names = "usb", "utmi-pads";
 997                 #phy-cells = <0>;
 998                 nvidia,hssync-start-delay = <0>;
 999                 nvidia,idle-wait-delay = <17>;
1000                 nvidia,elastic-limit = <16>;
1001                 nvidia,term-range-adj = <6>;
1002                 nvidia,xcvr-setup = <51>;
1003                 nvidia,xcvr-setup-use-fuses;
1004                 nvidia,xcvr-lsfslew = <2>;
1005                 nvidia,xcvr-lsrslew = <2>;
1006                 nvidia,xcvr-hsslew = <32>;
1007                 nvidia,hssquelch-level = <2>;
1008                 nvidia,hsdiscon-level = <5>;
1009                 status = "disabled";
1010         };
1011
1012         cpus {
1013                 #address-cells = <1>;
1014                 #size-cells = <0>;
1015
1016                 cpu@0 {
1017                         device_type = "cpu";
1018                         compatible = "arm,cortex-a9";
1019                         reg = <0>;
1020                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1021                 };
1022
1023                 cpu@1 {
1024                         device_type = "cpu";
1025                         compatible = "arm,cortex-a9";
1026                         reg = <1>;
1027                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1028                 };
1029
1030                 cpu@2 {
1031                         device_type = "cpu";
1032                         compatible = "arm,cortex-a9";
1033                         reg = <2>;
1034                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1035                 };
1036
1037                 cpu@3 {
1038                         device_type = "cpu";
1039                         compatible = "arm,cortex-a9";
1040                         reg = <3>;
1041                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1042                 };
1043         };
1044
1045         pmu {
1046                 compatible = "arm,cortex-a9-pmu";
1047                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1048                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1049                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1050                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1051                 interrupt-affinity = <&{/cpus/cpu@0}>,
1052                                      <&{/cpus/cpu@1}>,
1053                                      <&{/cpus/cpu@2}>,
1054                                      <&{/cpus/cpu@3}>;
1055         };
1056 };