1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include "skeleton.dtsi"
9 compatible = "nvidia,tegra30";
10 interrupt-parent = <&intc>;
20 pcie-controller@00003000 {
21 compatible = "nvidia,tegra30-pcie";
23 reg = <0x00003000 0x00000800 /* PADS registers */
24 0x00003800 0x00000200 /* AFI registers */
25 0x10000000 0x10000000>; /* configuration space */
26 reg-names = "pads", "afi", "cs";
27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
28 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi";
31 bus-range = <0x00 0xff>;
35 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
36 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
37 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
38 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
39 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
40 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
42 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
43 <&tegra_car TEGRA30_CLK_AFI>,
44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
50 reset-names = "pex", "afi", "pcie_x";
55 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
56 reg = <0x000800 0 0 0 0>;
63 nvidia,num-lanes = <2>;
68 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
69 reg = <0x001000 0 0 0 0>;
76 nvidia,num-lanes = <2>;
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
89 nvidia,num-lanes = <2>;
94 compatible = "nvidia,tegra30-host1x", "simple-bus";
95 reg = <0x50000000 0x00024000>;
96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
97 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
98 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
99 resets = <&tegra_car 28>;
100 reset-names = "host1x";
102 #address-cells = <1>;
105 ranges = <0x54000000 0x54000000 0x04000000>;
108 compatible = "nvidia,tegra30-mpe";
109 reg = <0x54040000 0x00040000>;
110 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&tegra_car TEGRA30_CLK_MPE>;
112 resets = <&tegra_car 60>;
117 compatible = "nvidia,tegra30-vi";
118 reg = <0x54080000 0x00040000>;
119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA30_CLK_VI>;
121 resets = <&tegra_car 20>;
126 compatible = "nvidia,tegra30-epp";
127 reg = <0x540c0000 0x00040000>;
128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&tegra_car TEGRA30_CLK_EPP>;
130 resets = <&tegra_car 19>;
135 compatible = "nvidia,tegra30-isp";
136 reg = <0x54100000 0x00040000>;
137 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&tegra_car TEGRA30_CLK_ISP>;
139 resets = <&tegra_car 23>;
144 compatible = "nvidia,tegra30-gr2d";
145 reg = <0x54140000 0x00040000>;
146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
147 resets = <&tegra_car 21>;
149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
153 compatible = "nvidia,tegra30-gr3d";
154 reg = <0x54180000 0x00040000>;
155 clocks = <&tegra_car TEGRA30_CLK_GR3D
156 &tegra_car TEGRA30_CLK_GR3D2>;
157 clock-names = "3d", "3d2";
158 resets = <&tegra_car 24>,
160 reset-names = "3d", "3d2";
164 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
165 reg = <0x54200000 0x00040000>;
166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
168 <&tegra_car TEGRA30_CLK_PLL_P>;
169 clock-names = "dc", "parent";
170 resets = <&tegra_car 27>;
181 compatible = "nvidia,tegra30-dc";
182 reg = <0x54240000 0x00040000>;
183 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
185 <&tegra_car TEGRA30_CLK_PLL_P>;
186 clock-names = "dc", "parent";
187 resets = <&tegra_car 26>;
198 compatible = "nvidia,tegra30-hdmi";
199 reg = <0x54280000 0x00040000>;
200 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
202 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
203 clock-names = "hdmi", "parent";
204 resets = <&tegra_car 51>;
205 reset-names = "hdmi";
210 compatible = "nvidia,tegra30-tvo";
211 reg = <0x542c0000 0x00040000>;
212 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&tegra_car TEGRA30_CLK_TVO>;
218 compatible = "nvidia,tegra30-dsi";
219 reg = <0x54300000 0x00040000>;
220 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
221 resets = <&tegra_car 48>;
228 compatible = "arm,cortex-a9-twd-timer";
229 reg = <0x50040600 0x20>;
230 interrupts = <GIC_PPI 13
231 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
232 clocks = <&tegra_car TEGRA30_CLK_TWD>;
235 intc: interrupt-controller@50041000 {
236 compatible = "arm,cortex-a9-gic";
237 reg = <0x50041000 0x1000
239 interrupt-controller;
240 #interrupt-cells = <3>;
243 cache-controller@50043000 {
244 compatible = "arm,pl310-cache";
245 reg = <0x50043000 0x1000>;
246 arm,data-latency = <6 6 2>;
247 arm,tag-latency = <5 5 2>;
253 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
254 reg = <0x60005000 0x400>;
255 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
264 tegra_car: clock@60006000 {
265 compatible = "nvidia,tegra30-car";
266 reg = <0x60006000 0x1000>;
271 apbdma: dma@6000a000 {
272 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
273 reg = <0x6000a000 0x1400>;
274 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
307 resets = <&tegra_car 34>;
313 compatible = "nvidia,tegra30-ahb";
314 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
317 gpio: gpio@6000d000 {
318 compatible = "nvidia,tegra30-gpio";
319 reg = <0x6000d000 0x1000>;
320 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
330 #interrupt-cells = <2>;
331 interrupt-controller;
334 pinmux: pinmux@70000868 {
335 compatible = "nvidia,tegra30-pinmux";
336 reg = <0x70000868 0xd4 /* Pad control registers */
337 0x70003000 0x3e4>; /* Mux registers */
341 * There are two serial driver i.e. 8250 based simple serial
342 * driver and APB DMA based serial driver for higher baudrate
343 * and performace. To enable the 8250 based driver, the compatible
344 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
345 * the APB DMA based serial driver, the comptible is
346 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
348 uarta: serial@70006000 {
349 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
350 reg = <0x70006000 0x40>;
352 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
354 resets = <&tegra_car 6>;
355 reset-names = "serial";
356 dmas = <&apbdma 8>, <&apbdma 8>;
357 dma-names = "rx", "tx";
361 uartb: serial@70006040 {
362 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
363 reg = <0x70006040 0x40>;
365 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
367 resets = <&tegra_car 7>;
368 reset-names = "serial";
369 dmas = <&apbdma 9>, <&apbdma 9>;
370 dma-names = "rx", "tx";
374 uartc: serial@70006200 {
375 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
376 reg = <0x70006200 0x100>;
378 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
380 resets = <&tegra_car 55>;
381 reset-names = "serial";
382 dmas = <&apbdma 10>, <&apbdma 10>;
383 dma-names = "rx", "tx";
387 uartd: serial@70006300 {
388 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
389 reg = <0x70006300 0x100>;
391 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
393 resets = <&tegra_car 65>;
394 reset-names = "serial";
395 dmas = <&apbdma 19>, <&apbdma 19>;
396 dma-names = "rx", "tx";
400 uarte: serial@70006400 {
401 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
402 reg = <0x70006400 0x100>;
404 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
406 resets = <&tegra_car 66>;
407 reset-names = "serial";
408 dmas = <&apbdma 20>, <&apbdma 20>;
409 dma-names = "rx", "tx";
414 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
415 reg = <0x7000a000 0x100>;
417 clocks = <&tegra_car TEGRA30_CLK_PWM>;
418 resets = <&tegra_car 17>;
424 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
425 reg = <0x7000e000 0x100>;
426 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&tegra_car TEGRA30_CLK_RTC>;
431 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
432 reg = <0x7000c000 0x100>;
433 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
434 #address-cells = <1>;
436 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
437 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
438 clock-names = "div-clk", "fast-clk";
439 resets = <&tegra_car 12>;
441 dmas = <&apbdma 21>, <&apbdma 21>;
442 dma-names = "rx", "tx";
447 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
448 reg = <0x7000c400 0x100>;
449 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
452 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
453 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
454 clock-names = "div-clk", "fast-clk";
455 resets = <&tegra_car 54>;
457 dmas = <&apbdma 22>, <&apbdma 22>;
458 dma-names = "rx", "tx";
463 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
464 reg = <0x7000c500 0x100>;
465 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
468 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
469 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
470 clock-names = "div-clk", "fast-clk";
471 resets = <&tegra_car 67>;
473 dmas = <&apbdma 23>, <&apbdma 23>;
474 dma-names = "rx", "tx";
479 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
480 reg = <0x7000c700 0x100>;
481 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
484 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
485 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
486 resets = <&tegra_car 103>;
488 clock-names = "div-clk", "fast-clk";
489 dmas = <&apbdma 26>, <&apbdma 26>;
490 dma-names = "rx", "tx";
495 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
496 reg = <0x7000d000 0x100>;
497 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
498 #address-cells = <1>;
500 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
501 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
502 clock-names = "div-clk", "fast-clk";
503 resets = <&tegra_car 47>;
505 dmas = <&apbdma 24>, <&apbdma 24>;
506 dma-names = "rx", "tx";
511 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
512 reg = <0x7000d400 0x200>;
513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
514 #address-cells = <1>;
516 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
517 resets = <&tegra_car 41>;
519 dmas = <&apbdma 15>, <&apbdma 15>;
520 dma-names = "rx", "tx";
525 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
526 reg = <0x7000d600 0x200>;
527 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
528 #address-cells = <1>;
530 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
531 resets = <&tegra_car 44>;
533 dmas = <&apbdma 16>, <&apbdma 16>;
534 dma-names = "rx", "tx";
539 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
540 reg = <0x7000d800 0x200>;
541 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
542 #address-cells = <1>;
544 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
545 resets = <&tegra_car 46>;
547 dmas = <&apbdma 17>, <&apbdma 17>;
548 dma-names = "rx", "tx";
553 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
554 reg = <0x7000da00 0x200>;
555 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
556 #address-cells = <1>;
558 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
559 resets = <&tegra_car 68>;
561 dmas = <&apbdma 18>, <&apbdma 18>;
562 dma-names = "rx", "tx";
567 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
568 reg = <0x7000dc00 0x200>;
569 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
572 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
573 resets = <&tegra_car 104>;
575 dmas = <&apbdma 27>, <&apbdma 27>;
576 dma-names = "rx", "tx";
581 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
582 reg = <0x7000de00 0x200>;
583 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
584 #address-cells = <1>;
586 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
587 resets = <&tegra_car 106>;
589 dmas = <&apbdma 28>, <&apbdma 28>;
590 dma-names = "rx", "tx";
595 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
596 reg = <0x7000e200 0x100>;
597 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&tegra_car TEGRA30_CLK_KBC>;
599 resets = <&tegra_car 36>;
605 compatible = "nvidia,tegra30-pmc";
606 reg = <0x7000e400 0x400>;
607 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
608 clock-names = "pclk", "clk32k_in";
611 memory-controller@7000f000 {
612 compatible = "nvidia,tegra30-mc";
613 reg = <0x7000f000 0x010
617 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
621 compatible = "nvidia,tegra30-smmu";
622 reg = <0x7000f010 0x02c
625 nvidia,#asids = <4>; /* # of ASIDs */
626 dma-window = <0 0x40000000>; /* IOVA start & length */
631 compatible = "nvidia,tegra30-ahub";
632 reg = <0x70080000 0x200
634 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
636 <&tegra_car TEGRA30_CLK_APBIF>;
637 clock-names = "d_audio", "apbif";
638 resets = <&tegra_car 106>, /* d_audio */
639 <&tegra_car 107>, /* apbif */
640 <&tegra_car 30>, /* i2s0 */
641 <&tegra_car 11>, /* i2s1 */
642 <&tegra_car 18>, /* i2s2 */
643 <&tegra_car 101>, /* i2s3 */
644 <&tegra_car 102>, /* i2s4 */
645 <&tegra_car 108>, /* dam0 */
646 <&tegra_car 109>, /* dam1 */
647 <&tegra_car 110>, /* dam2 */
648 <&tegra_car 10>; /* spdif */
649 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
650 "i2s3", "i2s4", "dam0", "dam1", "dam2",
652 dmas = <&apbdma 1>, <&apbdma 1>,
653 <&apbdma 2>, <&apbdma 2>,
654 <&apbdma 3>, <&apbdma 3>,
655 <&apbdma 4>, <&apbdma 4>;
656 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
659 #address-cells = <1>;
662 tegra_i2s0: i2s@70080300 {
663 compatible = "nvidia,tegra30-i2s";
664 reg = <0x70080300 0x100>;
665 nvidia,ahub-cif-ids = <4 4>;
666 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
667 resets = <&tegra_car 30>;
672 tegra_i2s1: i2s@70080400 {
673 compatible = "nvidia,tegra30-i2s";
674 reg = <0x70080400 0x100>;
675 nvidia,ahub-cif-ids = <5 5>;
676 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
677 resets = <&tegra_car 11>;
682 tegra_i2s2: i2s@70080500 {
683 compatible = "nvidia,tegra30-i2s";
684 reg = <0x70080500 0x100>;
685 nvidia,ahub-cif-ids = <6 6>;
686 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
687 resets = <&tegra_car 18>;
692 tegra_i2s3: i2s@70080600 {
693 compatible = "nvidia,tegra30-i2s";
694 reg = <0x70080600 0x100>;
695 nvidia,ahub-cif-ids = <7 7>;
696 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
697 resets = <&tegra_car 101>;
702 tegra_i2s4: i2s@70080700 {
703 compatible = "nvidia,tegra30-i2s";
704 reg = <0x70080700 0x100>;
705 nvidia,ahub-cif-ids = <8 8>;
706 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
707 resets = <&tegra_car 102>;
714 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
715 reg = <0x78000000 0x200>;
716 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
718 resets = <&tegra_car 14>;
719 reset-names = "sdhci";
724 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
725 reg = <0x78000200 0x200>;
726 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
728 resets = <&tegra_car 9>;
729 reset-names = "sdhci";
734 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
735 reg = <0x78000400 0x200>;
736 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
738 resets = <&tegra_car 69>;
739 reset-names = "sdhci";
744 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
745 reg = <0x78000600 0x200>;
746 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
748 resets = <&tegra_car 15>;
749 reset-names = "sdhci";
754 compatible = "nvidia,tegra30-ehci", "usb-ehci";
755 reg = <0x7d000000 0x4000>;
756 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&tegra_car TEGRA30_CLK_USBD>;
759 resets = <&tegra_car 22>;
761 nvidia,needs-double-reset;
762 nvidia,phy = <&phy1>;
766 phy1: usb-phy@7d000000 {
767 compatible = "nvidia,tegra30-usb-phy";
768 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
770 clocks = <&tegra_car TEGRA30_CLK_USBD>,
771 <&tegra_car TEGRA30_CLK_PLL_U>,
772 <&tegra_car TEGRA30_CLK_USBD>;
773 clock-names = "reg", "pll_u", "utmi-pads";
774 nvidia,hssync-start-delay = <9>;
775 nvidia,idle-wait-delay = <17>;
776 nvidia,elastic-limit = <16>;
777 nvidia,term-range-adj = <6>;
778 nvidia,xcvr-setup = <51>;
779 nvidia.xcvr-setup-use-fuses;
780 nvidia,xcvr-lsfslew = <1>;
781 nvidia,xcvr-lsrslew = <1>;
782 nvidia,xcvr-hsslew = <32>;
783 nvidia,hssquelch-level = <2>;
784 nvidia,hsdiscon-level = <5>;
789 compatible = "nvidia,tegra30-ehci", "usb-ehci";
790 reg = <0x7d004000 0x4000>;
791 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&tegra_car TEGRA30_CLK_USB2>;
794 resets = <&tegra_car 58>;
796 nvidia,phy = <&phy2>;
800 phy2: usb-phy@7d004000 {
801 compatible = "nvidia,tegra30-usb-phy";
802 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
804 clocks = <&tegra_car TEGRA30_CLK_USB2>,
805 <&tegra_car TEGRA30_CLK_PLL_U>,
806 <&tegra_car TEGRA30_CLK_USBD>;
807 clock-names = "reg", "pll_u", "utmi-pads";
808 nvidia,hssync-start-delay = <9>;
809 nvidia,idle-wait-delay = <17>;
810 nvidia,elastic-limit = <16>;
811 nvidia,term-range-adj = <6>;
812 nvidia,xcvr-setup = <51>;
813 nvidia.xcvr-setup-use-fuses;
814 nvidia,xcvr-lsfslew = <2>;
815 nvidia,xcvr-lsrslew = <2>;
816 nvidia,xcvr-hsslew = <32>;
817 nvidia,hssquelch-level = <2>;
818 nvidia,hsdiscon-level = <5>;
823 compatible = "nvidia,tegra30-ehci", "usb-ehci";
824 reg = <0x7d008000 0x4000>;
825 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&tegra_car TEGRA30_CLK_USB3>;
828 resets = <&tegra_car 59>;
830 nvidia,phy = <&phy3>;
834 phy3: usb-phy@7d008000 {
835 compatible = "nvidia,tegra30-usb-phy";
836 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
838 clocks = <&tegra_car TEGRA30_CLK_USB3>,
839 <&tegra_car TEGRA30_CLK_PLL_U>,
840 <&tegra_car TEGRA30_CLK_USBD>;
841 clock-names = "reg", "pll_u", "utmi-pads";
842 nvidia,hssync-start-delay = <0>;
843 nvidia,idle-wait-delay = <17>;
844 nvidia,elastic-limit = <16>;
845 nvidia,term-range-adj = <6>;
846 nvidia,xcvr-setup = <51>;
847 nvidia.xcvr-setup-use-fuses;
848 nvidia,xcvr-lsfslew = <2>;
849 nvidia,xcvr-lsrslew = <2>;
850 nvidia,xcvr-hsslew = <32>;
851 nvidia,hssquelch-level = <2>;
852 nvidia,hsdiscon-level = <5>;
857 #address-cells = <1>;
862 compatible = "arm,cortex-a9";
868 compatible = "arm,cortex-a9";
874 compatible = "arm,cortex-a9";
880 compatible = "arm,cortex-a9";
886 compatible = "arm,cortex-a9-pmu";
887 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;