1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "skeleton.dtsi"
10 compatible = "nvidia,tegra20";
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra20-host1x", "simple-bus";
15 reg = <0x50000000 0x00024000>;
16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
18 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
19 resets = <&tegra_car 28>;
20 reset-names = "host1x";
25 ranges = <0x54000000 0x54000000 0x04000000>;
28 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&tegra_car TEGRA20_CLK_MPE>;
32 resets = <&tegra_car 60>;
37 compatible = "nvidia,tegra20-vi";
38 reg = <0x54080000 0x00040000>;
39 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
40 clocks = <&tegra_car TEGRA20_CLK_VI>;
41 resets = <&tegra_car 20>;
46 compatible = "nvidia,tegra20-epp";
47 reg = <0x540c0000 0x00040000>;
48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&tegra_car TEGRA20_CLK_EPP>;
50 resets = <&tegra_car 19>;
55 compatible = "nvidia,tegra20-isp";
56 reg = <0x54100000 0x00040000>;
57 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&tegra_car TEGRA20_CLK_ISP>;
59 resets = <&tegra_car 23>;
64 compatible = "nvidia,tegra20-gr2d";
65 reg = <0x54140000 0x00040000>;
66 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
67 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
68 resets = <&tegra_car 21>;
73 compatible = "nvidia,tegra20-gr3d";
74 reg = <0x54180000 0x00040000>;
75 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
76 resets = <&tegra_car 24>;
81 compatible = "nvidia,tegra20-dc";
82 reg = <0x54200000 0x00040000>;
83 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
85 <&tegra_car TEGRA20_CLK_PLL_P>;
86 clock-names = "dc", "parent";
87 resets = <&tegra_car 27>;
98 compatible = "nvidia,tegra20-dc";
99 reg = <0x54240000 0x00040000>;
100 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
102 <&tegra_car TEGRA20_CLK_PLL_P>;
103 clock-names = "dc", "parent";
104 resets = <&tegra_car 26>;
115 compatible = "nvidia,tegra20-hdmi";
116 reg = <0x54280000 0x00040000>;
117 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
119 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
120 clock-names = "hdmi", "parent";
121 resets = <&tegra_car 51>;
122 reset-names = "hdmi";
127 compatible = "nvidia,tegra20-tvo";
128 reg = <0x542c0000 0x00040000>;
129 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&tegra_car TEGRA20_CLK_TVO>;
135 compatible = "nvidia,tegra20-dsi";
136 reg = <0x54300000 0x00040000>;
137 clocks = <&tegra_car TEGRA20_CLK_DSI>;
138 resets = <&tegra_car 48>;
145 compatible = "arm,cortex-a9-twd-timer";
146 interrupt-parent = <&intc>;
147 reg = <0x50040600 0x20>;
148 interrupts = <GIC_PPI 13
149 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
150 clocks = <&tegra_car TEGRA20_CLK_TWD>;
153 intc: interrupt-controller@50041000 {
154 compatible = "arm,cortex-a9-gic";
155 reg = <0x50041000 0x1000
157 interrupt-controller;
158 #interrupt-cells = <3>;
159 interrupt-parent = <&intc>;
162 cache-controller@50043000 {
163 compatible = "arm,pl310-cache";
164 reg = <0x50043000 0x1000>;
165 arm,data-latency = <5 5 2>;
166 arm,tag-latency = <4 4 2>;
171 lic: interrupt-controller@60004000 {
172 compatible = "nvidia,tegra20-ictlr";
173 reg = <0x60004000 0x100>,
177 interrupt-controller;
178 #interrupt-cells = <3>;
179 interrupt-parent = <&intc>;
183 compatible = "nvidia,tegra20-timer";
184 reg = <0x60005000 0x60>;
185 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
192 tegra_car: clock@60006000 {
193 compatible = "nvidia,tegra20-car";
194 reg = <0x60006000 0x1000>;
199 flow-controller@60007000 {
200 compatible = "nvidia,tegra20-flowctrl";
201 reg = <0x60007000 0x1000>;
204 apbdma: dma@6000a000 {
205 compatible = "nvidia,tegra20-apbdma";
206 reg = <0x6000a000 0x1200>;
207 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
224 resets = <&tegra_car 34>;
230 compatible = "nvidia,tegra20-ahb";
231 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
234 gpio: gpio@6000d000 {
235 compatible = "nvidia,tegra20-gpio";
236 reg = <0x6000d000 0x1000>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
246 #interrupt-cells = <2>;
247 interrupt-controller;
249 gpio-ranges = <&pinmux 0 0 224>;
254 compatible = "nvidia,tegra20-apbmisc";
255 reg = <0x70000800 0x64 /* Chip revision */
256 0x70000008 0x04>; /* Strapping options */
259 pinmux: pinmux@70000014 {
260 compatible = "nvidia,tegra20-pinmux";
261 reg = <0x70000014 0x10 /* Tri-state registers */
262 0x70000080 0x20 /* Mux registers */
263 0x700000a0 0x14 /* Pull-up/down registers */
264 0x70000868 0xa8>; /* Pad control registers */
268 compatible = "nvidia,tegra20-das";
269 reg = <0x70000c00 0x80>;
272 tegra_ac97: ac97@70002000 {
273 compatible = "nvidia,tegra20-ac97";
274 reg = <0x70002000 0x200>;
275 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&tegra_car TEGRA20_CLK_AC97>;
277 resets = <&tegra_car 3>;
278 reset-names = "ac97";
279 dmas = <&apbdma 12>, <&apbdma 12>;
280 dma-names = "rx", "tx";
284 tegra_i2s1: i2s@70002800 {
285 compatible = "nvidia,tegra20-i2s";
286 reg = <0x70002800 0x200>;
287 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
289 resets = <&tegra_car 11>;
291 dmas = <&apbdma 2>, <&apbdma 2>;
292 dma-names = "rx", "tx";
296 tegra_i2s2: i2s@70002a00 {
297 compatible = "nvidia,tegra20-i2s";
298 reg = <0x70002a00 0x200>;
299 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
301 resets = <&tegra_car 18>;
303 dmas = <&apbdma 1>, <&apbdma 1>;
304 dma-names = "rx", "tx";
309 * There are two serial driver i.e. 8250 based simple serial
310 * driver and APB DMA based serial driver for higher baudrate
311 * and performace. To enable the 8250 based driver, the compatible
312 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
313 * driver, the compatible is "nvidia,tegra20-hsuart".
315 uarta: serial@70006000 {
316 compatible = "nvidia,tegra20-uart";
317 reg = <0x70006000 0x40>;
319 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
321 resets = <&tegra_car 6>;
322 reset-names = "serial";
323 dmas = <&apbdma 8>, <&apbdma 8>;
324 dma-names = "rx", "tx";
328 uartb: serial@70006040 {
329 compatible = "nvidia,tegra20-uart";
330 reg = <0x70006040 0x40>;
332 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
334 resets = <&tegra_car 7>;
335 reset-names = "serial";
336 dmas = <&apbdma 9>, <&apbdma 9>;
337 dma-names = "rx", "tx";
341 uartc: serial@70006200 {
342 compatible = "nvidia,tegra20-uart";
343 reg = <0x70006200 0x100>;
345 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
347 resets = <&tegra_car 55>;
348 reset-names = "serial";
349 dmas = <&apbdma 10>, <&apbdma 10>;
350 dma-names = "rx", "tx";
354 uartd: serial@70006300 {
355 compatible = "nvidia,tegra20-uart";
356 reg = <0x70006300 0x100>;
358 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
360 resets = <&tegra_car 65>;
361 reset-names = "serial";
362 dmas = <&apbdma 19>, <&apbdma 19>;
363 dma-names = "rx", "tx";
367 uarte: serial@70006400 {
368 compatible = "nvidia,tegra20-uart";
369 reg = <0x70006400 0x100>;
371 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
373 resets = <&tegra_car 66>;
374 reset-names = "serial";
375 dmas = <&apbdma 20>, <&apbdma 20>;
376 dma-names = "rx", "tx";
381 compatible = "nvidia,tegra20-gmi";
382 reg = <0x70009000 0x1000>;
383 #address-cells = <2>;
385 ranges = <0 0 0xd0000000 0xfffffff>;
386 clocks = <&tegra_car TEGRA20_CLK_NOR>;
388 resets = <&tegra_car 42>;
394 compatible = "nvidia,tegra20-pwm";
395 reg = <0x7000a000 0x100>;
397 clocks = <&tegra_car TEGRA20_CLK_PWM>;
398 resets = <&tegra_car 17>;
404 compatible = "nvidia,tegra20-rtc";
405 reg = <0x7000e000 0x100>;
406 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&tegra_car TEGRA20_CLK_RTC>;
411 compatible = "nvidia,tegra20-i2c";
412 reg = <0x7000c000 0x100>;
413 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
416 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
417 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
418 clock-names = "div-clk", "fast-clk";
419 resets = <&tegra_car 12>;
421 dmas = <&apbdma 21>, <&apbdma 21>;
422 dma-names = "rx", "tx";
427 compatible = "nvidia,tegra20-sflash";
428 reg = <0x7000c380 0x80>;
429 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
432 clocks = <&tegra_car TEGRA20_CLK_SPI>;
433 resets = <&tegra_car 43>;
435 dmas = <&apbdma 11>, <&apbdma 11>;
436 dma-names = "rx", "tx";
441 compatible = "nvidia,tegra20-i2c";
442 reg = <0x7000c400 0x100>;
443 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
446 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
447 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
448 clock-names = "div-clk", "fast-clk";
449 resets = <&tegra_car 54>;
451 dmas = <&apbdma 22>, <&apbdma 22>;
452 dma-names = "rx", "tx";
457 compatible = "nvidia,tegra20-i2c";
458 reg = <0x7000c500 0x100>;
459 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
462 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
463 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
464 clock-names = "div-clk", "fast-clk";
465 resets = <&tegra_car 67>;
467 dmas = <&apbdma 23>, <&apbdma 23>;
468 dma-names = "rx", "tx";
473 compatible = "nvidia,tegra20-i2c-dvc";
474 reg = <0x7000d000 0x200>;
475 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
478 clocks = <&tegra_car TEGRA20_CLK_DVC>,
479 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
480 clock-names = "div-clk", "fast-clk";
481 resets = <&tegra_car 47>;
483 dmas = <&apbdma 24>, <&apbdma 24>;
484 dma-names = "rx", "tx";
489 compatible = "nvidia,tegra20-slink";
490 reg = <0x7000d400 0x200>;
491 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <1>;
494 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
495 resets = <&tegra_car 41>;
497 dmas = <&apbdma 15>, <&apbdma 15>;
498 dma-names = "rx", "tx";
503 compatible = "nvidia,tegra20-slink";
504 reg = <0x7000d600 0x200>;
505 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
508 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
509 resets = <&tegra_car 44>;
511 dmas = <&apbdma 16>, <&apbdma 16>;
512 dma-names = "rx", "tx";
517 compatible = "nvidia,tegra20-slink";
518 reg = <0x7000d800 0x200>;
519 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
522 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
523 resets = <&tegra_car 46>;
525 dmas = <&apbdma 17>, <&apbdma 17>;
526 dma-names = "rx", "tx";
531 compatible = "nvidia,tegra20-slink";
532 reg = <0x7000da00 0x200>;
533 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>;
536 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
537 resets = <&tegra_car 68>;
539 dmas = <&apbdma 18>, <&apbdma 18>;
540 dma-names = "rx", "tx";
545 compatible = "nvidia,tegra20-kbc";
546 reg = <0x7000e200 0x100>;
547 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&tegra_car TEGRA20_CLK_KBC>;
549 resets = <&tegra_car 36>;
555 compatible = "nvidia,tegra20-pmc";
556 reg = <0x7000e400 0x400>;
557 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
558 clock-names = "pclk", "clk32k_in";
561 memory-controller@7000f000 {
562 compatible = "nvidia,tegra20-mc";
563 reg = <0x7000f000 0x024
565 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
569 compatible = "nvidia,tegra20-gart";
570 reg = <0x7000f024 0x00000018 /* controller registers */
571 0x58000000 0x02000000>; /* GART aperture */
574 memory-controller@7000f400 {
575 compatible = "nvidia,tegra20-emc";
576 reg = <0x7000f400 0x200>;
577 #address-cells = <1>;
582 compatible = "nvidia,tegra20-efuse";
583 reg = <0x7000f800 0x400>;
584 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
585 clock-names = "fuse";
586 resets = <&tegra_car 39>;
587 reset-names = "fuse";
591 compatible = "nvidia,tegra20-pcie";
593 reg = <0x80003000 0x00000800 /* PADS registers */
594 0x80003800 0x00000200 /* AFI registers */
595 0x90000000 0x10000000>; /* configuration space */
596 reg-names = "pads", "afi", "cs";
597 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
598 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
599 interrupt-names = "intr", "msi";
601 #interrupt-cells = <1>;
602 interrupt-map-mask = <0 0 0 0>;
603 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
605 bus-range = <0x00 0xff>;
606 #address-cells = <3>;
609 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
610 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
611 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
612 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
613 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
615 clocks = <&tegra_car TEGRA20_CLK_PEX>,
616 <&tegra_car TEGRA20_CLK_AFI>,
617 <&tegra_car TEGRA20_CLK_PLL_E>;
618 clock-names = "pex", "afi", "pll_e";
619 resets = <&tegra_car 70>,
622 reset-names = "pex", "afi", "pcie_x";
627 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
628 reg = <0x000800 0 0 0 0>;
629 bus-range = <0x00 0xff>;
632 #address-cells = <3>;
636 nvidia,num-lanes = <2>;
641 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
642 reg = <0x001000 0 0 0 0>;
643 bus-range = <0x00 0xff>;
646 #address-cells = <3>;
650 nvidia,num-lanes = <2>;
655 compatible = "nvidia,tegra20-ehci", "usb-ehci";
656 reg = <0xc5000000 0x4000>;
657 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
659 nvidia,has-legacy-mode;
660 clocks = <&tegra_car TEGRA20_CLK_USBD>;
661 resets = <&tegra_car 22>;
663 nvidia,needs-double-reset;
664 nvidia,phy = <&phy1>;
668 phy1: usb-phy@c5000000 {
669 compatible = "nvidia,tegra20-usb-phy";
670 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
672 clocks = <&tegra_car TEGRA20_CLK_USBD>,
673 <&tegra_car TEGRA20_CLK_PLL_U>,
674 <&tegra_car TEGRA20_CLK_CLK_M>,
675 <&tegra_car TEGRA20_CLK_USBD>;
676 clock-names = "reg", "pll_u", "timer", "utmi-pads";
677 resets = <&tegra_car 22>, <&tegra_car 22>;
678 reset-names = "usb", "utmi-pads";
679 nvidia,has-legacy-mode;
680 nvidia,hssync-start-delay = <9>;
681 nvidia,idle-wait-delay = <17>;
682 nvidia,elastic-limit = <16>;
683 nvidia,term-range-adj = <6>;
684 nvidia,xcvr-setup = <9>;
685 nvidia,xcvr-lsfslew = <1>;
686 nvidia,xcvr-lsrslew = <1>;
687 nvidia,has-utmi-pad-registers;
692 compatible = "nvidia,tegra20-ehci", "usb-ehci";
693 reg = <0xc5004000 0x4000>;
694 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&tegra_car TEGRA20_CLK_USB2>;
697 resets = <&tegra_car 58>;
699 nvidia,phy = <&phy2>;
703 phy2: usb-phy@c5004000 {
704 compatible = "nvidia,tegra20-usb-phy";
705 reg = <0xc5004000 0x4000>;
707 clocks = <&tegra_car TEGRA20_CLK_USB2>,
708 <&tegra_car TEGRA20_CLK_PLL_U>,
709 <&tegra_car TEGRA20_CLK_CDEV2>;
710 clock-names = "reg", "pll_u", "ulpi-link";
711 resets = <&tegra_car 58>, <&tegra_car 22>;
712 reset-names = "usb", "utmi-pads";
717 compatible = "nvidia,tegra20-ehci", "usb-ehci";
718 reg = <0xc5008000 0x4000>;
719 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&tegra_car TEGRA20_CLK_USB3>;
722 resets = <&tegra_car 59>;
724 nvidia,phy = <&phy3>;
728 phy3: usb-phy@c5008000 {
729 compatible = "nvidia,tegra20-usb-phy";
730 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
732 clocks = <&tegra_car TEGRA20_CLK_USB3>,
733 <&tegra_car TEGRA20_CLK_PLL_U>,
734 <&tegra_car TEGRA20_CLK_CLK_M>,
735 <&tegra_car TEGRA20_CLK_USBD>;
736 clock-names = "reg", "pll_u", "timer", "utmi-pads";
737 resets = <&tegra_car 59>, <&tegra_car 22>;
738 reset-names = "usb", "utmi-pads";
739 nvidia,hssync-start-delay = <9>;
740 nvidia,idle-wait-delay = <17>;
741 nvidia,elastic-limit = <16>;
742 nvidia,term-range-adj = <6>;
743 nvidia,xcvr-setup = <9>;
744 nvidia,xcvr-lsfslew = <2>;
745 nvidia,xcvr-lsrslew = <2>;
750 compatible = "nvidia,tegra20-sdhci";
751 reg = <0xc8000000 0x200>;
752 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
754 resets = <&tegra_car 14>;
755 reset-names = "sdhci";
760 compatible = "nvidia,tegra20-sdhci";
761 reg = <0xc8000200 0x200>;
762 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
764 resets = <&tegra_car 9>;
765 reset-names = "sdhci";
770 compatible = "nvidia,tegra20-sdhci";
771 reg = <0xc8000400 0x200>;
772 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
774 resets = <&tegra_car 69>;
775 reset-names = "sdhci";
780 compatible = "nvidia,tegra20-sdhci";
781 reg = <0xc8000600 0x200>;
782 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
784 resets = <&tegra_car 15>;
785 reset-names = "sdhci";
790 #address-cells = <1>;
795 compatible = "arm,cortex-a9";
801 compatible = "arm,cortex-a9";
807 compatible = "arm,cortex-a9-pmu";
808 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;