arch/arm/boot/dts/tegra20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra20-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra20-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8
   9 / {
  10         compatible = "nvidia,tegra20";
  11         interrupt-parent = <&lic>;
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         memory@0 {
  16                 device_type = "memory";
  17                 reg = <0 0>;
  18         };
  19
  20         sram@40000000 {
  21                 compatible = "mmio-sram";
  22                 reg = <0x40000000 0x40000>;
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 ranges = <0 0x40000000 0x40000>;
  26
  27                 vde_pool: sram@400 {
  28                         reg = <0x400 0x3fc00>;
  29                         pool;
  30                 };
  31         };
  32
  33         host1x@50000000 {
  34                 compatible = "nvidia,tegra20-host1x";
  35                 reg = <0x50000000 0x00024000>;
  36                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  37                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  38                 interrupt-names = "syncpt", "host1x";
  39                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  40                 clock-names = "host1x";
  41                 resets = <&tegra_car 28>;
  42                 reset-names = "host1x";
  43
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46
  47                 ranges = <0x54000000 0x54000000 0x04000000>;
  48
  49                 mpe@54040000 {
  50                         compatible = "nvidia,tegra20-mpe";
  51                         reg = <0x54040000 0x00040000>;
  52                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  53                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  54                         resets = <&tegra_car 60>;
  55                         reset-names = "mpe";
  56                 };
  57
  58                 vi@54080000 {
  59                         compatible = "nvidia,tegra20-vi";
  60                         reg = <0x54080000 0x00040000>;
  61                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  62                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  63                         resets = <&tegra_car 20>;
  64                         reset-names = "vi";
  65                 };
  66
  67                 epp@540c0000 {
  68                         compatible = "nvidia,tegra20-epp";
  69                         reg = <0x540c0000 0x00040000>;
  70                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  71                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  72                         resets = <&tegra_car 19>;
  73                         reset-names = "epp";
  74                 };
  75
  76                 isp@54100000 {
  77                         compatible = "nvidia,tegra20-isp";
  78                         reg = <0x54100000 0x00040000>;
  79                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  80                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  81                         resets = <&tegra_car 23>;
  82                         reset-names = "isp";
  83                 };
  84
  85                 gr2d@54140000 {
  86                         compatible = "nvidia,tegra20-gr2d";
  87                         reg = <0x54140000 0x00040000>;
  88                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  89                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  90                         resets = <&tegra_car 21>;
  91                         reset-names = "2d";
  92                 };
  93
  94                 gr3d@54180000 {
  95                         compatible = "nvidia,tegra20-gr3d";
  96                         reg = <0x54180000 0x00040000>;
  97                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  98                         resets = <&tegra_car 24>;
  99                         reset-names = "3d";
 100                 };
 101
 102                 dc@54200000 {
 103                         compatible = "nvidia,tegra20-dc";
 104                         reg = <0x54200000 0x00040000>;
 105                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 106                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 107                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 108                         clock-names = "dc", "parent";
 109                         resets = <&tegra_car 27>;
 110                         reset-names = "dc";
 111
 112                         nvidia,head = <0>;
 113
 114                         interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
 115                                         <&mc TEGRA20_MC_DISPLAY0B &emc>,
 116                                         <&mc TEGRA20_MC_DISPLAY1B &emc>,
 117                                         <&mc TEGRA20_MC_DISPLAY0C &emc>,
 118                                         <&mc TEGRA20_MC_DISPLAYHC &emc>;
 119                         interconnect-names = "wina",
 120                                              "winb",
 121                                              "winb-vfilter",
 122                                              "winc",
 123                                              "cursor";
 124
 125                         rgb {
 126                                 status = "disabled";
 127                         };
 128                 };
 129
 130                 dc@54240000 {
 131                         compatible = "nvidia,tegra20-dc";
 132                         reg = <0x54240000 0x00040000>;
 133                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 134                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 135                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 136                         clock-names = "dc", "parent";
 137                         resets = <&tegra_car 26>;
 138                         reset-names = "dc";
 139
 140                         nvidia,head = <1>;
 141
 142                         interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
 143                                         <&mc TEGRA20_MC_DISPLAY0BB &emc>,
 144                                         <&mc TEGRA20_MC_DISPLAY1BB &emc>,
 145                                         <&mc TEGRA20_MC_DISPLAY0CB &emc>,
 146                                         <&mc TEGRA20_MC_DISPLAYHCB &emc>;
 147                         interconnect-names = "wina",
 148                                              "winb",
 149                                              "winb-vfilter",
 150                                              "winc",
 151                                              "cursor";
 152
 153                         rgb {
 154                                 status = "disabled";
 155                         };
 156                 };
 157
 158                 hdmi@54280000 {
 159                         compatible = "nvidia,tegra20-hdmi";
 160                         reg = <0x54280000 0x00040000>;
 161                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 162                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 163                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 164                         clock-names = "hdmi", "parent";
 165                         resets = <&tegra_car 51>;
 166                         reset-names = "hdmi";
 167                         status = "disabled";
 168                 };
 169
 170                 tvo@542c0000 {
 171                         compatible = "nvidia,tegra20-tvo";
 172                         reg = <0x542c0000 0x00040000>;
 173                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 174                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 175                         status = "disabled";
 176                 };
 177
 178                 dsi@54300000 {
 179                         compatible = "nvidia,tegra20-dsi";
 180                         reg = <0x54300000 0x00040000>;
 181                         clocks = <&tegra_car TEGRA20_CLK_DSI>,
 182                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 183                         clock-names = "dsi", "parent";
 184                         resets = <&tegra_car 48>;
 185                         reset-names = "dsi";
 186                         status = "disabled";
 187                 };
 188         };
 189
 190         timer@50040600 {
 191                 compatible = "arm,cortex-a9-twd-timer";
 192                 interrupt-parent = <&intc>;
 193                 reg = <0x50040600 0x20>;
 194                 interrupts = <GIC_PPI 13
 195                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 196                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 197         };
 198
 199         intc: interrupt-controller@50041000 {
 200                 compatible = "arm,cortex-a9-gic";
 201                 reg = <0x50041000 0x1000>,
 202                       <0x50040100 0x0100>;
 203                 interrupt-controller;
 204                 #interrupt-cells = <3>;
 205                 interrupt-parent = <&intc>;
 206         };
 207
 208         cache-controller@50043000 {
 209                 compatible = "arm,pl310-cache";
 210                 reg = <0x50043000 0x1000>;
 211                 arm,data-latency = <5 5 2>;
 212                 arm,tag-latency = <4 4 2>;
 213                 cache-unified;
 214                 cache-level = <2>;
 215         };
 216
 217         lic: interrupt-controller@60004000 {
 218                 compatible = "nvidia,tegra20-ictlr";
 219                 reg = <0x60004000 0x100>,
 220                       <0x60004100 0x50>,
 221                       <0x60004200 0x50>,
 222                       <0x60004300 0x50>;
 223                 interrupt-controller;
 224                 #interrupt-cells = <3>;
 225                 interrupt-parent = <&intc>;
 226         };
 227
 228         timer@60005000 {
 229                 compatible = "nvidia,tegra20-timer";
 230                 reg = <0x60005000 0x60>;
 231                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 235                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 236         };
 237
 238         tegra_car: clock@60006000 {
 239                 compatible = "nvidia,tegra20-car";
 240                 reg = <0x60006000 0x1000>;
 241                 #clock-cells = <1>;
 242                 #reset-cells = <1>;
 243         };
 244
 245         flow-controller@60007000 {
 246                 compatible = "nvidia,tegra20-flowctrl";
 247                 reg = <0x60007000 0x1000>;
 248         };
 249
 250         apbdma: dma@6000a000 {
 251                 compatible = "nvidia,tegra20-apbdma";
 252                 reg = <0x6000a000 0x1200>;
 253                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 270                 resets = <&tegra_car 34>;
 271                 reset-names = "dma";
 272                 #dma-cells = <1>;
 273         };
 274
 275         ahb@6000c000 {
 276                 compatible = "nvidia,tegra20-ahb";
 277                 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
 278         };
 279
 280         gpio: gpio@6000d000 {
 281                 compatible = "nvidia,tegra20-gpio";
 282                 reg = <0x6000d000 0x1000>;
 283                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 290                 #gpio-cells = <2>;
 291                 gpio-controller;
 292                 #interrupt-cells = <2>;
 293                 interrupt-controller;
 294                 /*
 295                 gpio-ranges = <&pinmux 0 0 224>;
 296                 */
 297         };
 298
 299         vde@6001a000 {
 300                 compatible = "nvidia,tegra20-vde";
 301                 reg = <0x6001a000 0x1000>, /* Syntax Engine */
 302                       <0x6001b000 0x1000>, /* Video Bitstream Engine */
 303                       <0x6001c000  0x100>, /* Macroblock Engine */
 304                       <0x6001c200  0x100>, /* Post-processing Engine */
 305                       <0x6001c400  0x100>, /* Motion Compensation Engine */
 306                       <0x6001c600  0x100>, /* Transform Engine */
 307                       <0x6001c800  0x100>, /* Pixel prediction block */
 308                       <0x6001ca00  0x100>, /* Video DMA */
 309                       <0x6001d800  0x300>; /* Video frame controls */
 310                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 311                             "tfe", "ppb", "vdma", "frameid";
 312                 iram = <&vde_pool>; /* IRAM region */
 313                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 314                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 315                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 316                 interrupt-names = "sync-token", "bsev", "sxe";
 317                 clocks = <&tegra_car TEGRA20_CLK_VDE>;
 318                 reset-names = "vde", "mc";
 319                 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
 320         };
 321
 322         apbmisc@70000800 {
 323                 compatible = "nvidia,tegra20-apbmisc";
 324                 reg = <0x70000800 0x64>, /* Chip revision */
 325                       <0x70000008 0x04>; /* Strapping options */
 326         };
 327
 328         pinmux: pinmux@70000014 {
 329                 compatible = "nvidia,tegra20-pinmux";
 330                 reg = <0x70000014 0x10>, /* Tri-state registers */
 331                       <0x70000080 0x20>, /* Mux registers */
 332                       <0x700000a0 0x14>, /* Pull-up/down registers */
 333                       <0x70000868 0xa8>; /* Pad control registers */
 334         };
 335
 336         das@70000c00 {
 337                 compatible = "nvidia,tegra20-das";
 338                 reg = <0x70000c00 0x80>;
 339         };
 340
 341         tegra_ac97: ac97@70002000 {
 342                 compatible = "nvidia,tegra20-ac97";
 343                 reg = <0x70002000 0x200>;
 344                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 346                 resets = <&tegra_car 3>;
 347                 reset-names = "ac97";
 348                 dmas = <&apbdma 12>, <&apbdma 12>;
 349                 dma-names = "rx", "tx";
 350                 status = "disabled";
 351         };
 352
 353         tegra_i2s1: i2s@70002800 {
 354                 compatible = "nvidia,tegra20-i2s";
 355                 reg = <0x70002800 0x200>;
 356                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 357                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 358                 resets = <&tegra_car 11>;
 359                 reset-names = "i2s";
 360                 dmas = <&apbdma 2>, <&apbdma 2>;
 361                 dma-names = "rx", "tx";
 362                 status = "disabled";
 363         };
 364
 365         tegra_i2s2: i2s@70002a00 {
 366                 compatible = "nvidia,tegra20-i2s";
 367                 reg = <0x70002a00 0x200>;
 368                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 370                 resets = <&tegra_car 18>;
 371                 reset-names = "i2s";
 372                 dmas = <&apbdma 1>, <&apbdma 1>;
 373                 dma-names = "rx", "tx";
 374                 status = "disabled";
 375         };
 376
 377         /*
 378          * There are two serial driver i.e. 8250 based simple serial
 379          * driver and APB DMA based serial driver for higher baudrate
 380          * and performace. To enable the 8250 based driver, the compatible
 381          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 382          * driver, the compatible is "nvidia,tegra20-hsuart".
 383          */
 384         uarta: serial@70006000 {
 385                 compatible = "nvidia,tegra20-uart";
 386                 reg = <0x70006000 0x40>;
 387                 reg-shift = <2>;
 388                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 390                 resets = <&tegra_car 6>;
 391                 reset-names = "serial";
 392                 dmas = <&apbdma 8>, <&apbdma 8>;
 393                 dma-names = "rx", "tx";
 394                 status = "disabled";
 395         };
 396
 397         uartb: serial@70006040 {
 398                 compatible = "nvidia,tegra20-uart";
 399                 reg = <0x70006040 0x40>;
 400                 reg-shift = <2>;
 401                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 403                 resets = <&tegra_car 7>;
 404                 reset-names = "serial";
 405                 dmas = <&apbdma 9>, <&apbdma 9>;
 406                 dma-names = "rx", "tx";
 407                 status = "disabled";
 408         };
 409
 410         uartc: serial@70006200 {
 411                 compatible = "nvidia,tegra20-uart";
 412                 reg = <0x70006200 0x100>;
 413                 reg-shift = <2>;
 414                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 416                 resets = <&tegra_car 55>;
 417                 reset-names = "serial";
 418                 dmas = <&apbdma 10>, <&apbdma 10>;
 419                 dma-names = "rx", "tx";
 420                 status = "disabled";
 421         };
 422
 423         uartd: serial@70006300 {
 424                 compatible = "nvidia,tegra20-uart";
 425                 reg = <0x70006300 0x100>;
 426                 reg-shift = <2>;
 427                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 429                 resets = <&tegra_car 65>;
 430                 reset-names = "serial";
 431                 dmas = <&apbdma 19>, <&apbdma 19>;
 432                 dma-names = "rx", "tx";
 433                 status = "disabled";
 434         };
 435
 436         uarte: serial@70006400 {
 437                 compatible = "nvidia,tegra20-uart";
 438                 reg = <0x70006400 0x100>;
 439                 reg-shift = <2>;
 440                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 442                 resets = <&tegra_car 66>;
 443                 reset-names = "serial";
 444                 dmas = <&apbdma 20>, <&apbdma 20>;
 445                 dma-names = "rx", "tx";
 446                 status = "disabled";
 447         };
 448
 449         nand-controller@70008000 {
 450                 compatible = "nvidia,tegra20-nand";
 451                 reg = <0x70008000 0x100>;
 452                 #address-cells = <1>;
 453                 #size-cells = <0>;
 454                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 456                 clock-names = "nand";
 457                 resets = <&tegra_car 13>;
 458                 reset-names = "nand";
 459                 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 460                 assigned-clock-rates = <150000000>;
 461                 status = "disabled";
 462         };
 463
 464         gmi@70009000 {
 465                 compatible = "nvidia,tegra20-gmi";
 466                 reg = <0x70009000 0x1000>;
 467                 #address-cells = <2>;
 468                 #size-cells = <1>;
 469                 ranges = <0 0 0xd0000000 0xfffffff>;
 470                 clocks = <&tegra_car TEGRA20_CLK_NOR>;
 471                 clock-names = "gmi";
 472                 resets = <&tegra_car 42>;
 473                 reset-names = "gmi";
 474                 status = "disabled";
 475         };
 476
 477         pwm: pwm@7000a000 {
 478                 compatible = "nvidia,tegra20-pwm";
 479                 reg = <0x7000a000 0x100>;
 480                 #pwm-cells = <2>;
 481                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 482                 resets = <&tegra_car 17>;
 483                 reset-names = "pwm";
 484                 status = "disabled";
 485         };
 486
 487         rtc@7000e000 {
 488                 compatible = "nvidia,tegra20-rtc";
 489                 reg = <0x7000e000 0x100>;
 490                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 491                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 492         };
 493
 494         i2c@7000c000 {
 495                 compatible = "nvidia,tegra20-i2c";
 496                 reg = <0x7000c000 0x100>;
 497                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 501                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 502                 clock-names = "div-clk", "fast-clk";
 503                 resets = <&tegra_car 12>;
 504                 reset-names = "i2c";
 505                 dmas = <&apbdma 21>, <&apbdma 21>;
 506                 dma-names = "rx", "tx";
 507                 status = "disabled";
 508         };
 509
 510         spi@7000c380 {
 511                 compatible = "nvidia,tegra20-sflash";
 512                 reg = <0x7000c380 0x80>;
 513                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 517                 resets = <&tegra_car 43>;
 518                 reset-names = "spi";
 519                 dmas = <&apbdma 11>, <&apbdma 11>;
 520                 dma-names = "rx", "tx";
 521                 status = "disabled";
 522         };
 523
 524         i2c@7000c400 {
 525                 compatible = "nvidia,tegra20-i2c";
 526                 reg = <0x7000c400 0x100>;
 527                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 528                 #address-cells = <1>;
 529                 #size-cells = <0>;
 530                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 531                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 532                 clock-names = "div-clk", "fast-clk";
 533                 resets = <&tegra_car 54>;
 534                 reset-names = "i2c";
 535                 dmas = <&apbdma 22>, <&apbdma 22>;
 536                 dma-names = "rx", "tx";
 537                 status = "disabled";
 538         };
 539
 540         i2c@7000c500 {
 541                 compatible = "nvidia,tegra20-i2c";
 542                 reg = <0x7000c500 0x100>;
 543                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 547                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 548                 clock-names = "div-clk", "fast-clk";
 549                 resets = <&tegra_car 67>;
 550                 reset-names = "i2c";
 551                 dmas = <&apbdma 23>, <&apbdma 23>;
 552                 dma-names = "rx", "tx";
 553                 status = "disabled";
 554         };
 555
 556         i2c@7000d000 {
 557                 compatible = "nvidia,tegra20-i2c-dvc";
 558                 reg = <0x7000d000 0x200>;
 559                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 563                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 564                 clock-names = "div-clk", "fast-clk";
 565                 resets = <&tegra_car 47>;
 566                 reset-names = "i2c";
 567                 dmas = <&apbdma 24>, <&apbdma 24>;
 568                 dma-names = "rx", "tx";
 569                 status = "disabled";
 570         };
 571
 572         spi@7000d400 {
 573                 compatible = "nvidia,tegra20-slink";
 574                 reg = <0x7000d400 0x200>;
 575                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 579                 resets = <&tegra_car 41>;
 580                 reset-names = "spi";
 581                 dmas = <&apbdma 15>, <&apbdma 15>;
 582                 dma-names = "rx", "tx";
 583                 status = "disabled";
 584         };
 585
 586         spi@7000d600 {
 587                 compatible = "nvidia,tegra20-slink";
 588                 reg = <0x7000d600 0x200>;
 589                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 593                 resets = <&tegra_car 44>;
 594                 reset-names = "spi";
 595                 dmas = <&apbdma 16>, <&apbdma 16>;
 596                 dma-names = "rx", "tx";
 597                 status = "disabled";
 598         };
 599
 600         spi@7000d800 {
 601                 compatible = "nvidia,tegra20-slink";
 602                 reg = <0x7000d800 0x200>;
 603                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 607                 resets = <&tegra_car 46>;
 608                 reset-names = "spi";
 609                 dmas = <&apbdma 17>, <&apbdma 17>;
 610                 dma-names = "rx", "tx";
 611                 status = "disabled";
 612         };
 613
 614         spi@7000da00 {
 615                 compatible = "nvidia,tegra20-slink";
 616                 reg = <0x7000da00 0x200>;
 617                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 621                 resets = <&tegra_car 68>;
 622                 reset-names = "spi";
 623                 dmas = <&apbdma 18>, <&apbdma 18>;
 624                 dma-names = "rx", "tx";
 625                 status = "disabled";
 626         };
 627
 628         kbc@7000e200 {
 629                 compatible = "nvidia,tegra20-kbc";
 630                 reg = <0x7000e200 0x100>;
 631                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 632                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 633                 resets = <&tegra_car 36>;
 634                 reset-names = "kbc";
 635                 status = "disabled";
 636         };
 637
 638         tegra_pmc: pmc@7000e400 {
 639                 compatible = "nvidia,tegra20-pmc";
 640                 reg = <0x7000e400 0x400>;
 641                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 642                 clock-names = "pclk", "clk32k_in";
 643                 #clock-cells = <1>;
 644         };
 645
 646         mc: memory-controller@7000f000 {
 647                 compatible = "nvidia,tegra20-mc-gart";
 648                 reg = <0x7000f000 0x00000400>, /* controller registers */
 649                       <0x58000000 0x02000000>; /* GART aperture */
 650                 clocks = <&tegra_car TEGRA20_CLK_MC>;
 651                 clock-names = "mc";
 652                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 653                 #reset-cells = <1>;
 654                 #iommu-cells = <0>;
 655                 #interconnect-cells = <1>;
 656         };
 657
 658         emc: memory-controller@7000f400 {
 659                 compatible = "nvidia,tegra20-emc";
 660                 reg = <0x7000f400 0x400>;
 661                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&tegra_car TEGRA20_CLK_EMC>;
 663                 #address-cells = <1>;
 664                 #size-cells = <0>;
 665                 #interconnect-cells = <0>;
 666
 667                 nvidia,memory-controller = <&mc>;
 668         };
 669
 670         fuse@7000f800 {
 671                 compatible = "nvidia,tegra20-efuse";
 672                 reg = <0x7000f800 0x400>;
 673                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 674                 clock-names = "fuse";
 675                 resets = <&tegra_car 39>;
 676                 reset-names = "fuse";
 677         };
 678
 679         pcie@80003000 {
 680                 compatible = "nvidia,tegra20-pcie";
 681                 device_type = "pci";
 682                 reg = <0x80003000 0x00000800>, /* PADS registers */
 683                       <0x80003800 0x00000200>, /* AFI registers */
 684                       <0x90000000 0x10000000>; /* configuration space */
 685                 reg-names = "pads", "afi", "cs";
 686                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 687                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 688                 interrupt-names = "intr", "msi";
 689
 690                 #interrupt-cells = <1>;
 691                 interrupt-map-mask = <0 0 0 0>;
 692                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 693
 694                 bus-range = <0x00 0xff>;
 695                 #address-cells = <3>;
 696                 #size-cells = <2>;
 697
 698                 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
 699                          <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
 700                          <0x01000000 0 0          0x82000000 0 0x00010000>, /* downstream I/O */
 701                          <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
 702                          <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 703
 704                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 705                          <&tegra_car TEGRA20_CLK_AFI>,
 706                          <&tegra_car TEGRA20_CLK_PLL_E>;
 707                 clock-names = "pex", "afi", "pll_e";
 708                 resets = <&tegra_car 70>,
 709                          <&tegra_car 72>,
 710                          <&tegra_car 74>;
 711                 reset-names = "pex", "afi", "pcie_x";
 712                 status = "disabled";
 713
 714                 pci@1,0 {
 715                         device_type = "pci";
 716                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 717                         reg = <0x000800 0 0 0 0>;
 718                         bus-range = <0x00 0xff>;
 719                         status = "disabled";
 720
 721                         #address-cells = <3>;
 722                         #size-cells = <2>;
 723                         ranges;
 724
 725                         nvidia,num-lanes = <2>;
 726                 };
 727
 728                 pci@2,0 {
 729                         device_type = "pci";
 730                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 731                         reg = <0x001000 0 0 0 0>;
 732                         bus-range = <0x00 0xff>;
 733                         status = "disabled";
 734
 735                         #address-cells = <3>;
 736                         #size-cells = <2>;
 737                         ranges;
 738
 739                         nvidia,num-lanes = <2>;
 740                 };
 741         };
 742
 743         usb@c5000000 {
 744                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 745                 reg = <0xc5000000 0x4000>;
 746                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 747                 phy_type = "utmi";
 748                 nvidia,has-legacy-mode;
 749                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 750                 resets = <&tegra_car 22>;
 751                 reset-names = "usb";
 752                 nvidia,needs-double-reset;
 753                 nvidia,phy = <&phy1>;
 754                 status = "disabled";
 755         };
 756
 757         phy1: usb-phy@c5000000 {
 758                 compatible = "nvidia,tegra20-usb-phy";
 759                 reg = <0xc5000000 0x4000>,
 760                       <0xc5000000 0x4000>;
 761                 phy_type = "utmi";
 762                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 763                          <&tegra_car TEGRA20_CLK_PLL_U>,
 764                          <&tegra_car TEGRA20_CLK_CLK_M>,
 765                          <&tegra_car TEGRA20_CLK_USBD>;
 766                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 767                 resets = <&tegra_car 22>, <&tegra_car 22>;
 768                 reset-names = "usb", "utmi-pads";
 769                 #phy-cells = <0>;
 770                 nvidia,has-legacy-mode;
 771                 nvidia,hssync-start-delay = <9>;
 772                 nvidia,idle-wait-delay = <17>;
 773                 nvidia,elastic-limit = <16>;
 774                 nvidia,term-range-adj = <6>;
 775                 nvidia,xcvr-setup = <9>;
 776                 nvidia,xcvr-lsfslew = <1>;
 777                 nvidia,xcvr-lsrslew = <1>;
 778                 nvidia,has-utmi-pad-registers;
 779                 status = "disabled";
 780         };
 781
 782         usb@c5004000 {
 783                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 784                 reg = <0xc5004000 0x4000>;
 785                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 786                 phy_type = "ulpi";
 787                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 788                 resets = <&tegra_car 58>;
 789                 reset-names = "usb";
 790                 nvidia,phy = <&phy2>;
 791                 status = "disabled";
 792         };
 793
 794         phy2: usb-phy@c5004000 {
 795                 compatible = "nvidia,tegra20-usb-phy";
 796                 reg = <0xc5004000 0x4000>;
 797                 phy_type = "ulpi";
 798                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 799                          <&tegra_car TEGRA20_CLK_PLL_U>,
 800                          <&tegra_car TEGRA20_CLK_CDEV2>;
 801                 clock-names = "reg", "pll_u", "ulpi-link";
 802                 resets = <&tegra_car 58>, <&tegra_car 22>;
 803                 reset-names = "usb", "utmi-pads";
 804                 #phy-cells = <0>;
 805                 status = "disabled";
 806         };
 807
 808         usb@c5008000 {
 809                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 810                 reg = <0xc5008000 0x4000>;
 811                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 812                 phy_type = "utmi";
 813                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 814                 resets = <&tegra_car 59>;
 815                 reset-names = "usb";
 816                 nvidia,phy = <&phy3>;
 817                 status = "disabled";
 818         };
 819
 820         phy3: usb-phy@c5008000 {
 821                 compatible = "nvidia,tegra20-usb-phy";
 822                 reg = <0xc5008000 0x4000>,
 823                       <0xc5000000 0x4000>;
 824                 phy_type = "utmi";
 825                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 826                          <&tegra_car TEGRA20_CLK_PLL_U>,
 827                          <&tegra_car TEGRA20_CLK_CLK_M>,
 828                          <&tegra_car TEGRA20_CLK_USBD>;
 829                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 830                 resets = <&tegra_car 59>, <&tegra_car 22>;
 831                 reset-names = "usb", "utmi-pads";
 832                 #phy-cells = <0>;
 833                 nvidia,hssync-start-delay = <9>;
 834                 nvidia,idle-wait-delay = <17>;
 835                 nvidia,elastic-limit = <16>;
 836                 nvidia,term-range-adj = <6>;
 837                 nvidia,xcvr-setup = <9>;
 838                 nvidia,xcvr-lsfslew = <2>;
 839                 nvidia,xcvr-lsrslew = <2>;
 840                 status = "disabled";
 841         };
 842
 843         mmc@c8000000 {
 844                 compatible = "nvidia,tegra20-sdhci";
 845                 reg = <0xc8000000 0x200>;
 846                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 847                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 848                 clock-names = "sdhci";
 849                 resets = <&tegra_car 14>;
 850                 reset-names = "sdhci";
 851                 status = "disabled";
 852         };
 853
 854         mmc@c8000200 {
 855                 compatible = "nvidia,tegra20-sdhci";
 856                 reg = <0xc8000200 0x200>;
 857                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 859                 clock-names = "sdhci";
 860                 resets = <&tegra_car 9>;
 861                 reset-names = "sdhci";
 862                 status = "disabled";
 863         };
 864
 865         mmc@c8000400 {
 866                 compatible = "nvidia,tegra20-sdhci";
 867                 reg = <0xc8000400 0x200>;
 868                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 869                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 870                 clock-names = "sdhci";
 871                 resets = <&tegra_car 69>;
 872                 reset-names = "sdhci";
 873                 status = "disabled";
 874         };
 875
 876         mmc@c8000600 {
 877                 compatible = "nvidia,tegra20-sdhci";
 878                 reg = <0xc8000600 0x200>;
 879                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 880                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 881                 clock-names = "sdhci";
 882                 resets = <&tegra_car 15>;
 883                 reset-names = "sdhci";
 884                 status = "disabled";
 885         };
 886
 887         cpus {
 888                 #address-cells = <1>;
 889                 #size-cells = <0>;
 890
 891                 cpu@0 {
 892                         device_type = "cpu";
 893                         compatible = "arm,cortex-a9";
 894                         reg = <0>;
 895                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
 896                 };
 897
 898                 cpu@1 {
 899                         device_type = "cpu";
 900                         compatible = "arm,cortex-a9";
 901                         reg = <1>;
 902                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
 903                 };
 904         };
 905
 906         pmu {
 907                 compatible = "arm,cortex-a9-pmu";
 908                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 909                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 910                 interrupt-affinity = <&{/cpus/cpu@0}>,
 911                                      <&{/cpus/cpu@1}>;
 912         };
 913 };