1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi"
5 * Toradex Colibri T20 Module Device Tree
6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
8 * Colibri T20 512MB IT V1.2A
13 * Set memory to 256 MB to be safe as this could be used on
14 * 256 or 512 MB module. It is expected from bootloader
15 * to fix this up for 512 MB version.
17 reg = <0x00000000 0x10000000>;
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
25 pll-supply = <®_1v8_avdd_hdmi_pll>;
26 vdd-supply = <®_3v3_avdd_hdmi>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&state_default>;
34 state_default: pinmux {
35 /* Analogue Audio AC97 to WM9712 (On-module) */
37 nvidia,pins = "cdev1";
38 nvidia,function = "plla_out";
39 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
40 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 nvidia,function = "dap3";
45 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
46 nvidia,tristate = <TEGRA_PIN_DISABLE>;
50 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
51 * (All on-module), SODIMM Pin 45 Wakeup
55 nvidia,function = "rsvd2";
56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
61 * Buffer Enables for nPWE and RDnWR (On-module,
62 * see GPIO hogging further down below)
66 nvidia,function = "rsvd4";
67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
73 * SYS_CLK_REQ (All on-module)
77 nvidia,function = "pwr_on";
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
82 * Colibri Address/Data Bus (GMI)
83 * Note: spid and spie optionally used for SPI1
86 nvidia,pins = "atc", "atd", "ate", "dap1",
87 "dap2", "dap4", "gmd", "gpu",
88 "irrx", "irtx", "spia", "spib",
89 "spic", "spid", "spie", "uca",
91 nvidia,function = "gmi";
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_ENABLE>;
95 /* Further pins may be used as GPIOs */
97 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
98 nvidia,function = "hdmi";
99 nvidia,tristate = <TEGRA_PIN_ENABLE>;
102 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
103 nvidia,function = "rsvd4";
104 nvidia,tristate = <TEGRA_PIN_ENABLE>;
110 nvidia,function = "rsvd1";
111 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
112 nvidia,tristate = <TEGRA_PIN_ENABLE>;
115 /* Colibri Backlight PWM<A>, PWM<B> */
118 nvidia,function = "pwm";
119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
125 nvidia,function = "i2c2";
126 nvidia,pull = <TEGRA_PIN_PULL_UP>;
127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
132 * Note: dtf optionally used for I2C3
135 nvidia,pins = "dtf", "spdi";
136 nvidia,function = "rsvd2";
137 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
138 nvidia,tristate = <TEGRA_PIN_ENABLE>;
142 * Colibri Ethernet (On-module)
143 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
146 nvidia,pins = "uaa", "uab", "uda";
147 nvidia,function = "ulpi";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 nvidia,pins = "cdev2";
153 nvidia,function = "pllp_out4";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
158 /* Colibri HOTPLUG_DETECT (HDMI) */
160 nvidia,pins = "hdint";
161 nvidia,function = "hdmi";
162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
168 nvidia,function = "i2c1";
169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
174 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
175 * today's display need DE, disable LCD_M1
179 nvidia,function = "rsvd3";
180 nvidia,tristate = <TEGRA_PIN_ENABLE>;
183 /* Colibri LCD (L_* resp. LDD<*>) */
185 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
186 "ld4", "ld5", "ld6", "ld7",
187 "ld8", "ld9", "ld10", "ld11",
188 "ld12", "ld13", "ld14", "ld15",
189 "ld16", "ld17", "lhs", "lsc0",
191 nvidia,function = "displaya";
192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
194 /* Colibri LCD (Optional 24 BPP Support) */
196 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
198 nvidia,function = "displaya";
199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
204 nvidia,pins = "atb", "gma";
205 nvidia,function = "sdio4";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
213 nvidia,function = "gmi_int";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
218 /* Colibri MMC (Optional 8-bit) */
221 nvidia,function = "sdio4";
222 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
227 * Colibri Parallel Camera (Optional)
228 * pins multiplexed with others and therefore disabled
229 * Note: dta used for BL_ON by default
232 nvidia,pins = "csus";
233 nvidia,function = "vi_sensor_clk";
234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
238 nvidia,pins = "dtb", "dtc", "dtd";
239 nvidia,function = "vi";
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
244 /* Colibri PWM<C>, PWM<D> */
246 nvidia,pins = "sdb", "sdd";
247 nvidia,function = "pwm";
248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
253 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
254 nvidia,function = "spi4";
255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_ENABLE>;
261 nvidia,pins = "sdio1";
262 nvidia,function = "uarta";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
267 nvidia,pins = "lpw1";
268 nvidia,function = "rsvd3";
269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
272 nvidia,pins = "lpw2";
273 nvidia,function = "hdmi";
274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
280 nvidia,function = "uartd";
281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristate = <TEGRA_PIN_ENABLE>;
288 nvidia,function = "irda";
289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
293 /* Colibri USB_CDET */
295 nvidia,pins = "spdo";
296 nvidia,function = "rsvd2";
297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298 nvidia,tristate = <TEGRA_PIN_ENABLE>;
301 /* Colibri USBH_OC */
303 nvidia,pins = "spih";
304 nvidia,function = "spi2_alt";
305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
309 /* Colibri USBH_PEN */
311 nvidia,pins = "spig";
312 nvidia,function = "spi2_alt";
313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
314 nvidia,tristate = <TEGRA_PIN_ENABLE>;
317 /* Colibri VGA not supported */
319 nvidia,pins = "crtp";
320 nvidia,function = "crt";
321 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
322 nvidia,tristate = <TEGRA_PIN_ENABLE>;
325 /* I2C3 (Optional) */
328 nvidia,function = "i2c3";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_ENABLE>;
335 nvidia,pins = "gpu7";
336 nvidia,function = "rtck";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
342 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
347 nvidia,function = "rsvd2";
348 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
349 nvidia,tristate = <TEGRA_PIN_DISABLE>;
353 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
354 * (All On-module); Colibri CAN_INT
358 nvidia,function = "rsvd1";
359 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
360 nvidia,tristate = <TEGRA_PIN_DISABLE>;
363 /* NAND (On-module) */
365 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
367 nvidia,function = "nand";
368 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
369 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 /* Onewire (Optional) */
375 nvidia,function = "owr";
376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristate = <TEGRA_PIN_ENABLE>;
380 /* Power I2C (On-module) */
382 nvidia,pins = "i2cp";
383 nvidia,function = "i2cp";
384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
391 nvidia,function = "gmi";
392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
398 * Note: spid and spie used for Colibri Address/Data
402 nvidia,pins = "spid", "spie", "spif";
403 nvidia,function = "spi1";
404 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405 nvidia,tristate = <TEGRA_PIN_ENABLE>;
409 * THERMD_ALERT# (On-module), unlatched I2C address pin
410 * of LM95245 temperature sensor therefore requires
414 nvidia,pins = "lvp0";
415 nvidia,function = "rsvd3";
416 nvidia,tristate = <TEGRA_PIN_ENABLE>;
421 tegra_ac97: ac97@70002000 {
423 nvidia,codec-reset-gpio =
424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
425 nvidia,codec-sync-gpio =
426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
430 compatible = "nvidia,tegra20-hsuart";
431 /delete-property/ reg-shift;
435 compatible = "nvidia,tegra20-hsuart";
436 /delete-property/ reg-shift;
439 nand-controller@70008000 {
444 #address-cells = <1>;
446 nand-bus-width = <8>;
448 nand-ecc-algo = "bch";
451 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
456 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
460 clock-frequency = <400000>;
463 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
464 hdmi_ddc: i2c@7000c400 {
465 clock-frequency = <10000>;
468 /* GEN2_I2C: unused */
470 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
472 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
475 clock-frequency = <100000>;
478 compatible = "ti,tps6586x";
480 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
481 ti,system-power-controller;
484 sys-supply = <®_module_3v3>;
485 vin-sm0-supply = <®_3v3_vsys>;
486 vin-sm1-supply = <®_3v3_vsys>;
487 vin-sm2-supply = <®_3v3_vsys>;
488 vinldo01-supply = <®_1v8_vdd_ddr2>;
489 vinldo23-supply = <®_module_3v3>;
490 vinldo4-supply = <®_module_3v3>;
491 vinldo678-supply = <®_module_3v3>;
492 vinldo9-supply = <®_module_3v3>;
496 regulator-name = "VSYS_3.3V";
501 regulator-name = "VDD_CORE_1.2V";
502 regulator-min-microvolt = <1200000>;
503 regulator-max-microvolt = <1200000>;
508 regulator-name = "VDD_CPU_1.0V";
509 regulator-min-microvolt = <1000000>;
510 regulator-max-microvolt = <1000000>;
514 reg_1v8_vdd_ddr2: sm2 {
515 regulator-name = "VDD_DDR2_1.8V";
516 regulator-min-microvolt = <1800000>;
517 regulator-max-microvolt = <1800000>;
521 /* LDO0 is not connected to anything */
524 * +3.3V_ENABLE_N switching via FET:
525 * AVDD_AUDIO_S and +3.3V
526 * see also +3.3V fixed supply
529 regulator-name = "AVDD_PLL_1.1V";
530 regulator-min-microvolt = <1100000>;
531 regulator-max-microvolt = <1100000>;
536 regulator-name = "VDD_RTC_1.2V";
537 regulator-min-microvolt = <1200000>;
538 regulator-max-microvolt = <1200000>;
541 /* LDO3 is not connected to anything */
544 regulator-name = "VDDIO_SYS_1.8V";
545 regulator-min-microvolt = <1800000>;
546 regulator-max-microvolt = <1800000>;
550 /* Switched via FET from regular +3.3V */
552 regulator-name = "+3.3V_USB";
553 regulator-min-microvolt = <3300000>;
554 regulator-max-microvolt = <3300000>;
559 regulator-name = "AVDD_VDAC_2.85V";
560 regulator-min-microvolt = <2850000>;
561 regulator-max-microvolt = <2850000>;
564 reg_3v3_avdd_hdmi: ldo7 {
565 regulator-name = "AVDD_HDMI_3.3V";
566 regulator-min-microvolt = <3300000>;
567 regulator-max-microvolt = <3300000>;
570 reg_1v8_avdd_hdmi_pll: ldo8 {
571 regulator-name = "AVDD_HDMI_PLL_1.8V";
572 regulator-min-microvolt = <1800000>;
573 regulator-max-microvolt = <1800000>;
577 regulator-name = "VDDIO_RX_DDR_2.85V";
578 regulator-min-microvolt = <2850000>;
579 regulator-max-microvolt = <2850000>;
584 regulator-name = "VCC_BATT";
585 regulator-min-microvolt = <3300000>;
586 regulator-max-microvolt = <3300000>;
592 /* LM95245 temperature sensor */
594 compatible = "national,lm95245";
600 nvidia,suspend-mode = <1>;
601 nvidia,cpu-pwr-good-time = <5000>;
602 nvidia,cpu-pwr-off-time = <5000>;
603 nvidia,core-pwr-good-time = <3845 3845>;
604 nvidia,core-pwr-off-time = <3875>;
605 nvidia,sys-clock-req-active-high;
606 core-supply = <&vdd_core>;
608 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
610 nvidia,i2c-controller-id = <3>;
611 nvidia,bus-addr = <0x34>;
612 nvidia,reg-addr = <0x14>;
613 nvidia,reg-data = <0x8>;
617 memory-controller@7000f400 {
620 compatible = "nvidia,tegra20-emc-table";
621 clock-frequency = <83250>;
622 nvidia,emc-registers = <0x00000005 0x00000011
623 0x00000004 0x00000002 0x00000004 0x00000004
624 0x00000001 0x0000000a 0x00000002 0x00000002
625 0x00000001 0x00000001 0x00000003 0x00000004
626 0x00000003 0x00000009 0x0000000c 0x0000025f
627 0x00000000 0x00000003 0x00000003 0x00000002
628 0x00000002 0x00000001 0x00000008 0x000000c8
629 0x00000003 0x00000005 0x00000003 0x0000000c
630 0x00000002 0x00000000 0x00000000 0x00000002
631 0x00000000 0x00000000 0x00000083 0x00520006
632 0x00000010 0x00000008 0x00000000 0x00000000
633 0x00000000 0x00000000 0x00000000 0x00000000>;
637 compatible = "nvidia,tegra20-emc-table";
638 clock-frequency = <133200>;
639 nvidia,emc-registers = <0x00000008 0x00000019
640 0x00000006 0x00000002 0x00000004 0x00000004
641 0x00000001 0x0000000a 0x00000002 0x00000002
642 0x00000002 0x00000001 0x00000003 0x00000004
643 0x00000003 0x00000009 0x0000000c 0x0000039f
644 0x00000000 0x00000003 0x00000003 0x00000002
645 0x00000002 0x00000001 0x00000008 0x000000c8
646 0x00000003 0x00000007 0x00000003 0x0000000c
647 0x00000002 0x00000000 0x00000000 0x00000002
648 0x00000000 0x00000000 0x00000083 0x00510006
649 0x00000010 0x00000008 0x00000000 0x00000000
650 0x00000000 0x00000000 0x00000000 0x00000000>;
654 compatible = "nvidia,tegra20-emc-table";
655 clock-frequency = <166500>;
656 nvidia,emc-registers = <0x0000000a 0x00000021
657 0x00000008 0x00000003 0x00000004 0x00000004
658 0x00000002 0x0000000a 0x00000003 0x00000003
659 0x00000002 0x00000001 0x00000003 0x00000004
660 0x00000003 0x00000009 0x0000000c 0x000004df
661 0x00000000 0x00000003 0x00000003 0x00000003
662 0x00000003 0x00000001 0x00000009 0x000000c8
663 0x00000003 0x00000009 0x00000004 0x0000000c
664 0x00000002 0x00000000 0x00000000 0x00000002
665 0x00000000 0x00000000 0x00000083 0x004f0006
666 0x00000010 0x00000008 0x00000000 0x00000000
667 0x00000000 0x00000000 0x00000000 0x00000000>;
671 compatible = "nvidia,tegra20-emc-table";
672 clock-frequency = <333000>;
673 nvidia,emc-registers = <0x00000014 0x00000041
674 0x0000000f 0x00000005 0x00000004 0x00000005
675 0x00000003 0x0000000a 0x00000005 0x00000005
676 0x00000004 0x00000001 0x00000003 0x00000004
677 0x00000003 0x00000009 0x0000000c 0x000009ff
678 0x00000000 0x00000003 0x00000003 0x00000005
679 0x00000005 0x00000001 0x0000000e 0x000000c8
680 0x00000003 0x00000011 0x00000006 0x0000000c
681 0x00000002 0x00000000 0x00000000 0x00000002
682 0x00000000 0x00000000 0x00000083 0x00380006
683 0x00000010 0x00000008 0x00000000 0x00000000
684 0x00000000 0x00000000 0x00000000 0x00000000>;
688 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
691 #address-cells = <1>;
695 compatible = "usbb95,772b";
697 local-mac-address = [00 00 00 00 00 00];
703 nvidia,phy-reset-gpio =
704 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
705 vbus-supply = <®_lan_v_bus>;
709 compatible = "fixed-clock";
711 clock-frequency = <32768>;
714 reg_lan_v_bus: regulator-lan-v-bus {
715 compatible = "regulator-fixed";
716 regulator-name = "LAN_V_BUS";
717 regulator-min-microvolt = <5000000>;
718 regulator-max-microvolt = <5000000>;
720 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
723 reg_module_3v3: regulator-module-3v3 {
724 compatible = "regulator-fixed";
725 regulator-name = "+V3.3";
726 regulator-min-microvolt = <3300000>;
727 regulator-max-microvolt = <3300000>;
732 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
733 "nvidia,tegra-audio-wm9712";
734 nvidia,model = "Toradex Colibri T20";
735 nvidia,audio-routing =
736 "Headphone", "HPOUTL",
737 "Headphone", "HPOUTR",
741 nvidia,ac97-controller = <&tegra_ac97>;
742 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
743 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
744 <&tegra_car TEGRA20_CLK_CDEV1>;
745 clock-names = "pll_a", "pll_a_out0", "mclk";
749 &emc_icc_dvfs_opp_table {
750 /delete-node/ opp-760000000;
756 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
758 line-name = "LAN_RESET#";
761 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
764 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
766 line-name = "Tri-state nPWE";
769 /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
772 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
774 line-name = "Not tri-state RDnWR";