1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
12 compatible = "nvidia,tegra124";
13 interrupt-parent = <&lic>;
18 device_type = "memory";
19 reg = <0x0 0x80000000 0x0 0x0>;
23 compatible = "nvidia,tegra124-pcie";
25 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
26 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
27 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
28 reg-names = "pads", "afi", "cs";
29 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
30 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
31 interrupt-names = "intr", "msi";
33 #interrupt-cells = <1>;
34 interrupt-map-mask = <0 0 0 0>;
35 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
37 bus-range = <0x00 0xff>;
41 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
42 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
43 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
44 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
45 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
47 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
48 <&tegra_car TEGRA124_CLK_AFI>,
49 <&tegra_car TEGRA124_CLK_PLL_E>,
50 <&tegra_car TEGRA124_CLK_CML0>;
51 clock-names = "pex", "afi", "pll_e", "cml";
52 resets = <&tegra_car 70>,
55 reset-names = "pex", "afi", "pcie_x";
60 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
61 reg = <0x000800 0 0 0 0>;
62 bus-range = <0x00 0xff>;
69 nvidia,num-lanes = <2>;
74 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
75 reg = <0x001000 0 0 0 0>;
76 bus-range = <0x00 0xff>;
83 nvidia,num-lanes = <1>;
88 compatible = "nvidia,tegra124-host1x", "simple-bus";
89 reg = <0x0 0x50000000 0x0 0x00034000>;
90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
92 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
93 resets = <&tegra_car 28>;
94 reset-names = "host1x";
95 iommus = <&mc TEGRA_SWGROUP_HC>;
100 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
103 compatible = "nvidia,tegra124-dc";
104 reg = <0x0 0x54200000 0x0 0x00040000>;
105 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
107 <&tegra_car TEGRA124_CLK_PLL_P>;
108 clock-names = "dc", "parent";
109 resets = <&tegra_car 27>;
112 iommus = <&mc TEGRA_SWGROUP_DC>;
118 compatible = "nvidia,tegra124-dc";
119 reg = <0x0 0x54240000 0x0 0x00040000>;
120 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
122 <&tegra_car TEGRA124_CLK_PLL_P>;
123 clock-names = "dc", "parent";
124 resets = <&tegra_car 26>;
127 iommus = <&mc TEGRA_SWGROUP_DCB>;
132 hdmi: hdmi@54280000 {
133 compatible = "nvidia,tegra124-hdmi";
134 reg = <0x0 0x54280000 0x0 0x00040000>;
135 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
137 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
138 clock-names = "hdmi", "parent";
139 resets = <&tegra_car 51>;
140 reset-names = "hdmi";
145 compatible = "nvidia,tegra124-vic";
146 reg = <0x0 0x54340000 0x0 0x00040000>;
147 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&tegra_car TEGRA124_CLK_VIC03>;
150 resets = <&tegra_car 178>;
153 iommus = <&mc TEGRA_SWGROUP_VIC>;
157 compatible = "nvidia,tegra124-sor";
158 reg = <0x0 0x54540000 0x0 0x00040000>;
159 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
161 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
162 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
163 <&tegra_car TEGRA124_CLK_PLL_DP>,
164 <&tegra_car TEGRA124_CLK_CLK_M>;
165 clock-names = "sor", "out", "parent", "dp", "safe";
166 resets = <&tegra_car 182>;
171 dpaux: dpaux@545c0000 {
172 compatible = "nvidia,tegra124-dpaux";
173 reg = <0x0 0x545c0000 0x0 0x00040000>;
174 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
176 <&tegra_car TEGRA124_CLK_PLL_DP>;
177 clock-names = "dpaux", "parent";
178 resets = <&tegra_car 181>;
179 reset-names = "dpaux";
184 gic: interrupt-controller@50041000 {
185 compatible = "arm,cortex-a15-gic";
186 #interrupt-cells = <3>;
187 interrupt-controller;
188 reg = <0x0 0x50041000 0x0 0x1000>,
189 <0x0 0x50042000 0x0 0x1000>,
190 <0x0 0x50044000 0x0 0x2000>,
191 <0x0 0x50046000 0x0 0x2000>;
192 interrupts = <GIC_PPI 9
193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
194 interrupt-parent = <&gic>;
198 * Please keep the following 0, notation in place as a former mainline
199 * U-Boot version was looking for that particular notation in order to
200 * perform required fix-ups on that GPU node.
203 compatible = "nvidia,gk20a";
204 reg = <0x0 0x57000000 0x0 0x01000000>,
205 <0x0 0x58000000 0x0 0x01000000>;
206 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-names = "stall", "nonstall";
209 clocks = <&tegra_car TEGRA124_CLK_GPU>,
210 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
211 clock-names = "gpu", "pwr";
212 resets = <&tegra_car 184>;
215 iommus = <&mc TEGRA_SWGROUP_GPU>;
220 lic: interrupt-controller@60004000 {
221 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
222 reg = <0x0 0x60004000 0x0 0x100>,
223 <0x0 0x60004100 0x0 0x100>,
224 <0x0 0x60004200 0x0 0x100>,
225 <0x0 0x60004300 0x0 0x100>,
226 <0x0 0x60004400 0x0 0x100>;
227 interrupt-controller;
228 #interrupt-cells = <3>;
229 interrupt-parent = <&gic>;
233 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
234 reg = <0x0 0x60005000 0x0 0x400>;
235 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
244 tegra_car: clock@60006000 {
245 compatible = "nvidia,tegra124-car";
246 reg = <0x0 0x60006000 0x0 0x1000>;
249 nvidia,external-memory-controller = <&emc>;
252 flow-controller@60007000 {
253 compatible = "nvidia,tegra124-flowctrl";
254 reg = <0x0 0x60007000 0x0 0x1000>;
258 compatible = "nvidia,tegra124-actmon";
259 reg = <0x0 0x6000c800 0x0 0x400>;
260 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
262 <&tegra_car TEGRA124_CLK_EMC>;
263 clock-names = "actmon", "emc";
264 resets = <&tegra_car 119>;
265 reset-names = "actmon";
268 gpio: gpio@6000d000 {
269 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
270 reg = <0x0 0x6000d000 0x0 0x1000>;
271 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
281 #interrupt-cells = <2>;
282 interrupt-controller;
284 gpio-ranges = <&pinmux 0 0 251>;
288 apbdma: dma@60020000 {
289 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
290 reg = <0x0 0x60020000 0x0 0x1400>;
291 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
324 resets = <&tegra_car 34>;
330 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
331 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
332 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
335 pinmux: pinmux@70000868 {
336 compatible = "nvidia,tegra124-pinmux";
337 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
338 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
339 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
343 * There are two serial driver i.e. 8250 based simple serial
344 * driver and APB DMA based serial driver for higher baudrate
345 * and performace. To enable the 8250 based driver, the compatible
346 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
347 * the APB DMA based serial driver, the compatible is
348 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
350 uarta: serial@70006000 {
351 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
352 reg = <0x0 0x70006000 0x0 0x40>;
354 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
356 resets = <&tegra_car 6>;
357 reset-names = "serial";
358 dmas = <&apbdma 8>, <&apbdma 8>;
359 dma-names = "rx", "tx";
363 uartb: serial@70006040 {
364 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
365 reg = <0x0 0x70006040 0x0 0x40>;
367 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
369 resets = <&tegra_car 7>;
370 reset-names = "serial";
371 dmas = <&apbdma 9>, <&apbdma 9>;
372 dma-names = "rx", "tx";
376 uartc: serial@70006200 {
377 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
378 reg = <0x0 0x70006200 0x0 0x40>;
380 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
382 resets = <&tegra_car 55>;
383 reset-names = "serial";
384 dmas = <&apbdma 10>, <&apbdma 10>;
385 dma-names = "rx", "tx";
389 uartd: serial@70006300 {
390 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
391 reg = <0x0 0x70006300 0x0 0x40>;
393 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
395 resets = <&tegra_car 65>;
396 reset-names = "serial";
397 dmas = <&apbdma 19>, <&apbdma 19>;
398 dma-names = "rx", "tx";
403 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
404 reg = <0x0 0x7000a000 0x0 0x100>;
406 clocks = <&tegra_car TEGRA124_CLK_PWM>;
407 resets = <&tegra_car 17>;
413 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
414 reg = <0x0 0x7000c000 0x0 0x100>;
415 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
418 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
419 clock-names = "div-clk";
420 resets = <&tegra_car 12>;
422 dmas = <&apbdma 21>, <&apbdma 21>;
423 dma-names = "rx", "tx";
428 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
429 reg = <0x0 0x7000c400 0x0 0x100>;
430 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
433 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
434 clock-names = "div-clk";
435 resets = <&tegra_car 54>;
437 dmas = <&apbdma 22>, <&apbdma 22>;
438 dma-names = "rx", "tx";
443 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
444 reg = <0x0 0x7000c500 0x0 0x100>;
445 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
448 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
449 clock-names = "div-clk";
450 resets = <&tegra_car 67>;
452 dmas = <&apbdma 23>, <&apbdma 23>;
453 dma-names = "rx", "tx";
458 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
459 reg = <0x0 0x7000c700 0x0 0x100>;
460 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
461 #address-cells = <1>;
463 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
464 clock-names = "div-clk";
465 resets = <&tegra_car 103>;
467 dmas = <&apbdma 26>, <&apbdma 26>;
468 dma-names = "rx", "tx";
473 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
474 reg = <0x0 0x7000d000 0x0 0x100>;
475 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
478 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
479 clock-names = "div-clk";
480 resets = <&tegra_car 47>;
482 dmas = <&apbdma 24>, <&apbdma 24>;
483 dma-names = "rx", "tx";
488 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
489 reg = <0x0 0x7000d100 0x0 0x100>;
490 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
493 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
494 clock-names = "div-clk";
495 resets = <&tegra_car 166>;
497 dmas = <&apbdma 30>, <&apbdma 30>;
498 dma-names = "rx", "tx";
503 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
504 reg = <0x0 0x7000d400 0x0 0x200>;
505 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
508 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
510 resets = <&tegra_car 41>;
512 dmas = <&apbdma 15>, <&apbdma 15>;
513 dma-names = "rx", "tx";
518 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
519 reg = <0x0 0x7000d600 0x0 0x200>;
520 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
521 #address-cells = <1>;
523 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
525 resets = <&tegra_car 44>;
527 dmas = <&apbdma 16>, <&apbdma 16>;
528 dma-names = "rx", "tx";
533 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
534 reg = <0x0 0x7000d800 0x0 0x200>;
535 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
536 #address-cells = <1>;
538 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
540 resets = <&tegra_car 46>;
542 dmas = <&apbdma 17>, <&apbdma 17>;
543 dma-names = "rx", "tx";
548 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
549 reg = <0x0 0x7000da00 0x0 0x200>;
550 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
551 #address-cells = <1>;
553 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
555 resets = <&tegra_car 68>;
557 dmas = <&apbdma 18>, <&apbdma 18>;
558 dma-names = "rx", "tx";
563 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
564 reg = <0x0 0x7000dc00 0x0 0x200>;
565 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
568 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
570 resets = <&tegra_car 104>;
572 dmas = <&apbdma 27>, <&apbdma 27>;
573 dma-names = "rx", "tx";
578 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
579 reg = <0x0 0x7000de00 0x0 0x200>;
580 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
581 #address-cells = <1>;
583 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
585 resets = <&tegra_car 105>;
587 dmas = <&apbdma 28>, <&apbdma 28>;
588 dma-names = "rx", "tx";
593 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
594 reg = <0x0 0x7000e000 0x0 0x100>;
595 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&tegra_car TEGRA124_CLK_RTC>;
599 tegra_pmc: pmc@7000e400 {
600 compatible = "nvidia,tegra124-pmc";
601 reg = <0x0 0x7000e400 0x0 0x400>;
602 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
603 clock-names = "pclk", "clk32k_in";
608 compatible = "nvidia,tegra124-efuse";
609 reg = <0x0 0x7000f800 0x0 0x400>;
610 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
611 clock-names = "fuse";
612 resets = <&tegra_car 39>;
613 reset-names = "fuse";
616 mc: memory-controller@70019000 {
617 compatible = "nvidia,tegra124-mc";
618 reg = <0x0 0x70019000 0x0 0x1000>;
619 clocks = <&tegra_car TEGRA124_CLK_MC>;
622 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
627 emc: external-memory-controller@7001b000 {
628 compatible = "nvidia,tegra124-emc";
629 reg = <0x0 0x7001b000 0x0 0x1000>;
630 clocks = <&tegra_car TEGRA124_CLK_EMC>;
633 nvidia,memory-controller = <&mc>;
637 compatible = "nvidia,tegra124-ahci";
638 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
639 <0x0 0x70020000 0x0 0x7000>; /* SATA */
640 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&tegra_car TEGRA124_CLK_SATA>,
642 <&tegra_car TEGRA124_CLK_SATA_OOB>,
643 <&tegra_car TEGRA124_CLK_CML1>,
644 <&tegra_car TEGRA124_CLK_PLL_E>;
645 clock-names = "sata", "sata-oob", "cml1", "pll_e";
646 resets = <&tegra_car 124>,
649 reset-names = "sata", "sata-oob", "sata-cold";
654 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
655 reg = <0x0 0x70030000 0x0 0x10000>;
656 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&tegra_car TEGRA124_CLK_HDA>,
658 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
659 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
660 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
661 resets = <&tegra_car 125>, /* hda */
662 <&tegra_car 128>, /* hda2hdmi */
663 <&tegra_car 111>; /* hda2codec_2x */
664 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
669 compatible = "nvidia,tegra124-xusb";
670 reg = <0x0 0x70090000 0x0 0x8000>,
671 <0x0 0x70098000 0x0 0x1000>,
672 <0x0 0x70099000 0x0 0x1000>;
673 reg-names = "hcd", "fpci", "ipfs";
675 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
679 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
680 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
681 <&tegra_car TEGRA124_CLK_XUSB_SS>,
682 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
683 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
684 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
685 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
686 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
687 <&tegra_car TEGRA124_CLK_CLK_M>,
688 <&tegra_car TEGRA124_CLK_PLL_E>;
689 clock-names = "xusb_host", "xusb_host_src",
690 "xusb_falcon_src", "xusb_ss",
691 "xusb_ss_div2", "xusb_ss_src",
692 "xusb_hs_src", "xusb_fs_src",
693 "pll_u_480m", "clk_m", "pll_e";
694 resets = <&tegra_car 89>, <&tegra_car 156>,
696 reset-names = "xusb_host", "xusb_ss", "xusb_src";
698 nvidia,xusb-padctl = <&padctl>;
703 padctl: padctl@7009f000 {
704 compatible = "nvidia,tegra124-xusb-padctl";
705 reg = <0x0 0x7009f000 0x0 0x1000>;
706 resets = <&tegra_car 142>;
707 reset-names = "padctl";
837 compatible = "nvidia,tegra124-sdhci";
838 reg = <0x0 0x700b0000 0x0 0x200>;
839 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
841 resets = <&tegra_car 14>;
842 reset-names = "sdhci";
847 compatible = "nvidia,tegra124-sdhci";
848 reg = <0x0 0x700b0200 0x0 0x200>;
849 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
851 resets = <&tegra_car 9>;
852 reset-names = "sdhci";
857 compatible = "nvidia,tegra124-sdhci";
858 reg = <0x0 0x700b0400 0x0 0x200>;
859 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
861 resets = <&tegra_car 69>;
862 reset-names = "sdhci";
867 compatible = "nvidia,tegra124-sdhci";
868 reg = <0x0 0x700b0600 0x0 0x200>;
869 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
871 resets = <&tegra_car 15>;
872 reset-names = "sdhci";
877 compatible = "nvidia,tegra124-cec";
878 reg = <0x0 0x70015000 0x0 0x00001000>;
879 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&tegra_car TEGRA124_CLK_CEC>;
883 hdmi-phandle = <&hdmi>;
886 soctherm: thermal-sensor@700e2000 {
887 compatible = "nvidia,tegra124-soctherm";
888 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
889 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
890 reg-names = "soctherm-reg", "car-reg";
891 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
893 <&tegra_car TEGRA124_CLK_SOC_THERM>;
894 clock-names = "tsensor", "soctherm";
895 resets = <&tegra_car 78>;
896 reset-names = "soctherm";
897 #thermal-sensor-cells = <1>;
900 throttle_heavy: heavy {
901 nvidia,priority = <100>;
902 nvidia,cpu-throt-percent = <85>;
904 #cooling-cells = <2>;
909 dfll: clock@70110000 {
910 compatible = "nvidia,tegra124-dfll";
911 reg = <0 0x70110000 0 0x100>, /* DFLL control */
912 <0 0x70110000 0 0x100>, /* I2C output control */
913 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
914 <0 0x70110200 0 0x100>; /* Look-up table RAM */
915 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
917 <&tegra_car TEGRA124_CLK_DFLL_REF>,
918 <&tegra_car TEGRA124_CLK_I2C5>;
919 clock-names = "soc", "ref", "i2c";
920 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
921 reset-names = "dvco";
923 clock-output-names = "dfllCPU_out";
924 nvidia,sample-rate = <12500>;
925 nvidia,droop-ctrl = <0x00000f00>;
926 nvidia,force-mode = <1>;
934 compatible = "nvidia,tegra124-ahub";
935 reg = <0x0 0x70300000 0x0 0x200>,
936 <0x0 0x70300800 0x0 0x800>,
937 <0x0 0x70300200 0x0 0x600>;
938 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
940 <&tegra_car TEGRA124_CLK_APBIF>;
941 clock-names = "d_audio", "apbif";
942 resets = <&tegra_car 106>, /* d_audio */
943 <&tegra_car 107>, /* apbif */
944 <&tegra_car 30>, /* i2s0 */
945 <&tegra_car 11>, /* i2s1 */
946 <&tegra_car 18>, /* i2s2 */
947 <&tegra_car 101>, /* i2s3 */
948 <&tegra_car 102>, /* i2s4 */
949 <&tegra_car 108>, /* dam0 */
950 <&tegra_car 109>, /* dam1 */
951 <&tegra_car 110>, /* dam2 */
952 <&tegra_car 10>, /* spdif */
953 <&tegra_car 153>, /* amx */
954 <&tegra_car 185>, /* amx1 */
955 <&tegra_car 154>, /* adx */
956 <&tegra_car 180>, /* adx1 */
957 <&tegra_car 186>, /* afc0 */
958 <&tegra_car 187>, /* afc1 */
959 <&tegra_car 188>, /* afc2 */
960 <&tegra_car 189>, /* afc3 */
961 <&tegra_car 190>, /* afc4 */
962 <&tegra_car 191>; /* afc5 */
963 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
964 "i2s3", "i2s4", "dam0", "dam1", "dam2",
965 "spdif", "amx", "amx1", "adx", "adx1",
966 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
967 dmas = <&apbdma 1>, <&apbdma 1>,
968 <&apbdma 2>, <&apbdma 2>,
969 <&apbdma 3>, <&apbdma 3>,
970 <&apbdma 4>, <&apbdma 4>,
971 <&apbdma 6>, <&apbdma 6>,
972 <&apbdma 7>, <&apbdma 7>,
973 <&apbdma 12>, <&apbdma 12>,
974 <&apbdma 13>, <&apbdma 13>,
975 <&apbdma 14>, <&apbdma 14>,
976 <&apbdma 29>, <&apbdma 29>;
977 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
978 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
979 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
982 #address-cells = <2>;
985 tegra_i2s0: i2s@70301000 {
986 compatible = "nvidia,tegra124-i2s";
987 reg = <0x0 0x70301000 0x0 0x100>;
988 nvidia,ahub-cif-ids = <4 4>;
989 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
990 resets = <&tegra_car 30>;
995 tegra_i2s1: i2s@70301100 {
996 compatible = "nvidia,tegra124-i2s";
997 reg = <0x0 0x70301100 0x0 0x100>;
998 nvidia,ahub-cif-ids = <5 5>;
999 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1000 resets = <&tegra_car 11>;
1001 reset-names = "i2s";
1002 status = "disabled";
1005 tegra_i2s2: i2s@70301200 {
1006 compatible = "nvidia,tegra124-i2s";
1007 reg = <0x0 0x70301200 0x0 0x100>;
1008 nvidia,ahub-cif-ids = <6 6>;
1009 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1010 resets = <&tegra_car 18>;
1011 reset-names = "i2s";
1012 status = "disabled";
1015 tegra_i2s3: i2s@70301300 {
1016 compatible = "nvidia,tegra124-i2s";
1017 reg = <0x0 0x70301300 0x0 0x100>;
1018 nvidia,ahub-cif-ids = <7 7>;
1019 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1020 resets = <&tegra_car 101>;
1021 reset-names = "i2s";
1022 status = "disabled";
1025 tegra_i2s4: i2s@70301400 {
1026 compatible = "nvidia,tegra124-i2s";
1027 reg = <0x0 0x70301400 0x0 0x100>;
1028 nvidia,ahub-cif-ids = <8 8>;
1029 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1030 resets = <&tegra_car 102>;
1031 reset-names = "i2s";
1032 status = "disabled";
1037 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1038 reg = <0x0 0x7d000000 0x0 0x4000>;
1039 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1042 resets = <&tegra_car 22>;
1043 reset-names = "usb";
1044 nvidia,phy = <&phy1>;
1045 status = "disabled";
1048 phy1: usb-phy@7d000000 {
1049 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1050 reg = <0x0 0x7d000000 0x0 0x4000>,
1051 <0x0 0x7d000000 0x0 0x4000>;
1053 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1054 <&tegra_car TEGRA124_CLK_PLL_U>,
1055 <&tegra_car TEGRA124_CLK_USBD>;
1056 clock-names = "reg", "pll_u", "utmi-pads";
1057 resets = <&tegra_car 22>, <&tegra_car 22>;
1058 reset-names = "usb", "utmi-pads";
1059 nvidia,hssync-start-delay = <0>;
1060 nvidia,idle-wait-delay = <17>;
1061 nvidia,elastic-limit = <16>;
1062 nvidia,term-range-adj = <6>;
1063 nvidia,xcvr-setup = <9>;
1064 nvidia,xcvr-lsfslew = <0>;
1065 nvidia,xcvr-lsrslew = <3>;
1066 nvidia,hssquelch-level = <2>;
1067 nvidia,hsdiscon-level = <5>;
1068 nvidia,xcvr-hsslew = <12>;
1069 nvidia,has-utmi-pad-registers;
1070 status = "disabled";
1074 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1075 reg = <0x0 0x7d004000 0x0 0x4000>;
1076 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1079 resets = <&tegra_car 58>;
1080 reset-names = "usb";
1081 nvidia,phy = <&phy2>;
1082 status = "disabled";
1085 phy2: usb-phy@7d004000 {
1086 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1087 reg = <0x0 0x7d004000 0x0 0x4000>,
1088 <0x0 0x7d000000 0x0 0x4000>;
1090 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1091 <&tegra_car TEGRA124_CLK_PLL_U>,
1092 <&tegra_car TEGRA124_CLK_USBD>;
1093 clock-names = "reg", "pll_u", "utmi-pads";
1094 resets = <&tegra_car 58>, <&tegra_car 22>;
1095 reset-names = "usb", "utmi-pads";
1096 nvidia,hssync-start-delay = <0>;
1097 nvidia,idle-wait-delay = <17>;
1098 nvidia,elastic-limit = <16>;
1099 nvidia,term-range-adj = <6>;
1100 nvidia,xcvr-setup = <9>;
1101 nvidia,xcvr-lsfslew = <0>;
1102 nvidia,xcvr-lsrslew = <3>;
1103 nvidia,hssquelch-level = <2>;
1104 nvidia,hsdiscon-level = <5>;
1105 nvidia,xcvr-hsslew = <12>;
1106 status = "disabled";
1110 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1111 reg = <0x0 0x7d008000 0x0 0x4000>;
1112 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1115 resets = <&tegra_car 59>;
1116 reset-names = "usb";
1117 nvidia,phy = <&phy3>;
1118 status = "disabled";
1121 phy3: usb-phy@7d008000 {
1122 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1123 reg = <0x0 0x7d008000 0x0 0x4000>,
1124 <0x0 0x7d000000 0x0 0x4000>;
1126 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1127 <&tegra_car TEGRA124_CLK_PLL_U>,
1128 <&tegra_car TEGRA124_CLK_USBD>;
1129 clock-names = "reg", "pll_u", "utmi-pads";
1130 resets = <&tegra_car 59>, <&tegra_car 22>;
1131 reset-names = "usb", "utmi-pads";
1132 nvidia,hssync-start-delay = <0>;
1133 nvidia,idle-wait-delay = <17>;
1134 nvidia,elastic-limit = <16>;
1135 nvidia,term-range-adj = <6>;
1136 nvidia,xcvr-setup = <9>;
1137 nvidia,xcvr-lsfslew = <0>;
1138 nvidia,xcvr-lsrslew = <3>;
1139 nvidia,hssquelch-level = <2>;
1140 nvidia,hsdiscon-level = <5>;
1141 nvidia,xcvr-hsslew = <12>;
1142 status = "disabled";
1146 #address-cells = <1>;
1150 device_type = "cpu";
1151 compatible = "arm,cortex-a15";
1154 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1155 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1156 <&tegra_car TEGRA124_CLK_PLL_X>,
1157 <&tegra_car TEGRA124_CLK_PLL_P>,
1159 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1160 /* FIXME: what's the actual transition time? */
1161 clock-latency = <300000>;
1165 device_type = "cpu";
1166 compatible = "arm,cortex-a15";
1171 device_type = "cpu";
1172 compatible = "arm,cortex-a15";
1177 device_type = "cpu";
1178 compatible = "arm,cortex-a15";
1184 compatible = "arm,cortex-a15-pmu";
1185 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1189 interrupt-affinity = <&{/cpus/cpu@0}>,
1197 polling-delay-passive = <1000>;
1198 polling-delay = <1000>;
1201 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1205 temperature = <103000>;
1209 cpu_throttle_trip: throttle-trip {
1210 temperature = <100000>;
1211 hysteresis = <1000>;
1218 trip = <&cpu_throttle_trip>;
1219 cooling-device = <&throttle_heavy 1 1>;
1225 polling-delay-passive = <1000>;
1226 polling-delay = <1000>;
1229 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1233 temperature = <103000>;
1241 * There are currently no cooling maps,
1242 * because there are no cooling devices.
1248 polling-delay-passive = <1000>;
1249 polling-delay = <1000>;
1252 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1256 temperature = <101000>;
1260 gpu_throttle_trip: throttle-trip {
1261 temperature = <99000>;
1262 hysteresis = <1000>;
1269 trip = <&gpu_throttle_trip>;
1270 cooling-device = <&throttle_heavy 1 1>;
1276 polling-delay-passive = <1000>;
1277 polling-delay = <1000>;
1280 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1283 pllx-shutdown-trip {
1284 temperature = <103000>;
1292 * There are currently no cooling maps,
1293 * because there are no cooling devices.
1300 compatible = "arm,armv7-timer";
1301 interrupts = <GIC_PPI 13
1302 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1304 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1306 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1308 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1309 interrupt-parent = <&gic>;