arch/arm/boot/dts/tegra124.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra124-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra124-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/tegra124-car.h>
   8 #include <dt-bindings/thermal/tegra124-soctherm.h>
   9 #include <dt-bindings/soc/tegra-pmc.h>
  10
  11 / {
  12         compatible = "nvidia,tegra124";
  13         interrupt-parent = <&lic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         memory@80000000 {
  18                 device_type = "memory";
  19                 reg = <0x0 0x80000000 0x0 0x0>;
  20         };
  21
  22         pcie@1003000 {
  23                 compatible = "nvidia,tegra124-pcie";
  24                 device_type = "pci";
  25                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  26                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  27                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  28                 reg-names = "pads", "afi", "cs";
  29                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  30                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  31                 interrupt-names = "intr", "msi";
  32
  33                 #interrupt-cells = <1>;
  34                 interrupt-map-mask = <0 0 0 0>;
  35                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  36
  37                 bus-range = <0x00 0xff>;
  38                 #address-cells = <3>;
  39                 #size-cells = <2>;
  40
  41                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  42                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  43                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  44                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  45                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  46
  47                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  48                          <&tegra_car TEGRA124_CLK_AFI>,
  49                          <&tegra_car TEGRA124_CLK_PLL_E>,
  50                          <&tegra_car TEGRA124_CLK_CML0>;
  51                 clock-names = "pex", "afi", "pll_e", "cml";
  52                 resets = <&tegra_car 70>,
  53                          <&tegra_car 72>,
  54                          <&tegra_car 74>;
  55                 reset-names = "pex", "afi", "pcie_x";
  56                 status = "disabled";
  57
  58                 pci@1,0 {
  59                         device_type = "pci";
  60                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  61                         reg = <0x000800 0 0 0 0>;
  62                         bus-range = <0x00 0xff>;
  63                         status = "disabled";
  64
  65                         #address-cells = <3>;
  66                         #size-cells = <2>;
  67                         ranges;
  68
  69                         nvidia,num-lanes = <2>;
  70                 };
  71
  72                 pci@2,0 {
  73                         device_type = "pci";
  74                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  75                         reg = <0x001000 0 0 0 0>;
  76                         bus-range = <0x00 0xff>;
  77                         status = "disabled";
  78
  79                         #address-cells = <3>;
  80                         #size-cells = <2>;
  81                         ranges;
  82
  83                         nvidia,num-lanes = <1>;
  84                 };
  85         };
  86
  87         host1x@50000000 {
  88                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  89                 reg = <0x0 0x50000000 0x0 0x00034000>;
  90                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  91                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  92                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  93                 resets = <&tegra_car 28>;
  94                 reset-names = "host1x";
  95                 iommus = <&mc TEGRA_SWGROUP_HC>;
  96
  97                 #address-cells = <2>;
  98                 #size-cells = <2>;
  99
 100                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
 101
 102                 dc@54200000 {
 103                         compatible = "nvidia,tegra124-dc";
 104                         reg = <0x0 0x54200000 0x0 0x00040000>;
 105                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 106                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 107                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 108                         clock-names = "dc", "parent";
 109                         resets = <&tegra_car 27>;
 110                         reset-names = "dc";
 111
 112                         iommus = <&mc TEGRA_SWGROUP_DC>;
 113
 114                         nvidia,head = <0>;
 115                 };
 116
 117                 dc@54240000 {
 118                         compatible = "nvidia,tegra124-dc";
 119                         reg = <0x0 0x54240000 0x0 0x00040000>;
 120                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 121                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 122                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 123                         clock-names = "dc", "parent";
 124                         resets = <&tegra_car 26>;
 125                         reset-names = "dc";
 126
 127                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 128
 129                         nvidia,head = <1>;
 130                 };
 131
 132                 hdmi: hdmi@54280000 {
 133                         compatible = "nvidia,tegra124-hdmi";
 134                         reg = <0x0 0x54280000 0x0 0x00040000>;
 135                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 136                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 137                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 138                         clock-names = "hdmi", "parent";
 139                         resets = <&tegra_car 51>;
 140                         reset-names = "hdmi";
 141                         status = "disabled";
 142                 };
 143
 144                 vic@54340000 {
 145                         compatible = "nvidia,tegra124-vic";
 146                         reg = <0x0 0x54340000 0x0 0x00040000>;
 147                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 148                         clocks = <&tegra_car TEGRA124_CLK_VIC03>;
 149                         clock-names = "vic";
 150                         resets = <&tegra_car 178>;
 151                         reset-names = "vic";
 152
 153                         iommus = <&mc TEGRA_SWGROUP_VIC>;
 154                 };
 155
 156                 sor@54540000 {
 157                         compatible = "nvidia,tegra124-sor";
 158                         reg = <0x0 0x54540000 0x0 0x00040000>;
 159                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 160                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 161                                  <&tegra_car TEGRA124_CLK_SOR0_OUT>,
 162                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 163                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 164                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 165                         clock-names = "sor", "out", "parent", "dp", "safe";
 166                         resets = <&tegra_car 182>;
 167                         reset-names = "sor";
 168                         status = "disabled";
 169                 };
 170
 171                 dpaux: dpaux@545c0000 {
 172                         compatible = "nvidia,tegra124-dpaux";
 173                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 174                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 175                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 176                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 177                         clock-names = "dpaux", "parent";
 178                         resets = <&tegra_car 181>;
 179                         reset-names = "dpaux";
 180                         status = "disabled";
 181                 };
 182         };
 183
 184         gic: interrupt-controller@50041000 {
 185                 compatible = "arm,cortex-a15-gic";
 186                 #interrupt-cells = <3>;
 187                 interrupt-controller;
 188                 reg = <0x0 0x50041000 0x0 0x1000>,
 189                       <0x0 0x50042000 0x0 0x1000>,
 190                       <0x0 0x50044000 0x0 0x2000>,
 191                       <0x0 0x50046000 0x0 0x2000>;
 192                 interrupts = <GIC_PPI 9
 193                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 194                 interrupt-parent = <&gic>;
 195         };
 196
 197         /*
 198          * Please keep the following 0, notation in place as a former mainline
 199          * U-Boot version was looking for that particular notation in order to
 200          * perform required fix-ups on that GPU node.
 201          */
 202         gpu@0,57000000 {
 203                 compatible = "nvidia,gk20a";
 204                 reg = <0x0 0x57000000 0x0 0x01000000>,
 205                       <0x0 0x58000000 0x0 0x01000000>;
 206                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 208                 interrupt-names = "stall", "nonstall";
 209                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 210                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 211                 clock-names = "gpu", "pwr";
 212                 resets = <&tegra_car 184>;
 213                 reset-names = "gpu";
 214
 215                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 216
 217                 status = "disabled";
 218         };
 219
 220         lic: interrupt-controller@60004000 {
 221                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 222                 reg = <0x0 0x60004000 0x0 0x100>,
 223                       <0x0 0x60004100 0x0 0x100>,
 224                       <0x0 0x60004200 0x0 0x100>,
 225                       <0x0 0x60004300 0x0 0x100>,
 226                       <0x0 0x60004400 0x0 0x100>;
 227                 interrupt-controller;
 228                 #interrupt-cells = <3>;
 229                 interrupt-parent = <&gic>;
 230         };
 231
 232         timer@60005000 {
 233                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 234                 reg = <0x0 0x60005000 0x0 0x400>;
 235                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 242         };
 243
 244         tegra_car: clock@60006000 {
 245                 compatible = "nvidia,tegra124-car";
 246                 reg = <0x0 0x60006000 0x0 0x1000>;
 247                 #clock-cells = <1>;
 248                 #reset-cells = <1>;
 249                 nvidia,external-memory-controller = <&emc>;
 250         };
 251
 252         flow-controller@60007000 {
 253                 compatible = "nvidia,tegra124-flowctrl";
 254                 reg = <0x0 0x60007000 0x0 0x1000>;
 255         };
 256
 257         actmon@6000c800 {
 258                 compatible = "nvidia,tegra124-actmon";
 259                 reg = <0x0 0x6000c800 0x0 0x400>;
 260                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 262                          <&tegra_car TEGRA124_CLK_EMC>;
 263                 clock-names = "actmon", "emc";
 264                 resets = <&tegra_car 119>;
 265                 reset-names = "actmon";
 266         };
 267
 268         gpio: gpio@6000d000 {
 269                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 270                 reg = <0x0 0x6000d000 0x0 0x1000>;
 271                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 279                 #gpio-cells = <2>;
 280                 gpio-controller;
 281                 #interrupt-cells = <2>;
 282                 interrupt-controller;
 283                 /*
 284                 gpio-ranges = <&pinmux 0 0 251>;
 285                 */
 286         };
 287
 288         apbdma: dma@60020000 {
 289                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 290                 reg = <0x0 0x60020000 0x0 0x1400>;
 291                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 306                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 314                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 315                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 316                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 317                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 320                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 323                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 324                 resets = <&tegra_car 34>;
 325                 reset-names = "dma";
 326                 #dma-cells = <1>;
 327         };
 328
 329         apbmisc@70000800 {
 330                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 331                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 332                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 333         };
 334
 335         pinmux: pinmux@70000868 {
 336                 compatible = "nvidia,tegra124-pinmux";
 337                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 338                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 339                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 340         };
 341
 342         /*
 343          * There are two serial driver i.e. 8250 based simple serial
 344          * driver and APB DMA based serial driver for higher baudrate
 345          * and performace. To enable the 8250 based driver, the compatible
 346          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 347          * the APB DMA based serial driver, the compatible is
 348          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 349          */
 350         uarta: serial@70006000 {
 351                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 352                 reg = <0x0 0x70006000 0x0 0x40>;
 353                 reg-shift = <2>;
 354                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 356                 resets = <&tegra_car 6>;
 357                 reset-names = "serial";
 358                 dmas = <&apbdma 8>, <&apbdma 8>;
 359                 dma-names = "rx", "tx";
 360                 status = "disabled";
 361         };
 362
 363         uartb: serial@70006040 {
 364                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 365                 reg = <0x0 0x70006040 0x0 0x40>;
 366                 reg-shift = <2>;
 367                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 369                 resets = <&tegra_car 7>;
 370                 reset-names = "serial";
 371                 dmas = <&apbdma 9>, <&apbdma 9>;
 372                 dma-names = "rx", "tx";
 373                 status = "disabled";
 374         };
 375
 376         uartc: serial@70006200 {
 377                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 378                 reg = <0x0 0x70006200 0x0 0x40>;
 379                 reg-shift = <2>;
 380                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 382                 resets = <&tegra_car 55>;
 383                 reset-names = "serial";
 384                 dmas = <&apbdma 10>, <&apbdma 10>;
 385                 dma-names = "rx", "tx";
 386                 status = "disabled";
 387         };
 388
 389         uartd: serial@70006300 {
 390                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 391                 reg = <0x0 0x70006300 0x0 0x40>;
 392                 reg-shift = <2>;
 393                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 395                 resets = <&tegra_car 65>;
 396                 reset-names = "serial";
 397                 dmas = <&apbdma 19>, <&apbdma 19>;
 398                 dma-names = "rx", "tx";
 399                 status = "disabled";
 400         };
 401
 402         pwm: pwm@7000a000 {
 403                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 404                 reg = <0x0 0x7000a000 0x0 0x100>;
 405                 #pwm-cells = <2>;
 406                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 407                 resets = <&tegra_car 17>;
 408                 reset-names = "pwm";
 409                 status = "disabled";
 410         };
 411
 412         i2c@7000c000 {
 413                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 414                 reg = <0x0 0x7000c000 0x0 0x100>;
 415                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 419                 clock-names = "div-clk";
 420                 resets = <&tegra_car 12>;
 421                 reset-names = "i2c";
 422                 dmas = <&apbdma 21>, <&apbdma 21>;
 423                 dma-names = "rx", "tx";
 424                 status = "disabled";
 425         };
 426
 427         i2c@7000c400 {
 428                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 429                 reg = <0x0 0x7000c400 0x0 0x100>;
 430                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 434                 clock-names = "div-clk";
 435                 resets = <&tegra_car 54>;
 436                 reset-names = "i2c";
 437                 dmas = <&apbdma 22>, <&apbdma 22>;
 438                 dma-names = "rx", "tx";
 439                 status = "disabled";
 440         };
 441
 442         i2c@7000c500 {
 443                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 444                 reg = <0x0 0x7000c500 0x0 0x100>;
 445                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 449                 clock-names = "div-clk";
 450                 resets = <&tegra_car 67>;
 451                 reset-names = "i2c";
 452                 dmas = <&apbdma 23>, <&apbdma 23>;
 453                 dma-names = "rx", "tx";
 454                 status = "disabled";
 455         };
 456
 457         i2c@7000c700 {
 458                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 459                 reg = <0x0 0x7000c700 0x0 0x100>;
 460                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 464                 clock-names = "div-clk";
 465                 resets = <&tegra_car 103>;
 466                 reset-names = "i2c";
 467                 dmas = <&apbdma 26>, <&apbdma 26>;
 468                 dma-names = "rx", "tx";
 469                 status = "disabled";
 470         };
 471
 472         i2c@7000d000 {
 473                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 474                 reg = <0x0 0x7000d000 0x0 0x100>;
 475                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 476                 #address-cells = <1>;
 477                 #size-cells = <0>;
 478                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 479                 clock-names = "div-clk";
 480                 resets = <&tegra_car 47>;
 481                 reset-names = "i2c";
 482                 dmas = <&apbdma 24>, <&apbdma 24>;
 483                 dma-names = "rx", "tx";
 484                 status = "disabled";
 485         };
 486
 487         i2c@7000d100 {
 488                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 489                 reg = <0x0 0x7000d100 0x0 0x100>;
 490                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 491                 #address-cells = <1>;
 492                 #size-cells = <0>;
 493                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 494                 clock-names = "div-clk";
 495                 resets = <&tegra_car 166>;
 496                 reset-names = "i2c";
 497                 dmas = <&apbdma 30>, <&apbdma 30>;
 498                 dma-names = "rx", "tx";
 499                 status = "disabled";
 500         };
 501
 502         spi@7000d400 {
 503                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 504                 reg = <0x0 0x7000d400 0x0 0x200>;
 505                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 509                 clock-names = "spi";
 510                 resets = <&tegra_car 41>;
 511                 reset-names = "spi";
 512                 dmas = <&apbdma 15>, <&apbdma 15>;
 513                 dma-names = "rx", "tx";
 514                 status = "disabled";
 515         };
 516
 517         spi@7000d600 {
 518                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 519                 reg = <0x0 0x7000d600 0x0 0x200>;
 520                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 521                 #address-cells = <1>;
 522                 #size-cells = <0>;
 523                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 524                 clock-names = "spi";
 525                 resets = <&tegra_car 44>;
 526                 reset-names = "spi";
 527                 dmas = <&apbdma 16>, <&apbdma 16>;
 528                 dma-names = "rx", "tx";
 529                 status = "disabled";
 530         };
 531
 532         spi@7000d800 {
 533                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 534                 reg = <0x0 0x7000d800 0x0 0x200>;
 535                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 539                 clock-names = "spi";
 540                 resets = <&tegra_car 46>;
 541                 reset-names = "spi";
 542                 dmas = <&apbdma 17>, <&apbdma 17>;
 543                 dma-names = "rx", "tx";
 544                 status = "disabled";
 545         };
 546
 547         spi@7000da00 {
 548                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 549                 reg = <0x0 0x7000da00 0x0 0x200>;
 550                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 554                 clock-names = "spi";
 555                 resets = <&tegra_car 68>;
 556                 reset-names = "spi";
 557                 dmas = <&apbdma 18>, <&apbdma 18>;
 558                 dma-names = "rx", "tx";
 559                 status = "disabled";
 560         };
 561
 562         spi@7000dc00 {
 563                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 564                 reg = <0x0 0x7000dc00 0x0 0x200>;
 565                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 569                 clock-names = "spi";
 570                 resets = <&tegra_car 104>;
 571                 reset-names = "spi";
 572                 dmas = <&apbdma 27>, <&apbdma 27>;
 573                 dma-names = "rx", "tx";
 574                 status = "disabled";
 575         };
 576
 577         spi@7000de00 {
 578                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 579                 reg = <0x0 0x7000de00 0x0 0x200>;
 580                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 584                 clock-names = "spi";
 585                 resets = <&tegra_car 105>;
 586                 reset-names = "spi";
 587                 dmas = <&apbdma 28>, <&apbdma 28>;
 588                 dma-names = "rx", "tx";
 589                 status = "disabled";
 590         };
 591
 592         rtc@7000e000 {
 593                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 594                 reg = <0x0 0x7000e000 0x0 0x100>;
 595                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 596                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 597         };
 598
 599         tegra_pmc: pmc@7000e400 {
 600                 compatible = "nvidia,tegra124-pmc";
 601                 reg = <0x0 0x7000e400 0x0 0x400>;
 602                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 603                 clock-names = "pclk", "clk32k_in";
 604                 #clock-cells = <1>;
 605         };
 606
 607         fuse@7000f800 {
 608                 compatible = "nvidia,tegra124-efuse";
 609                 reg = <0x0 0x7000f800 0x0 0x400>;
 610                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 611                 clock-names = "fuse";
 612                 resets = <&tegra_car 39>;
 613                 reset-names = "fuse";
 614         };
 615
 616         mc: memory-controller@70019000 {
 617                 compatible = "nvidia,tegra124-mc";
 618                 reg = <0x0 0x70019000 0x0 0x1000>;
 619                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 620                 clock-names = "mc";
 621
 622                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 623
 624                 #iommu-cells = <1>;
 625         };
 626
 627         emc: external-memory-controller@7001b000 {
 628                 compatible = "nvidia,tegra124-emc";
 629                 reg = <0x0 0x7001b000 0x0 0x1000>;
 630                 clocks = <&tegra_car TEGRA124_CLK_EMC>;
 631                 clock-names = "emc";
 632
 633                 nvidia,memory-controller = <&mc>;
 634         };
 635
 636         sata@70020000 {
 637                 compatible = "nvidia,tegra124-ahci";
 638                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 639                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
 640                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 642                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
 643                          <&tegra_car TEGRA124_CLK_CML1>,
 644                          <&tegra_car TEGRA124_CLK_PLL_E>;
 645                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 646                 resets = <&tegra_car 124>,
 647                          <&tegra_car 123>,
 648                          <&tegra_car 129>;
 649                 reset-names = "sata", "sata-oob", "sata-cold";
 650                 status = "disabled";
 651         };
 652
 653         hda@70030000 {
 654                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 655                 reg = <0x0 0x70030000 0x0 0x10000>;
 656                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 657                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 658                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 659                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 660                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 661                 resets = <&tegra_car 125>, /* hda */
 662                          <&tegra_car 128>, /* hda2hdmi */
 663                          <&tegra_car 111>; /* hda2codec_2x */
 664                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 665                 status = "disabled";
 666         };
 667
 668         usb@70090000 {
 669                 compatible = "nvidia,tegra124-xusb";
 670                 reg = <0x0 0x70090000 0x0 0x8000>,
 671                       <0x0 0x70098000 0x0 0x1000>,
 672                       <0x0 0x70099000 0x0 0x1000>;
 673                 reg-names = "hcd", "fpci", "ipfs";
 674
 675                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 676                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 677
 678                 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
 679                          <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
 680                          <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
 681                          <&tegra_car TEGRA124_CLK_XUSB_SS>,
 682                          <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
 683                          <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
 684                          <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
 685                          <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
 686                          <&tegra_car TEGRA124_CLK_PLL_U_480M>,
 687                          <&tegra_car TEGRA124_CLK_CLK_M>,
 688                          <&tegra_car TEGRA124_CLK_PLL_E>;
 689                 clock-names = "xusb_host", "xusb_host_src",
 690                               "xusb_falcon_src", "xusb_ss",
 691                               "xusb_ss_div2", "xusb_ss_src",
 692                               "xusb_hs_src", "xusb_fs_src",
 693                               "pll_u_480m", "clk_m", "pll_e";
 694                 resets = <&tegra_car 89>, <&tegra_car 156>,
 695                          <&tegra_car 143>;
 696                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 697
 698                 nvidia,xusb-padctl = <&padctl>;
 699
 700                 status = "disabled";
 701         };
 702
 703         padctl: padctl@7009f000 {
 704                 compatible = "nvidia,tegra124-xusb-padctl";
 705                 reg = <0x0 0x7009f000 0x0 0x1000>;
 706                 resets = <&tegra_car 142>;
 707                 reset-names = "padctl";
 708
 709                 pads {
 710                         usb2 {
 711                                 status = "disabled";
 712
 713                                 lanes {
 714                                         usb2-0 {
 715                                                 status = "disabled";
 716                                                 #phy-cells = <0>;
 717                                         };
 718
 719                                         usb2-1 {
 720                                                 status = "disabled";
 721                                                 #phy-cells = <0>;
 722                                         };
 723
 724                                         usb2-2 {
 725                                                 status = "disabled";
 726                                                 #phy-cells = <0>;
 727                                         };
 728                                 };
 729                         };
 730
 731                         ulpi {
 732                                 status = "disabled";
 733
 734                                 lanes {
 735                                         ulpi-0 {
 736                                                 status = "disabled";
 737                                                 #phy-cells = <0>;
 738                                         };
 739                                 };
 740                         };
 741
 742                         hsic {
 743                                 status = "disabled";
 744
 745                                 lanes {
 746                                         hsic-0 {
 747                                                 status = "disabled";
 748                                                 #phy-cells = <0>;
 749                                         };
 750
 751                                         hsic-1 {
 752                                                 status = "disabled";
 753                                                 #phy-cells = <0>;
 754                                         };
 755                                 };
 756                         };
 757
 758                         pcie {
 759                                 status = "disabled";
 760
 761                                 lanes {
 762                                         pcie-0 {
 763                                                 status = "disabled";
 764                                                 #phy-cells = <0>;
 765                                         };
 766
 767                                         pcie-1 {
 768                                                 status = "disabled";
 769                                                 #phy-cells = <0>;
 770                                         };
 771
 772                                         pcie-2 {
 773                                                 status = "disabled";
 774                                                 #phy-cells = <0>;
 775                                         };
 776
 777                                         pcie-3 {
 778                                                 status = "disabled";
 779                                                 #phy-cells = <0>;
 780                                         };
 781
 782                                         pcie-4 {
 783                                                 status = "disabled";
 784                                                 #phy-cells = <0>;
 785                                         };
 786                                 };
 787                         };
 788
 789                         sata {
 790                                 status = "disabled";
 791
 792                                 lanes {
 793                                         sata-0 {
 794                                                 status = "disabled";
 795                                                 #phy-cells = <0>;
 796                                         };
 797                                 };
 798                         };
 799                 };
 800
 801                 ports {
 802                         usb2-0 {
 803                                 status = "disabled";
 804                         };
 805
 806                         usb2-1 {
 807                                 status = "disabled";
 808                         };
 809
 810                         usb2-2 {
 811                                 status = "disabled";
 812                         };
 813
 814                         ulpi-0 {
 815                                 status = "disabled";
 816                         };
 817
 818                         hsic-0 {
 819                                 status = "disabled";
 820                         };
 821
 822                         hsic-1 {
 823                                 status = "disabled";
 824                         };
 825
 826                         usb3-0 {
 827                                 status = "disabled";
 828                         };
 829
 830                         usb3-1 {
 831                                 status = "disabled";
 832                         };
 833                 };
 834         };
 835
 836         sdhci@700b0000 {
 837                 compatible = "nvidia,tegra124-sdhci";
 838                 reg = <0x0 0x700b0000 0x0 0x200>;
 839                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 840                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 841                 resets = <&tegra_car 14>;
 842                 reset-names = "sdhci";
 843                 status = "disabled";
 844         };
 845
 846         sdhci@700b0200 {
 847                 compatible = "nvidia,tegra124-sdhci";
 848                 reg = <0x0 0x700b0200 0x0 0x200>;
 849                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 850                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 851                 resets = <&tegra_car 9>;
 852                 reset-names = "sdhci";
 853                 status = "disabled";
 854         };
 855
 856         sdhci@700b0400 {
 857                 compatible = "nvidia,tegra124-sdhci";
 858                 reg = <0x0 0x700b0400 0x0 0x200>;
 859                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 860                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 861                 resets = <&tegra_car 69>;
 862                 reset-names = "sdhci";
 863                 status = "disabled";
 864         };
 865
 866         sdhci@700b0600 {
 867                 compatible = "nvidia,tegra124-sdhci";
 868                 reg = <0x0 0x700b0600 0x0 0x200>;
 869                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 870                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 871                 resets = <&tegra_car 15>;
 872                 reset-names = "sdhci";
 873                 status = "disabled";
 874         };
 875
 876         cec@70015000 {
 877                 compatible = "nvidia,tegra124-cec";
 878                 reg = <0x0 0x70015000 0x0 0x00001000>;
 879                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 880                 clocks = <&tegra_car TEGRA124_CLK_CEC>;
 881                 clock-names = "cec";
 882                 status = "disabled";
 883                 hdmi-phandle = <&hdmi>;
 884         };
 885
 886         soctherm: thermal-sensor@700e2000 {
 887                 compatible = "nvidia,tegra124-soctherm";
 888                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
 889                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
 890                 reg-names = "soctherm-reg", "car-reg";
 891                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 892                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 893                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 894                 clock-names = "tsensor", "soctherm";
 895                 resets = <&tegra_car 78>;
 896                 reset-names = "soctherm";
 897                 #thermal-sensor-cells = <1>;
 898
 899                 throttle-cfgs {
 900                         throttle_heavy: heavy {
 901                                 nvidia,priority = <100>;
 902                                 nvidia,cpu-throt-percent = <85>;
 903
 904                                 #cooling-cells = <2>;
 905                         };
 906                 };
 907         };
 908
 909         dfll: clock@70110000 {
 910                 compatible = "nvidia,tegra124-dfll";
 911                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
 912                       <0 0x70110000 0 0x100>, /* I2C output control */
 913                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
 914                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
 915                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 916                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
 917                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
 918                          <&tegra_car TEGRA124_CLK_I2C5>;
 919                 clock-names = "soc", "ref", "i2c";
 920                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
 921                 reset-names = "dvco";
 922                 #clock-cells = <0>;
 923                 clock-output-names = "dfllCPU_out";
 924                 nvidia,sample-rate = <12500>;
 925                 nvidia,droop-ctrl = <0x00000f00>;
 926                 nvidia,force-mode = <1>;
 927                 nvidia,cf = <10>;
 928                 nvidia,ci = <0>;
 929                 nvidia,cg = <2>;
 930                 status = "disabled";
 931         };
 932
 933         ahub@70300000 {
 934                 compatible = "nvidia,tegra124-ahub";
 935                 reg = <0x0 0x70300000 0x0 0x200>,
 936                       <0x0 0x70300800 0x0 0x800>,
 937                       <0x0 0x70300200 0x0 0x600>;
 938                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 939                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 940                          <&tegra_car TEGRA124_CLK_APBIF>;
 941                 clock-names = "d_audio", "apbif";
 942                 resets = <&tegra_car 106>, /* d_audio */
 943                          <&tegra_car 107>, /* apbif */
 944                          <&tegra_car 30>,  /* i2s0 */
 945                          <&tegra_car 11>,  /* i2s1 */
 946                          <&tegra_car 18>,  /* i2s2 */
 947                          <&tegra_car 101>, /* i2s3 */
 948                          <&tegra_car 102>, /* i2s4 */
 949                          <&tegra_car 108>, /* dam0 */
 950                          <&tegra_car 109>, /* dam1 */
 951                          <&tegra_car 110>, /* dam2 */
 952                          <&tegra_car 10>,  /* spdif */
 953                          <&tegra_car 153>, /* amx */
 954                          <&tegra_car 185>, /* amx1 */
 955                          <&tegra_car 154>, /* adx */
 956                          <&tegra_car 180>, /* adx1 */
 957                          <&tegra_car 186>, /* afc0 */
 958                          <&tegra_car 187>, /* afc1 */
 959                          <&tegra_car 188>, /* afc2 */
 960                          <&tegra_car 189>, /* afc3 */
 961                          <&tegra_car 190>, /* afc4 */
 962                          <&tegra_car 191>; /* afc5 */
 963                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 964                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 965                               "spdif", "amx", "amx1", "adx", "adx1",
 966                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 967                 dmas = <&apbdma 1>, <&apbdma 1>,
 968                        <&apbdma 2>, <&apbdma 2>,
 969                        <&apbdma 3>, <&apbdma 3>,
 970                        <&apbdma 4>, <&apbdma 4>,
 971                        <&apbdma 6>, <&apbdma 6>,
 972                        <&apbdma 7>, <&apbdma 7>,
 973                        <&apbdma 12>, <&apbdma 12>,
 974                        <&apbdma 13>, <&apbdma 13>,
 975                        <&apbdma 14>, <&apbdma 14>,
 976                        <&apbdma 29>, <&apbdma 29>;
 977                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 978                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 979                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 980                             "rx9", "tx9";
 981                 ranges;
 982                 #address-cells = <2>;
 983                 #size-cells = <2>;
 984
 985                 tegra_i2s0: i2s@70301000 {
 986                         compatible = "nvidia,tegra124-i2s";
 987                         reg = <0x0 0x70301000 0x0 0x100>;
 988                         nvidia,ahub-cif-ids = <4 4>;
 989                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 990                         resets = <&tegra_car 30>;
 991                         reset-names = "i2s";
 992                         status = "disabled";
 993                 };
 994
 995                 tegra_i2s1: i2s@70301100 {
 996                         compatible = "nvidia,tegra124-i2s";
 997                         reg = <0x0 0x70301100 0x0 0x100>;
 998                         nvidia,ahub-cif-ids = <5 5>;
 999                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1000                         resets = <&tegra_car 11>;
1001                         reset-names = "i2s";
1002                         status = "disabled";
1003                 };
1004
1005                 tegra_i2s2: i2s@70301200 {
1006                         compatible = "nvidia,tegra124-i2s";
1007                         reg = <0x0 0x70301200 0x0 0x100>;
1008                         nvidia,ahub-cif-ids = <6 6>;
1009                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1010                         resets = <&tegra_car 18>;
1011                         reset-names = "i2s";
1012                         status = "disabled";
1013                 };
1014
1015                 tegra_i2s3: i2s@70301300 {
1016                         compatible = "nvidia,tegra124-i2s";
1017                         reg = <0x0 0x70301300 0x0 0x100>;
1018                         nvidia,ahub-cif-ids = <7 7>;
1019                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1020                         resets = <&tegra_car 101>;
1021                         reset-names = "i2s";
1022                         status = "disabled";
1023                 };
1024
1025                 tegra_i2s4: i2s@70301400 {
1026                         compatible = "nvidia,tegra124-i2s";
1027                         reg = <0x0 0x70301400 0x0 0x100>;
1028                         nvidia,ahub-cif-ids = <8 8>;
1029                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1030                         resets = <&tegra_car 102>;
1031                         reset-names = "i2s";
1032                         status = "disabled";
1033                 };
1034         };
1035
1036         usb@7d000000 {
1037                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1038                 reg = <0x0 0x7d000000 0x0 0x4000>;
1039                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1040                 phy_type = "utmi";
1041                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1042                 resets = <&tegra_car 22>;
1043                 reset-names = "usb";
1044                 nvidia,phy = <&phy1>;
1045                 status = "disabled";
1046         };
1047
1048         phy1: usb-phy@7d000000 {
1049                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1050                 reg = <0x0 0x7d000000 0x0 0x4000>,
1051                       <0x0 0x7d000000 0x0 0x4000>;
1052                 phy_type = "utmi";
1053                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1054                          <&tegra_car TEGRA124_CLK_PLL_U>,
1055                          <&tegra_car TEGRA124_CLK_USBD>;
1056                 clock-names = "reg", "pll_u", "utmi-pads";
1057                 resets = <&tegra_car 22>, <&tegra_car 22>;
1058                 reset-names = "usb", "utmi-pads";
1059                 nvidia,hssync-start-delay = <0>;
1060                 nvidia,idle-wait-delay = <17>;
1061                 nvidia,elastic-limit = <16>;
1062                 nvidia,term-range-adj = <6>;
1063                 nvidia,xcvr-setup = <9>;
1064                 nvidia,xcvr-lsfslew = <0>;
1065                 nvidia,xcvr-lsrslew = <3>;
1066                 nvidia,hssquelch-level = <2>;
1067                 nvidia,hsdiscon-level = <5>;
1068                 nvidia,xcvr-hsslew = <12>;
1069                 nvidia,has-utmi-pad-registers;
1070                 status = "disabled";
1071         };
1072
1073         usb@7d004000 {
1074                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1075                 reg = <0x0 0x7d004000 0x0 0x4000>;
1076                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1077                 phy_type = "utmi";
1078                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1079                 resets = <&tegra_car 58>;
1080                 reset-names = "usb";
1081                 nvidia,phy = <&phy2>;
1082                 status = "disabled";
1083         };
1084
1085         phy2: usb-phy@7d004000 {
1086                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1087                 reg = <0x0 0x7d004000 0x0 0x4000>,
1088                       <0x0 0x7d000000 0x0 0x4000>;
1089                 phy_type = "utmi";
1090                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1091                          <&tegra_car TEGRA124_CLK_PLL_U>,
1092                          <&tegra_car TEGRA124_CLK_USBD>;
1093                 clock-names = "reg", "pll_u", "utmi-pads";
1094                 resets = <&tegra_car 58>, <&tegra_car 22>;
1095                 reset-names = "usb", "utmi-pads";
1096                 nvidia,hssync-start-delay = <0>;
1097                 nvidia,idle-wait-delay = <17>;
1098                 nvidia,elastic-limit = <16>;
1099                 nvidia,term-range-adj = <6>;
1100                 nvidia,xcvr-setup = <9>;
1101                 nvidia,xcvr-lsfslew = <0>;
1102                 nvidia,xcvr-lsrslew = <3>;
1103                 nvidia,hssquelch-level = <2>;
1104                 nvidia,hsdiscon-level = <5>;
1105                 nvidia,xcvr-hsslew = <12>;
1106                 status = "disabled";
1107         };
1108
1109         usb@7d008000 {
1110                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1111                 reg = <0x0 0x7d008000 0x0 0x4000>;
1112                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1113                 phy_type = "utmi";
1114                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1115                 resets = <&tegra_car 59>;
1116                 reset-names = "usb";
1117                 nvidia,phy = <&phy3>;
1118                 status = "disabled";
1119         };
1120
1121         phy3: usb-phy@7d008000 {
1122                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1123                 reg = <0x0 0x7d008000 0x0 0x4000>,
1124                       <0x0 0x7d000000 0x0 0x4000>;
1125                 phy_type = "utmi";
1126                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1127                          <&tegra_car TEGRA124_CLK_PLL_U>,
1128                          <&tegra_car TEGRA124_CLK_USBD>;
1129                 clock-names = "reg", "pll_u", "utmi-pads";
1130                 resets = <&tegra_car 59>, <&tegra_car 22>;
1131                 reset-names = "usb", "utmi-pads";
1132                 nvidia,hssync-start-delay = <0>;
1133                 nvidia,idle-wait-delay = <17>;
1134                 nvidia,elastic-limit = <16>;
1135                 nvidia,term-range-adj = <6>;
1136                 nvidia,xcvr-setup = <9>;
1137                 nvidia,xcvr-lsfslew = <0>;
1138                 nvidia,xcvr-lsrslew = <3>;
1139                 nvidia,hssquelch-level = <2>;
1140                 nvidia,hsdiscon-level = <5>;
1141                 nvidia,xcvr-hsslew = <12>;
1142                 status = "disabled";
1143         };
1144
1145         cpus {
1146                 #address-cells = <1>;
1147                 #size-cells = <0>;
1148
1149                 cpu@0 {
1150                         device_type = "cpu";
1151                         compatible = "arm,cortex-a15";
1152                         reg = <0>;
1153
1154                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1155                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
1156                                  <&tegra_car TEGRA124_CLK_PLL_X>,
1157                                  <&tegra_car TEGRA124_CLK_PLL_P>,
1158                                  <&dfll>;
1159                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1160                         /* FIXME: what's the actual transition time? */
1161                         clock-latency = <300000>;
1162                 };
1163
1164                 cpu@1 {
1165                         device_type = "cpu";
1166                         compatible = "arm,cortex-a15";
1167                         reg = <1>;
1168                 };
1169
1170                 cpu@2 {
1171                         device_type = "cpu";
1172                         compatible = "arm,cortex-a15";
1173                         reg = <2>;
1174                 };
1175
1176                 cpu@3 {
1177                         device_type = "cpu";
1178                         compatible = "arm,cortex-a15";
1179                         reg = <3>;
1180                 };
1181         };
1182
1183         pmu {
1184                 compatible = "arm,cortex-a15-pmu";
1185                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1186                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1187                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1188                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1189                 interrupt-affinity = <&{/cpus/cpu@0}>,
1190                                      <&{/cpus/cpu@1}>,
1191                                      <&{/cpus/cpu@2}>,
1192                                      <&{/cpus/cpu@3}>;
1193         };
1194
1195         thermal-zones {
1196                 cpu {
1197                         polling-delay-passive = <1000>;
1198                         polling-delay = <1000>;
1199
1200                         thermal-sensors =
1201                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1202
1203                         trips {
1204                                 cpu-shutdown-trip {
1205                                         temperature = <103000>;
1206                                         hysteresis = <0>;
1207                                         type = "critical";
1208                                 };
1209                                 cpu_throttle_trip: throttle-trip {
1210                                         temperature = <100000>;
1211                                         hysteresis = <1000>;
1212                                         type = "hot";
1213                                 };
1214                         };
1215
1216                         cooling-maps {
1217                                 map0 {
1218                                         trip = <&cpu_throttle_trip>;
1219                                         cooling-device = <&throttle_heavy 1 1>;
1220                                 };
1221                         };
1222                 };
1223
1224                 mem {
1225                         polling-delay-passive = <1000>;
1226                         polling-delay = <1000>;
1227
1228                         thermal-sensors =
1229                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1230
1231                         trips {
1232                                 mem-shutdown-trip {
1233                                         temperature = <103000>;
1234                                         hysteresis = <0>;
1235                                         type = "critical";
1236                                 };
1237                         };
1238
1239                         cooling-maps {
1240                                 /*
1241                                  * There are currently no cooling maps,
1242                                  * because there are no cooling devices.
1243                                  */
1244                         };
1245                 };
1246
1247                 gpu {
1248                         polling-delay-passive = <1000>;
1249                         polling-delay = <1000>;
1250
1251                         thermal-sensors =
1252                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1253
1254                         trips {
1255                                 gpu-shutdown-trip {
1256                                         temperature = <101000>;
1257                                         hysteresis = <0>;
1258                                         type = "critical";
1259                                 };
1260                                 gpu_throttle_trip: throttle-trip {
1261                                         temperature = <99000>;
1262                                         hysteresis = <1000>;
1263                                         type = "hot";
1264                                 };
1265                         };
1266
1267                         cooling-maps {
1268                                 map0 {
1269                                         trip = <&gpu_throttle_trip>;
1270                                         cooling-device = <&throttle_heavy 1 1>;
1271                                 };
1272                         };
1273                 };
1274
1275                 pllx {
1276                         polling-delay-passive = <1000>;
1277                         polling-delay = <1000>;
1278
1279                         thermal-sensors =
1280                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1281
1282                         trips {
1283                                 pllx-shutdown-trip {
1284                                         temperature = <103000>;
1285                                         hysteresis = <0>;
1286                                         type = "critical";
1287                                 };
1288                         };
1289
1290                         cooling-maps {
1291                                 /*
1292                                  * There are currently no cooling maps,
1293                                  * because there are no cooling devices.
1294                                  */
1295                         };
1296                 };
1297         };
1298
1299         timer {
1300                 compatible = "arm,armv7-timer";
1301                 interrupts = <GIC_PPI 13
1302                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1303                              <GIC_PPI 14
1304                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1305                              <GIC_PPI 11
1306                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1307                              <GIC_PPI 10
1308                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1309                 interrupt-parent = <&gic>;
1310         };
1311 };