arch/arm/boot/dts/tegra114.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra114-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra114-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8
   9 / {
  10         compatible = "nvidia,tegra114";
  11         interrupt-parent = <&lic>;
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x80000000 0x0>;
  18         };
  19
  20         host1x@50000000 {
  21                 compatible = "nvidia,tegra114-host1x", "simple-bus";
  22                 reg = <0x50000000 0x00028000>;
  23                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  24                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  25                 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
  26                 resets = <&tegra_car 28>;
  27                 reset-names = "host1x";
  28                 iommus = <&mc TEGRA_SWGROUP_HC>;
  29
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32
  33                 ranges = <0x54000000 0x54000000 0x01000000>;
  34
  35                 gr2d@54140000 {
  36                         compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
  37                         reg = <0x54140000 0x00040000>;
  38                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  39                         clocks = <&tegra_car TEGRA114_CLK_GR2D>;
  40                         resets = <&tegra_car 21>;
  41                         reset-names = "2d";
  42
  43                         iommus = <&mc TEGRA_SWGROUP_G2>;
  44                 };
  45
  46                 gr3d@54180000 {
  47                         compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
  48                         reg = <0x54180000 0x00040000>;
  49                         clocks = <&tegra_car TEGRA114_CLK_GR3D>;
  50                         resets = <&tegra_car 24>;
  51                         reset-names = "3d";
  52
  53                         iommus = <&mc TEGRA_SWGROUP_NV>;
  54                 };
  55
  56                 dc@54200000 {
  57                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  58                         reg = <0x54200000 0x00040000>;
  59                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  60                         clocks = <&tegra_car TEGRA114_CLK_DISP1>,
  61                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  62                         clock-names = "dc", "parent";
  63                         resets = <&tegra_car 27>;
  64                         reset-names = "dc";
  65
  66                         iommus = <&mc TEGRA_SWGROUP_DC>;
  67
  68                         nvidia,head = <0>;
  69
  70                         rgb {
  71                                 status = "disabled";
  72                         };
  73                 };
  74
  75                 dc@54240000 {
  76                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  77                         reg = <0x54240000 0x00040000>;
  78                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  79                         clocks = <&tegra_car TEGRA114_CLK_DISP2>,
  80                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  81                         clock-names = "dc", "parent";
  82                         resets = <&tegra_car 26>;
  83                         reset-names = "dc";
  84
  85                         iommus = <&mc TEGRA_SWGROUP_DCB>;
  86
  87                         nvidia,head = <1>;
  88
  89                         rgb {
  90                                 status = "disabled";
  91                         };
  92                 };
  93
  94                 hdmi@54280000 {
  95                         compatible = "nvidia,tegra114-hdmi";
  96                         reg = <0x54280000 0x00040000>;
  97                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  98                         clocks = <&tegra_car TEGRA114_CLK_HDMI>,
  99                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
 100                         clock-names = "hdmi", "parent";
 101                         resets = <&tegra_car 51>;
 102                         reset-names = "hdmi";
 103                         status = "disabled";
 104                 };
 105
 106                 dsi@54300000 {
 107                         compatible = "nvidia,tegra114-dsi";
 108                         reg = <0x54300000 0x00040000>;
 109                         clocks = <&tegra_car TEGRA114_CLK_DSIA>,
 110                                  <&tegra_car TEGRA114_CLK_DSIALP>,
 111                                  <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
 112                         clock-names = "dsi", "lp", "parent";
 113                         resets = <&tegra_car 48>;
 114                         reset-names = "dsi";
 115                         nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
 116                         status = "disabled";
 117
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                 };
 121
 122                 dsi@54400000 {
 123                         compatible = "nvidia,tegra114-dsi";
 124                         reg = <0x54400000 0x00040000>;
 125                         clocks = <&tegra_car TEGRA114_CLK_DSIB>,
 126                                  <&tegra_car TEGRA114_CLK_DSIBLP>,
 127                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
 128                         clock-names = "dsi", "lp", "parent";
 129                         resets = <&tegra_car 82>;
 130                         reset-names = "dsi";
 131                         nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
 132                         status = "disabled";
 133
 134                         #address-cells = <1>;
 135                         #size-cells = <0>;
 136                 };
 137         };
 138
 139         gic: interrupt-controller@50041000 {
 140                 compatible = "arm,cortex-a15-gic";
 141                 #interrupt-cells = <3>;
 142                 interrupt-controller;
 143                 reg = <0x50041000 0x1000>,
 144                       <0x50042000 0x1000>,
 145                       <0x50044000 0x2000>,
 146                       <0x50046000 0x2000>;
 147                 interrupts = <GIC_PPI 9
 148                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149                 interrupt-parent = <&gic>;
 150         };
 151
 152         lic: interrupt-controller@60004000 {
 153                 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
 154                 reg = <0x60004000 0x100>,
 155                       <0x60004100 0x50>,
 156                       <0x60004200 0x50>,
 157                       <0x60004300 0x50>,
 158                       <0x60004400 0x50>;
 159                 interrupt-controller;
 160                 #interrupt-cells = <3>;
 161                 interrupt-parent = <&gic>;
 162         };
 163
 164         timer@60005000 {
 165                 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 166                 reg = <0x60005000 0x400>;
 167                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 174         };
 175
 176         tegra_car: clock@60006000 {
 177                 compatible = "nvidia,tegra114-car";
 178                 reg = <0x60006000 0x1000>;
 179                 #clock-cells = <1>;
 180                 #reset-cells = <1>;
 181         };
 182
 183         flow-controller@60007000 {
 184                 compatible = "nvidia,tegra114-flowctrl";
 185                 reg = <0x60007000 0x1000>;
 186         };
 187
 188         apbdma: dma@6000a000 {
 189                 compatible = "nvidia,tegra114-apbdma";
 190                 reg = <0x6000a000 0x1400>;
 191                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 217                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 218                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 224                 resets = <&tegra_car 34>;
 225                 reset-names = "dma";
 226                 #dma-cells = <1>;
 227         };
 228
 229         ahb: ahb@6000c000 {
 230                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
 231                 reg = <0x6000c000 0x150>;
 232         };
 233
 234         gpio: gpio@6000d000 {
 235                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 236                 reg = <0x6000d000 0x1000>;
 237                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 243                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 244                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 245                 #gpio-cells = <2>;
 246                 gpio-controller;
 247                 #interrupt-cells = <2>;
 248                 interrupt-controller;
 249                 /*
 250                 gpio-ranges = <&pinmux 0 0 246>;
 251                 */
 252         };
 253
 254         apbmisc@70000800 {
 255                 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
 256                 reg = <0x70000800 0x64   /* Chip revision */
 257                        0x70000008 0x04>; /* Strapping options */
 258         };
 259
 260         pinmux: pinmux@70000868 {
 261                 compatible = "nvidia,tegra114-pinmux";
 262                 reg = <0x70000868 0x148         /* Pad control registers */
 263                        0x70003000 0x40c>;       /* Mux registers */
 264         };
 265
 266         /*
 267          * There are two serial driver i.e. 8250 based simple serial
 268          * driver and APB DMA based serial driver for higher baudrate
 269          * and performace. To enable the 8250 based driver, the compatible
 270          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 271          * the APB DMA based serial driver, the compatible is
 272          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 273          */
 274         uarta: serial@70006000 {
 275                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 276                 reg = <0x70006000 0x40>;
 277                 reg-shift = <2>;
 278                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 280                 resets = <&tegra_car 6>;
 281                 reset-names = "serial";
 282                 dmas = <&apbdma 8>, <&apbdma 8>;
 283                 dma-names = "rx", "tx";
 284                 status = "disabled";
 285         };
 286
 287         uartb: serial@70006040 {
 288                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 289                 reg = <0x70006040 0x40>;
 290                 reg-shift = <2>;
 291                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 292                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 293                 resets = <&tegra_car 7>;
 294                 reset-names = "serial";
 295                 dmas = <&apbdma 9>, <&apbdma 9>;
 296                 dma-names = "rx", "tx";
 297                 status = "disabled";
 298         };
 299
 300         uartc: serial@70006200 {
 301                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 302                 reg = <0x70006200 0x100>;
 303                 reg-shift = <2>;
 304                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 305                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 306                 resets = <&tegra_car 55>;
 307                 reset-names = "serial";
 308                 dmas = <&apbdma 10>, <&apbdma 10>;
 309                 dma-names = "rx", "tx";
 310                 status = "disabled";
 311         };
 312
 313         uartd: serial@70006300 {
 314                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 315                 reg = <0x70006300 0x100>;
 316                 reg-shift = <2>;
 317                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 319                 resets = <&tegra_car 65>;
 320                 reset-names = "serial";
 321                 dmas = <&apbdma 19>, <&apbdma 19>;
 322                 dma-names = "rx", "tx";
 323                 status = "disabled";
 324         };
 325
 326         pwm: pwm@7000a000 {
 327                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 328                 reg = <0x7000a000 0x100>;
 329                 #pwm-cells = <2>;
 330                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
 331                 resets = <&tegra_car 17>;
 332                 reset-names = "pwm";
 333                 status = "disabled";
 334         };
 335
 336         i2c@7000c000 {
 337                 compatible = "nvidia,tegra114-i2c";
 338                 reg = <0x7000c000 0x100>;
 339                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 343                 clock-names = "div-clk";
 344                 resets = <&tegra_car 12>;
 345                 reset-names = "i2c";
 346                 dmas = <&apbdma 21>, <&apbdma 21>;
 347                 dma-names = "rx", "tx";
 348                 status = "disabled";
 349         };
 350
 351         i2c@7000c400 {
 352                 compatible = "nvidia,tegra114-i2c";
 353                 reg = <0x7000c400 0x100>;
 354                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 358                 clock-names = "div-clk";
 359                 resets = <&tegra_car 54>;
 360                 reset-names = "i2c";
 361                 dmas = <&apbdma 22>, <&apbdma 22>;
 362                 dma-names = "rx", "tx";
 363                 status = "disabled";
 364         };
 365
 366         i2c@7000c500 {
 367                 compatible = "nvidia,tegra114-i2c";
 368                 reg = <0x7000c500 0x100>;
 369                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 373                 clock-names = "div-clk";
 374                 resets = <&tegra_car 67>;
 375                 reset-names = "i2c";
 376                 dmas = <&apbdma 23>, <&apbdma 23>;
 377                 dma-names = "rx", "tx";
 378                 status = "disabled";
 379         };
 380
 381         i2c@7000c700 {
 382                 compatible = "nvidia,tegra114-i2c";
 383                 reg = <0x7000c700 0x100>;
 384                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 388                 clock-names = "div-clk";
 389                 resets = <&tegra_car 103>;
 390                 reset-names = "i2c";
 391                 dmas = <&apbdma 26>, <&apbdma 26>;
 392                 dma-names = "rx", "tx";
 393                 status = "disabled";
 394         };
 395
 396         i2c@7000d000 {
 397                 compatible = "nvidia,tegra114-i2c";
 398                 reg = <0x7000d000 0x100>;
 399                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 403                 clock-names = "div-clk";
 404                 resets = <&tegra_car 47>;
 405                 reset-names = "i2c";
 406                 dmas = <&apbdma 24>, <&apbdma 24>;
 407                 dma-names = "rx", "tx";
 408                 status = "disabled";
 409         };
 410
 411         spi@7000d400 {
 412                 compatible = "nvidia,tegra114-spi";
 413                 reg = <0x7000d400 0x200>;
 414                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 418                 clock-names = "spi";
 419                 resets = <&tegra_car 41>;
 420                 reset-names = "spi";
 421                 dmas = <&apbdma 15>, <&apbdma 15>;
 422                 dma-names = "rx", "tx";
 423                 status = "disabled";
 424         };
 425
 426         spi@7000d600 {
 427                 compatible = "nvidia,tegra114-spi";
 428                 reg = <0x7000d600 0x200>;
 429                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 433                 clock-names = "spi";
 434                 resets = <&tegra_car 44>;
 435                 reset-names = "spi";
 436                 dmas = <&apbdma 16>, <&apbdma 16>;
 437                 dma-names = "rx", "tx";
 438                 status = "disabled";
 439         };
 440
 441         spi@7000d800 {
 442                 compatible = "nvidia,tegra114-spi";
 443                 reg = <0x7000d800 0x200>;
 444                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 448                 clock-names = "spi";
 449                 resets = <&tegra_car 46>;
 450                 reset-names = "spi";
 451                 dmas = <&apbdma 17>, <&apbdma 17>;
 452                 dma-names = "rx", "tx";
 453                 status = "disabled";
 454         };
 455
 456         spi@7000da00 {
 457                 compatible = "nvidia,tegra114-spi";
 458                 reg = <0x7000da00 0x200>;
 459                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 463                 clock-names = "spi";
 464                 resets = <&tegra_car 68>;
 465                 reset-names = "spi";
 466                 dmas = <&apbdma 18>, <&apbdma 18>;
 467                 dma-names = "rx", "tx";
 468                 status = "disabled";
 469         };
 470
 471         spi@7000dc00 {
 472                 compatible = "nvidia,tegra114-spi";
 473                 reg = <0x7000dc00 0x200>;
 474                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 478                 clock-names = "spi";
 479                 resets = <&tegra_car 104>;
 480                 reset-names = "spi";
 481                 dmas = <&apbdma 27>, <&apbdma 27>;
 482                 dma-names = "rx", "tx";
 483                 status = "disabled";
 484         };
 485
 486         spi@7000de00 {
 487                 compatible = "nvidia,tegra114-spi";
 488                 reg = <0x7000de00 0x200>;
 489                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 493                 clock-names = "spi";
 494                 resets = <&tegra_car 105>;
 495                 reset-names = "spi";
 496                 dmas = <&apbdma 28>, <&apbdma 28>;
 497                 dma-names = "rx", "tx";
 498                 status = "disabled";
 499         };
 500
 501         rtc@7000e000 {
 502                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 503                 reg = <0x7000e000 0x100>;
 504                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
 506         };
 507
 508         kbc@7000e200 {
 509                 compatible = "nvidia,tegra114-kbc";
 510                 reg = <0x7000e200 0x100>;
 511                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
 513                 resets = <&tegra_car 36>;
 514                 reset-names = "kbc";
 515                 status = "disabled";
 516         };
 517
 518         tegra_pmc: pmc@7000e400 {
 519                 compatible = "nvidia,tegra114-pmc";
 520                 reg = <0x7000e400 0x400>;
 521                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 522                 clock-names = "pclk", "clk32k_in";
 523                 #clock-cells = <1>;
 524         };
 525
 526         fuse@7000f800 {
 527                 compatible = "nvidia,tegra114-efuse";
 528                 reg = <0x7000f800 0x400>;
 529                 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
 530                 clock-names = "fuse";
 531                 resets = <&tegra_car 39>;
 532                 reset-names = "fuse";
 533         };
 534
 535         mc: memory-controller@70019000 {
 536                 compatible = "nvidia,tegra114-mc";
 537                 reg = <0x70019000 0x1000>;
 538                 clocks = <&tegra_car TEGRA114_CLK_MC>;
 539                 clock-names = "mc";
 540
 541                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 542
 543                 #iommu-cells = <1>;
 544         };
 545
 546         ahub@70080000 {
 547                 compatible = "nvidia,tegra114-ahub";
 548                 reg = <0x70080000 0x200>,
 549                       <0x70080200 0x100>,
 550                       <0x70081000 0x200>;
 551                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 552                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 553                          <&tegra_car TEGRA114_CLK_APBIF>;
 554                 clock-names = "d_audio", "apbif";
 555                 resets = <&tegra_car 106>, /* d_audio */
 556                          <&tegra_car 107>, /* apbif */
 557                          <&tegra_car 30>,  /* i2s0 */
 558                          <&tegra_car 11>,  /* i2s1 */
 559                          <&tegra_car 18>,  /* i2s2 */
 560                          <&tegra_car 101>, /* i2s3 */
 561                          <&tegra_car 102>, /* i2s4 */
 562                          <&tegra_car 108>, /* dam0 */
 563                          <&tegra_car 109>, /* dam1 */
 564                          <&tegra_car 110>, /* dam2 */
 565                          <&tegra_car 10>,  /* spdif */
 566                          <&tegra_car 153>, /* amx */
 567                          <&tegra_car 154>; /* adx */
 568                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 569                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 570                               "spdif", "amx", "adx";
 571                 dmas = <&apbdma 1>, <&apbdma 1>,
 572                        <&apbdma 2>, <&apbdma 2>,
 573                        <&apbdma 3>, <&apbdma 3>,
 574                        <&apbdma 4>, <&apbdma 4>,
 575                        <&apbdma 6>, <&apbdma 6>,
 576                        <&apbdma 7>, <&apbdma 7>,
 577                        <&apbdma 12>, <&apbdma 12>,
 578                        <&apbdma 13>, <&apbdma 13>,
 579                        <&apbdma 14>, <&apbdma 14>,
 580                        <&apbdma 29>, <&apbdma 29>;
 581                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 582                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 583                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 584                             "rx9", "tx9";
 585                 ranges;
 586                 #address-cells = <1>;
 587                 #size-cells = <1>;
 588
 589                 tegra_i2s0: i2s@70080300 {
 590                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 591                         reg = <0x70080300 0x100>;
 592                         nvidia,ahub-cif-ids = <4 4>;
 593                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 594                         resets = <&tegra_car 30>;
 595                         reset-names = "i2s";
 596                         status = "disabled";
 597                 };
 598
 599                 tegra_i2s1: i2s@70080400 {
 600                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 601                         reg = <0x70080400 0x100>;
 602                         nvidia,ahub-cif-ids = <5 5>;
 603                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 604                         resets = <&tegra_car 11>;
 605                         reset-names = "i2s";
 606                         status = "disabled";
 607                 };
 608
 609                 tegra_i2s2: i2s@70080500 {
 610                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 611                         reg = <0x70080500 0x100>;
 612                         nvidia,ahub-cif-ids = <6 6>;
 613                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 614                         resets = <&tegra_car 18>;
 615                         reset-names = "i2s";
 616                         status = "disabled";
 617                 };
 618
 619                 tegra_i2s3: i2s@70080600 {
 620                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 621                         reg = <0x70080600 0x100>;
 622                         nvidia,ahub-cif-ids = <7 7>;
 623                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 624                         resets = <&tegra_car 101>;
 625                         reset-names = "i2s";
 626                         status = "disabled";
 627                 };
 628
 629                 tegra_i2s4: i2s@70080700 {
 630                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 631                         reg = <0x70080700 0x100>;
 632                         nvidia,ahub-cif-ids = <8 8>;
 633                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 634                         resets = <&tegra_car 102>;
 635                         reset-names = "i2s";
 636                         status = "disabled";
 637                 };
 638         };
 639
 640         mipi: mipi@700e3000 {
 641                 compatible = "nvidia,tegra114-mipi";
 642                 reg = <0x700e3000 0x100>;
 643                 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
 644                 #nvidia,mipi-calibrate-cells = <1>;
 645         };
 646
 647         sdhci@78000000 {
 648                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 649                 reg = <0x78000000 0x200>;
 650                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 652                 resets = <&tegra_car 14>;
 653                 reset-names = "sdhci";
 654                 status = "disabled";
 655         };
 656
 657         sdhci@78000200 {
 658                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 659                 reg = <0x78000200 0x200>;
 660                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 662                 resets = <&tegra_car 9>;
 663                 reset-names = "sdhci";
 664                 status = "disabled";
 665         };
 666
 667         sdhci@78000400 {
 668                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 669                 reg = <0x78000400 0x200>;
 670                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 671                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 672                 resets = <&tegra_car 69>;
 673                 reset-names = "sdhci";
 674                 status = "disabled";
 675         };
 676
 677         sdhci@78000600 {
 678                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 679                 reg = <0x78000600 0x200>;
 680                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 681                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 682                 resets = <&tegra_car 15>;
 683                 reset-names = "sdhci";
 684                 status = "disabled";
 685         };
 686
 687         usb@7d000000 {
 688                 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 689                 reg = <0x7d000000 0x4000>;
 690                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 691                 phy_type = "utmi";
 692                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
 693                 resets = <&tegra_car 22>;
 694                 reset-names = "usb";
 695                 nvidia,phy = <&phy1>;
 696                 status = "disabled";
 697         };
 698
 699         phy1: usb-phy@7d000000 {
 700                 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
 701                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 702                 phy_type = "utmi";
 703                 clocks = <&tegra_car TEGRA114_CLK_USBD>,
 704                          <&tegra_car TEGRA114_CLK_PLL_U>,
 705                          <&tegra_car TEGRA114_CLK_USBD>;
 706                 clock-names = "reg", "pll_u", "utmi-pads";
 707                 resets = <&tegra_car 22>, <&tegra_car 22>;
 708                 reset-names = "usb", "utmi-pads";
 709                 nvidia,hssync-start-delay = <0>;
 710                 nvidia,idle-wait-delay = <17>;
 711                 nvidia,elastic-limit = <16>;
 712                 nvidia,term-range-adj = <6>;
 713                 nvidia,xcvr-setup = <9>;
 714                 nvidia,xcvr-lsfslew = <0>;
 715                 nvidia,xcvr-lsrslew = <3>;
 716                 nvidia,hssquelch-level = <2>;
 717                 nvidia,hsdiscon-level = <5>;
 718                 nvidia,xcvr-hsslew = <12>;
 719                 nvidia,has-utmi-pad-registers;
 720                 status = "disabled";
 721         };
 722
 723         usb@7d008000 {
 724                 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 725                 reg = <0x7d008000 0x4000>;
 726                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 727                 phy_type = "utmi";
 728                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
 729                 resets = <&tegra_car 59>;
 730                 reset-names = "usb";
 731                 nvidia,phy = <&phy3>;
 732                 status = "disabled";
 733         };
 734
 735         phy3: usb-phy@7d008000 {
 736                 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
 737                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 738                 phy_type = "utmi";
 739                 clocks = <&tegra_car TEGRA114_CLK_USB3>,
 740                          <&tegra_car TEGRA114_CLK_PLL_U>,
 741                          <&tegra_car TEGRA114_CLK_USBD>;
 742                 clock-names = "reg", "pll_u", "utmi-pads";
 743                 resets = <&tegra_car 59>, <&tegra_car 22>;
 744                 reset-names = "usb", "utmi-pads";
 745                 nvidia,hssync-start-delay = <0>;
 746                 nvidia,idle-wait-delay = <17>;
 747                 nvidia,elastic-limit = <16>;
 748                 nvidia,term-range-adj = <6>;
 749                 nvidia,xcvr-setup = <9>;
 750                 nvidia,xcvr-lsfslew = <0>;
 751                 nvidia,xcvr-lsrslew = <3>;
 752                 nvidia,hssquelch-level = <2>;
 753                 nvidia,hsdiscon-level = <5>;
 754                 nvidia,xcvr-hsslew = <12>;
 755                 status = "disabled";
 756         };
 757
 758         cpus {
 759                 #address-cells = <1>;
 760                 #size-cells = <0>;
 761
 762                 cpu@0 {
 763                         device_type = "cpu";
 764                         compatible = "arm,cortex-a15";
 765                         reg = <0>;
 766                 };
 767
 768                 cpu@1 {
 769                         device_type = "cpu";
 770                         compatible = "arm,cortex-a15";
 771                         reg = <1>;
 772                 };
 773
 774                 cpu@2 {
 775                         device_type = "cpu";
 776                         compatible = "arm,cortex-a15";
 777                         reg = <2>;
 778                 };
 779
 780                 cpu@3 {
 781                         device_type = "cpu";
 782                         compatible = "arm,cortex-a15";
 783                         reg = <3>;
 784                 };
 785         };
 786
 787         timer {
 788                 compatible = "arm,armv7-timer";
 789                 interrupts =
 790                         <GIC_PPI 13
 791                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 792                         <GIC_PPI 14
 793                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 794                         <GIC_PPI 11
 795                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 796                         <GIC_PPI 10
 797                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 798                 interrupt-parent = <&gic>;
 799         };
 800 };