2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/sun8i-de2.h>
44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/reset/sun8i-de2.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
52 interrupt-parent = <&gic>;
62 compatible = "allwinner,simple-framebuffer",
64 allwinner,pipeline = "mixer0-lcd0-hdmi";
65 clocks = <&display_clocks CLK_MIXER0>,
66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
71 compatible = "allwinner,simple-framebuffer",
73 allwinner,pipeline = "mixer1-lcd1-tve";
74 clocks = <&display_clocks CLK_MIXER1>,
87 compatible = "fixed-clock";
88 clock-frequency = <24000000>;
89 clock-output-names = "osc24M";
94 compatible = "fixed-clock";
95 clock-frequency = <32768>;
96 clock-output-names = "osc32k";
99 iosc: internal-osc-clk {
101 compatible = "fixed-clock";
102 clock-frequency = <16000000>;
103 clock-accuracy = <300000000>;
104 clock-output-names = "iosc";
109 compatible = "simple-bus";
110 #address-cells = <1>;
114 display_clocks: clock@1000000 {
115 /* compatible is in per SoC .dtsi file */
116 reg = <0x01000000 0x100000>;
117 clocks = <&ccu CLK_DE>,
121 resets = <&ccu RST_BUS_DE>;
126 syscon: syscon@1c00000 {
127 compatible = "allwinner,sun8i-h3-system-controller",
129 reg = <0x01c00000 0x1000>;
132 dma: dma-controller@1c02000 {
133 compatible = "allwinner,sun8i-h3-dma";
134 reg = <0x01c02000 0x1000>;
135 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&ccu CLK_BUS_DMA>;
137 resets = <&ccu RST_BUS_DMA>;
142 /* compatible and clocks are in per SoC .dtsi file */
143 reg = <0x01c0f000 0x1000>;
144 resets = <&ccu RST_BUS_MMC0>;
146 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
148 #address-cells = <1>;
153 /* compatible and clocks are in per SoC .dtsi file */
154 reg = <0x01c10000 0x1000>;
155 resets = <&ccu RST_BUS_MMC1>;
157 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
159 #address-cells = <1>;
164 /* compatible and clocks are in per SoC .dtsi file */
165 reg = <0x01c11000 0x1000>;
166 resets = <&ccu RST_BUS_MMC2>;
168 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
170 #address-cells = <1>;
174 usb_otg: usb@1c19000 {
175 compatible = "allwinner,sun8i-h3-musb";
176 reg = <0x01c19000 0x400>;
177 clocks = <&ccu CLK_BUS_OTG>;
178 resets = <&ccu RST_BUS_OTG>;
179 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "mc";
183 extcon = <&usbphy 0>;
187 usbphy: phy@1c19400 {
188 compatible = "allwinner,sun8i-h3-usb-phy";
189 reg = <0x01c19400 0x2c>,
194 reg-names = "phy_ctrl",
199 clocks = <&ccu CLK_USB_PHY0>,
203 clock-names = "usb0_phy",
207 resets = <&ccu RST_USB_PHY0>,
211 reset-names = "usb0_reset",
220 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
221 reg = <0x01c1a000 0x100>;
222 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
224 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
229 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
230 reg = <0x01c1a400 0x100>;
231 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
233 <&ccu CLK_USB_OHCI0>;
234 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
239 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
240 reg = <0x01c1b000 0x100>;
241 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
243 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
250 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
251 reg = <0x01c1b400 0x100>;
252 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
254 <&ccu CLK_USB_OHCI1>;
255 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
262 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
263 reg = <0x01c1c000 0x100>;
264 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
266 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
273 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
274 reg = <0x01c1c400 0x100>;
275 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
277 <&ccu CLK_USB_OHCI2>;
278 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
285 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
286 reg = <0x01c1d000 0x100>;
287 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
289 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
296 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
297 reg = <0x01c1d400 0x100>;
298 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
300 <&ccu CLK_USB_OHCI3>;
301 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
308 /* compatible is in per SoC .dtsi file */
309 reg = <0x01c20000 0x400>;
310 clocks = <&osc24M>, <&osc32k>;
311 clock-names = "hosc", "losc";
316 pio: pinctrl@1c20800 {
317 /* compatible is in per SoC .dtsi file */
318 reg = <0x01c20800 0x400>;
319 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
322 clock-names = "apb", "hosc", "losc";
325 interrupt-controller;
326 #interrupt-cells = <3>;
328 emac_rgmii_pins: emac0 {
329 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
330 "PD5", "PD7", "PD8", "PD9", "PD10",
331 "PD12", "PD13", "PD15", "PD16", "PD17";
333 drive-strength = <40>;
337 pins = "PA11", "PA12";
342 pins = "PA18", "PA19";
347 pins = "PE12", "PE13";
352 pins = "PF0", "PF1", "PF2", "PF3",
355 drive-strength = <30>;
359 mmc0_cd_pin: mmc0_cd_pin {
361 function = "gpio_in";
366 pins = "PG0", "PG1", "PG2", "PG3",
369 drive-strength = <30>;
373 mmc2_8bit_pins: mmc2_8bit {
374 pins = "PC5", "PC6", "PC8",
375 "PC9", "PC10", "PC11",
376 "PC12", "PC13", "PC14",
379 drive-strength = <30>;
383 spdif_tx_pins_a: spdif {
389 pins = "PC0", "PC1", "PC2", "PC3";
394 pins = "PA15", "PA16", "PA14", "PA13";
398 uart0_pins_a: uart0 {
408 uart1_rts_cts_pins: uart1_rts_cts {
419 pins = "PA13", "PA14";
423 uart3_rts_cts_pins: uart3_rts_cts {
424 pins = "PA15", "PA16";
430 compatible = "allwinner,sun4i-a10-timer";
431 reg = <0x01c20c00 0xa0>;
432 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
437 emac: ethernet@1c30000 {
438 compatible = "allwinner,sun8i-h3-emac";
440 reg = <0x01c30000 0x10000>;
441 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-names = "macirq";
443 resets = <&ccu RST_BUS_EMAC>;
444 reset-names = "stmmaceth";
445 clocks = <&ccu CLK_BUS_EMAC>;
446 clock-names = "stmmaceth";
447 #address-cells = <1>;
452 #address-cells = <1>;
454 compatible = "snps,dwmac-mdio";
458 compatible = "allwinner,sun8i-h3-mdio-mux";
459 #address-cells = <1>;
462 mdio-parent-bus = <&mdio>;
463 /* Only one MDIO is usable at the time */
464 internal_mdio: mdio@1 {
465 compatible = "allwinner,sun8i-h3-mdio-internal";
467 #address-cells = <1>;
470 int_mii_phy: ethernet-phy@1 {
471 compatible = "ethernet-phy-ieee802.3-c22";
473 clocks = <&ccu CLK_BUS_EPHY>;
474 resets = <&ccu RST_BUS_EPHY>;
478 external_mdio: mdio@2 {
480 #address-cells = <1>;
487 compatible = "allwinner,sun8i-h3-spi";
488 reg = <0x01c68000 0x1000>;
489 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
491 clock-names = "ahb", "mod";
492 dmas = <&dma 23>, <&dma 23>;
493 dma-names = "rx", "tx";
494 pinctrl-names = "default";
495 pinctrl-0 = <&spi0_pins>;
496 resets = <&ccu RST_BUS_SPI0>;
498 #address-cells = <1>;
503 compatible = "allwinner,sun8i-h3-spi";
504 reg = <0x01c69000 0x1000>;
505 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
507 clock-names = "ahb", "mod";
508 dmas = <&dma 24>, <&dma 24>;
509 dma-names = "rx", "tx";
510 pinctrl-names = "default";
511 pinctrl-0 = <&spi1_pins>;
512 resets = <&ccu RST_BUS_SPI1>;
514 #address-cells = <1>;
518 wdt0: watchdog@1c20ca0 {
519 compatible = "allwinner,sun6i-a31-wdt";
520 reg = <0x01c20ca0 0x20>;
521 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
524 spdif: spdif@1c21000 {
525 #sound-dai-cells = <0>;
526 compatible = "allwinner,sun8i-h3-spdif";
527 reg = <0x01c21000 0x400>;
528 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
530 resets = <&ccu RST_BUS_SPDIF>;
531 clock-names = "apb", "spdif";
538 compatible = "allwinner,sun8i-h3-pwm";
539 reg = <0x01c21400 0x8>;
546 #sound-dai-cells = <0>;
547 compatible = "allwinner,sun8i-h3-i2s";
548 reg = <0x01c22000 0x400>;
549 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
551 clock-names = "apb", "mod";
552 dmas = <&dma 3>, <&dma 3>;
553 resets = <&ccu RST_BUS_I2S0>;
554 dma-names = "rx", "tx";
559 #sound-dai-cells = <0>;
560 compatible = "allwinner,sun8i-h3-i2s";
561 reg = <0x01c22400 0x400>;
562 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
564 clock-names = "apb", "mod";
565 dmas = <&dma 4>, <&dma 4>;
566 resets = <&ccu RST_BUS_I2S1>;
567 dma-names = "rx", "tx";
571 codec: codec@1c22c00 {
572 #sound-dai-cells = <0>;
573 compatible = "allwinner,sun8i-h3-codec";
574 reg = <0x01c22c00 0x400>;
575 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
577 clock-names = "apb", "codec";
578 resets = <&ccu RST_BUS_CODEC>;
579 dmas = <&dma 15>, <&dma 15>;
580 dma-names = "rx", "tx";
581 allwinner,codec-analog-controls = <&codec_analog>;
585 uart0: serial@1c28000 {
586 compatible = "snps,dw-apb-uart";
587 reg = <0x01c28000 0x400>;
588 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&ccu CLK_BUS_UART0>;
592 resets = <&ccu RST_BUS_UART0>;
593 dmas = <&dma 6>, <&dma 6>;
594 dma-names = "rx", "tx";
598 uart1: serial@1c28400 {
599 compatible = "snps,dw-apb-uart";
600 reg = <0x01c28400 0x400>;
601 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&ccu CLK_BUS_UART1>;
605 resets = <&ccu RST_BUS_UART1>;
606 dmas = <&dma 7>, <&dma 7>;
607 dma-names = "rx", "tx";
611 uart2: serial@1c28800 {
612 compatible = "snps,dw-apb-uart";
613 reg = <0x01c28800 0x400>;
614 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&ccu CLK_BUS_UART2>;
618 resets = <&ccu RST_BUS_UART2>;
619 dmas = <&dma 8>, <&dma 8>;
620 dma-names = "rx", "tx";
624 uart3: serial@1c28c00 {
625 compatible = "snps,dw-apb-uart";
626 reg = <0x01c28c00 0x400>;
627 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&ccu CLK_BUS_UART3>;
631 resets = <&ccu RST_BUS_UART3>;
632 dmas = <&dma 9>, <&dma 9>;
633 dma-names = "rx", "tx";
638 compatible = "allwinner,sun6i-a31-i2c";
639 reg = <0x01c2ac00 0x400>;
640 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&ccu CLK_BUS_I2C0>;
642 resets = <&ccu RST_BUS_I2C0>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2c0_pins>;
646 #address-cells = <1>;
651 compatible = "allwinner,sun6i-a31-i2c";
652 reg = <0x01c2b000 0x400>;
653 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&ccu CLK_BUS_I2C1>;
655 resets = <&ccu RST_BUS_I2C1>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&i2c1_pins>;
659 #address-cells = <1>;
664 compatible = "allwinner,sun6i-a31-i2c";
665 reg = <0x01c2b400 0x400>;
666 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&ccu CLK_BUS_I2C2>;
668 resets = <&ccu RST_BUS_I2C2>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&i2c2_pins>;
672 #address-cells = <1>;
676 gic: interrupt-controller@1c81000 {
677 compatible = "arm,gic-400";
678 reg = <0x01c81000 0x1000>,
682 interrupt-controller;
683 #interrupt-cells = <3>;
684 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
688 compatible = "allwinner,sun6i-a31-rtc";
689 reg = <0x01f00000 0x54>;
690 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
694 r_ccu: clock@1f01400 {
695 compatible = "allwinner,sun8i-h3-r-ccu";
696 reg = <0x01f01400 0x100>;
697 clocks = <&osc24M>, <&osc32k>, <&iosc>,
699 clock-names = "hosc", "losc", "iosc", "pll-periph";
704 codec_analog: codec-analog@1f015c0 {
705 compatible = "allwinner,sun8i-h3-codec-analog";
706 reg = <0x01f015c0 0x4>;
710 compatible = "allwinner,sun5i-a13-ir";
711 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
712 clock-names = "apb", "ir";
713 resets = <&r_ccu RST_APB0_IR>;
714 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
715 reg = <0x01f02000 0x40>;
719 r_pio: pinctrl@1f02c00 {
720 compatible = "allwinner,sun8i-h3-r-pinctrl";
721 reg = <0x01f02c00 0x400>;
722 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
724 clock-names = "apb", "hosc", "losc";
727 interrupt-controller;
728 #interrupt-cells = <3>;
732 function = "s_cir_rx";