arch/arm/boot/dts/sunxi-h3-h5.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/sun8i-de2.h>
  44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  45 #include <dt-bindings/clock/sun8i-r-ccu.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/reset/sun8i-de2.h>
  48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49 #include <dt-bindings/reset/sun8i-r-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         chosen {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60
  61                 framebuffer-hdmi {
  62                         compatible = "allwinner,simple-framebuffer",
  63                                      "simple-framebuffer";
  64                         allwinner,pipeline = "mixer0-lcd0-hdmi";
  65                         clocks = <&display_clocks CLK_MIXER0>,
  66                                  <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
  67                         status = "disabled";
  68                 };
  69
  70                 framebuffer-tve {
  71                         compatible = "allwinner,simple-framebuffer",
  72                                      "simple-framebuffer";
  73                         allwinner,pipeline = "mixer1-lcd1-tve";
  74                         clocks = <&display_clocks CLK_MIXER1>,
  75                                  <&ccu CLK_TVE>;
  76                         status = "disabled";
  77                 };
  78         };
  79
  80         clocks {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 osc24M: osc24M_clk {
  86                         #clock-cells = <0>;
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <24000000>;
  89                         clock-accuracy = <50000>;
  90                         clock-output-names = "osc24M";
  91                 };
  92
  93                 osc32k: osc32k_clk {
  94                         #clock-cells = <0>;
  95                         compatible = "fixed-clock";
  96                         clock-frequency = <32768>;
  97                         clock-accuracy = <50000>;
  98                         clock-output-names = "ext_osc32k";
  99                 };
 100         };
 101
 102         de: display-engine {
 103                 compatible = "allwinner,sun8i-h3-display-engine";
 104                 allwinner,pipelines = <&mixer0>;
 105                 status = "disabled";
 106         };
 107
 108         soc {
 109                 compatible = "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 dma-ranges;
 113                 ranges;
 114
 115                 display_clocks: clock@1000000 {
 116                         /* compatible is in per SoC .dtsi file */
 117                         reg = <0x01000000 0x10000>;
 118                         clocks = <&ccu CLK_BUS_DE>,
 119                                  <&ccu CLK_DE>;
 120                         clock-names = "bus",
 121                                       "mod";
 122                         resets = <&ccu RST_BUS_DE>;
 123                         #clock-cells = <1>;
 124                         #reset-cells = <1>;
 125                 };
 126
 127                 mixer0: mixer@1100000 {
 128                         compatible = "allwinner,sun8i-h3-de2-mixer-0";
 129                         reg = <0x01100000 0x100000>;
 130                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 131                                  <&display_clocks CLK_MIXER0>;
 132                         clock-names = "bus",
 133                                       "mod";
 134                         resets = <&display_clocks RST_MIXER0>;
 135
 136                         ports {
 137                                 #address-cells = <1>;
 138                                 #size-cells = <0>;
 139
 140                                 mixer0_out: port@1 {
 141                                         reg = <1>;
 142
 143                                         mixer0_out_tcon0: endpoint {
 144                                                 remote-endpoint = <&tcon0_in_mixer0>;
 145                                         };
 146                                 };
 147                         };
 148                 };
 149
 150                 dma: dma-controller@1c02000 {
 151                         compatible = "allwinner,sun8i-h3-dma";
 152                         reg = <0x01c02000 0x1000>;
 153                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 154                         clocks = <&ccu CLK_BUS_DMA>;
 155                         resets = <&ccu RST_BUS_DMA>;
 156                         #dma-cells = <1>;
 157                 };
 158
 159                 tcon0: lcd-controller@1c0c000 {
 160                         compatible = "allwinner,sun8i-h3-tcon-tv",
 161                                      "allwinner,sun8i-a83t-tcon-tv";
 162                         reg = <0x01c0c000 0x1000>;
 163                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 165                         clock-names = "ahb", "tcon-ch1";
 166                         resets = <&ccu RST_BUS_TCON0>;
 167                         reset-names = "lcd";
 168
 169                         ports {
 170                                 #address-cells = <1>;
 171                                 #size-cells = <0>;
 172
 173                                 tcon0_in: port@0 {
 174                                         reg = <0>;
 175
 176                                         tcon0_in_mixer0: endpoint {
 177                                                 remote-endpoint = <&mixer0_out_tcon0>;
 178                                         };
 179                                 };
 180
 181                                 tcon0_out: port@1 {
 182                                         #address-cells = <1>;
 183                                         #size-cells = <0>;
 184                                         reg = <1>;
 185
 186                                         tcon0_out_hdmi: endpoint@1 {
 187                                                 reg = <1>;
 188                                                 remote-endpoint = <&hdmi_in_tcon0>;
 189                                         };
 190                                 };
 191                         };
 192                 };
 193
 194                 mmc0: mmc@1c0f000 {
 195                         /* compatible and clocks are in per SoC .dtsi file */
 196                         reg = <0x01c0f000 0x1000>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&mmc0_pins>;
 199                         resets = <&ccu RST_BUS_MMC0>;
 200                         reset-names = "ahb";
 201                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 202                         status = "disabled";
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                 };
 206
 207                 mmc1: mmc@1c10000 {
 208                         /* compatible and clocks are in per SoC .dtsi file */
 209                         reg = <0x01c10000 0x1000>;
 210                         pinctrl-names = "default";
 211                         pinctrl-0 = <&mmc1_pins>;
 212                         resets = <&ccu RST_BUS_MMC1>;
 213                         reset-names = "ahb";
 214                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 215                         status = "disabled";
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                 };
 219
 220                 mmc2: mmc@1c11000 {
 221                         /* compatible and clocks are in per SoC .dtsi file */
 222                         reg = <0x01c11000 0x1000>;
 223                         resets = <&ccu RST_BUS_MMC2>;
 224                         reset-names = "ahb";
 225                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 226                         status = "disabled";
 227                         #address-cells = <1>;
 228                         #size-cells = <0>;
 229                 };
 230
 231                 sid: eeprom@1c14000 {
 232                         /* compatible is in per SoC .dtsi file */
 233                         reg = <0x1c14000 0x400>;
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236
 237                         ths_calibration: thermal-sensor-calibration@34 {
 238                                 reg = <0x34 4>;
 239                         };
 240                 };
 241
 242                 usb_otg: usb@1c19000 {
 243                         compatible = "allwinner,sun8i-h3-musb";
 244                         reg = <0x01c19000 0x400>;
 245                         clocks = <&ccu CLK_BUS_OTG>;
 246                         resets = <&ccu RST_BUS_OTG>;
 247                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 248                         interrupt-names = "mc";
 249                         phys = <&usbphy 0>;
 250                         phy-names = "usb";
 251                         extcon = <&usbphy 0>;
 252                         dr_mode = "otg";
 253                         status = "disabled";
 254                 };
 255
 256                 usbphy: phy@1c19400 {
 257                         compatible = "allwinner,sun8i-h3-usb-phy";
 258                         reg = <0x01c19400 0x2c>,
 259                               <0x01c1a800 0x4>,
 260                               <0x01c1b800 0x4>,
 261                               <0x01c1c800 0x4>,
 262                               <0x01c1d800 0x4>;
 263                         reg-names = "phy_ctrl",
 264                                     "pmu0",
 265                                     "pmu1",
 266                                     "pmu2",
 267                                     "pmu3";
 268                         clocks = <&ccu CLK_USB_PHY0>,
 269                                  <&ccu CLK_USB_PHY1>,
 270                                  <&ccu CLK_USB_PHY2>,
 271                                  <&ccu CLK_USB_PHY3>;
 272                         clock-names = "usb0_phy",
 273                                       "usb1_phy",
 274                                       "usb2_phy",
 275                                       "usb3_phy";
 276                         resets = <&ccu RST_USB_PHY0>,
 277                                  <&ccu RST_USB_PHY1>,
 278                                  <&ccu RST_USB_PHY2>,
 279                                  <&ccu RST_USB_PHY3>;
 280                         reset-names = "usb0_reset",
 281                                       "usb1_reset",
 282                                       "usb2_reset",
 283                                       "usb3_reset";
 284                         status = "disabled";
 285                         #phy-cells = <1>;
 286                 };
 287
 288                 ehci0: usb@1c1a000 {
 289                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 290                         reg = <0x01c1a000 0x100>;
 291                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
 293                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 294                         status = "disabled";
 295                 };
 296
 297                 ohci0: usb@1c1a400 {
 298                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 299                         reg = <0x01c1a400 0x100>;
 300                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
 302                                  <&ccu CLK_USB_OHCI0>;
 303                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 304                         status = "disabled";
 305                 };
 306
 307                 ehci1: usb@1c1b000 {
 308                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 309                         reg = <0x01c1b000 0x100>;
 310                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 312                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 313                         phys = <&usbphy 1>;
 314                         phy-names = "usb";
 315                         status = "disabled";
 316                 };
 317
 318                 ohci1: usb@1c1b400 {
 319                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 320                         reg = <0x01c1b400 0x100>;
 321                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 323                                  <&ccu CLK_USB_OHCI1>;
 324                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 325                         phys = <&usbphy 1>;
 326                         phy-names = "usb";
 327                         status = "disabled";
 328                 };
 329
 330                 ehci2: usb@1c1c000 {
 331                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 332                         reg = <0x01c1c000 0x100>;
 333                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 335                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 336                         phys = <&usbphy 2>;
 337                         phy-names = "usb";
 338                         status = "disabled";
 339                 };
 340
 341                 ohci2: usb@1c1c400 {
 342                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 343                         reg = <0x01c1c400 0x100>;
 344                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 345                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 346                                  <&ccu CLK_USB_OHCI2>;
 347                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 348                         phys = <&usbphy 2>;
 349                         phy-names = "usb";
 350                         status = "disabled";
 351                 };
 352
 353                 ehci3: usb@1c1d000 {
 354                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 355                         reg = <0x01c1d000 0x100>;
 356                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 358                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 359                         phys = <&usbphy 3>;
 360                         phy-names = "usb";
 361                         status = "disabled";
 362                 };
 363
 364                 ohci3: usb@1c1d400 {
 365                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 366                         reg = <0x01c1d400 0x100>;
 367                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 369                                  <&ccu CLK_USB_OHCI3>;
 370                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 371                         phys = <&usbphy 3>;
 372                         phy-names = "usb";
 373                         status = "disabled";
 374                 };
 375
 376                 ccu: clock@1c20000 {
 377                         /* compatible is in per SoC .dtsi file */
 378                         reg = <0x01c20000 0x400>;
 379                         clocks = <&osc24M>, <&rtc 0>;
 380                         clock-names = "hosc", "losc";
 381                         #clock-cells = <1>;
 382                         #reset-cells = <1>;
 383                 };
 384
 385                 pio: pinctrl@1c20800 {
 386                         /* compatible is in per SoC .dtsi file */
 387                         reg = <0x01c20800 0x400>;
 388                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 389                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 390                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 391                         clock-names = "apb", "hosc", "losc";
 392                         gpio-controller;
 393                         #gpio-cells = <3>;
 394                         interrupt-controller;
 395                         #interrupt-cells = <3>;
 396
 397                         csi_pins: csi-pins {
 398                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 399                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 400                                        "PE11";
 401                                 function = "csi";
 402                         };
 403
 404                         emac_rgmii_pins: emac-rgmii-pins {
 405                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 406                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 407                                        "PD12", "PD13", "PD15", "PD16", "PD17";
 408                                 function = "emac";
 409                                 drive-strength = <40>;
 410                         };
 411
 412                         i2c0_pins: i2c0-pins {
 413                                 pins = "PA11", "PA12";
 414                                 function = "i2c0";
 415                         };
 416
 417                         i2c1_pins: i2c1-pins {
 418                                 pins = "PA18", "PA19";
 419                                 function = "i2c1";
 420                         };
 421
 422                         i2c2_pins: i2c2-pins {
 423                                 pins = "PE12", "PE13";
 424                                 function = "i2c2";
 425                         };
 426
 427                         mmc0_pins: mmc0-pins {
 428                                 pins = "PF0", "PF1", "PF2", "PF3",
 429                                        "PF4", "PF5";
 430                                 function = "mmc0";
 431                                 drive-strength = <30>;
 432                                 bias-pull-up;
 433                         };
 434
 435                         mmc1_pins: mmc1-pins {
 436                                 pins = "PG0", "PG1", "PG2", "PG3",
 437                                        "PG4", "PG5";
 438                                 function = "mmc1";
 439                                 drive-strength = <30>;
 440                                 bias-pull-up;
 441                         };
 442
 443                         mmc2_8bit_pins: mmc2-8bit-pins {
 444                                 pins = "PC5", "PC6", "PC8",
 445                                        "PC9", "PC10", "PC11",
 446                                        "PC12", "PC13", "PC14",
 447                                        "PC15", "PC16";
 448                                 function = "mmc2";
 449                                 drive-strength = <30>;
 450                                 bias-pull-up;
 451                         };
 452
 453                         spdif_tx_pin: spdif-tx-pin {
 454                                 pins = "PA17";
 455                                 function = "spdif";
 456                         };
 457
 458                         spi0_pins: spi0-pins {
 459                                 pins = "PC0", "PC1", "PC2", "PC3";
 460                                 function = "spi0";
 461                         };
 462
 463                         spi1_pins: spi1-pins {
 464                                 pins = "PA15", "PA16", "PA14", "PA13";
 465                                 function = "spi1";
 466                         };
 467
 468                         uart0_pa_pins: uart0-pa-pins {
 469                                 pins = "PA4", "PA5";
 470                                 function = "uart0";
 471                         };
 472
 473                         uart1_pins: uart1-pins {
 474                                 pins = "PG6", "PG7";
 475                                 function = "uart1";
 476                         };
 477
 478                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 479                                 pins = "PG8", "PG9";
 480                                 function = "uart1";
 481                         };
 482
 483                         uart2_pins: uart2-pins {
 484                                 pins = "PA0", "PA1";
 485                                 function = "uart2";
 486                         };
 487
 488                         uart2_rts_cts_pins: uart2-rts-cts-pins {
 489                                 pins = "PA2", "PA3";
 490                                 function = "uart2";
 491                         };
 492
 493                         uart3_pins: uart3-pins {
 494                                 pins = "PA13", "PA14";
 495                                 function = "uart3";
 496                         };
 497
 498                         uart3_rts_cts_pins: uart3-rts-cts-pins {
 499                                 pins = "PA15", "PA16";
 500                                 function = "uart3";
 501                         };
 502                 };
 503
 504                 timer@1c20c00 {
 505                         compatible = "allwinner,sun8i-a23-timer";
 506                         reg = <0x01c20c00 0xa0>;
 507                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 508                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 509                         clocks = <&osc24M>;
 510                 };
 511
 512                 emac: ethernet@1c30000 {
 513                         compatible = "allwinner,sun8i-h3-emac";
 514                         syscon = <&syscon>;
 515                         reg = <0x01c30000 0x10000>;
 516                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 517                         interrupt-names = "macirq";
 518                         resets = <&ccu RST_BUS_EMAC>;
 519                         reset-names = "stmmaceth";
 520                         clocks = <&ccu CLK_BUS_EMAC>;
 521                         clock-names = "stmmaceth";
 522                         status = "disabled";
 523
 524                         mdio: mdio {
 525                                 #address-cells = <1>;
 526                                 #size-cells = <0>;
 527                                 compatible = "snps,dwmac-mdio";
 528                         };
 529
 530                         mdio-mux {
 531                                 compatible = "allwinner,sun8i-h3-mdio-mux";
 532                                 #address-cells = <1>;
 533                                 #size-cells = <0>;
 534
 535                                 mdio-parent-bus = <&mdio>;
 536                                 /* Only one MDIO is usable at the time */
 537                                 internal_mdio: mdio@1 {
 538                                         compatible = "allwinner,sun8i-h3-mdio-internal";
 539                                         reg = <1>;
 540                                         #address-cells = <1>;
 541                                         #size-cells = <0>;
 542
 543                                         int_mii_phy: ethernet-phy@1 {
 544                                                 compatible = "ethernet-phy-ieee802.3-c22";
 545                                                 reg = <1>;
 546                                                 clocks = <&ccu CLK_BUS_EPHY>;
 547                                                 resets = <&ccu RST_BUS_EPHY>;
 548                                         };
 549                                 };
 550
 551                                 external_mdio: mdio@2 {
 552                                         reg = <2>;
 553                                         #address-cells = <1>;
 554                                         #size-cells = <0>;
 555                                 };
 556                         };
 557                 };
 558
 559                 mbus: dram-controller@1c62000 {
 560                         compatible = "allwinner,sun8i-h3-mbus";
 561                         reg = <0x01c62000 0x1000>;
 562                         clocks = <&ccu CLK_MBUS>;
 563                         #address-cells = <1>;
 564                         #size-cells = <1>;
 565                         dma-ranges = <0x00000000 0x40000000 0xc0000000>;
 566                         #interconnect-cells = <1>;
 567                 };
 568
 569                 spi0: spi@1c68000 {
 570                         compatible = "allwinner,sun8i-h3-spi";
 571                         reg = <0x01c68000 0x1000>;
 572                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 573                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 574                         clock-names = "ahb", "mod";
 575                         dmas = <&dma 23>, <&dma 23>;
 576                         dma-names = "rx", "tx";
 577                         pinctrl-names = "default";
 578                         pinctrl-0 = <&spi0_pins>;
 579                         resets = <&ccu RST_BUS_SPI0>;
 580                         status = "disabled";
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                 };
 584
 585                 spi1: spi@1c69000 {
 586                         compatible = "allwinner,sun8i-h3-spi";
 587                         reg = <0x01c69000 0x1000>;
 588                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 589                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 590                         clock-names = "ahb", "mod";
 591                         dmas = <&dma 24>, <&dma 24>;
 592                         dma-names = "rx", "tx";
 593                         pinctrl-names = "default";
 594                         pinctrl-0 = <&spi1_pins>;
 595                         resets = <&ccu RST_BUS_SPI1>;
 596                         status = "disabled";
 597                         #address-cells = <1>;
 598                         #size-cells = <0>;
 599                 };
 600
 601                 wdt0: watchdog@1c20ca0 {
 602                         compatible = "allwinner,sun6i-a31-wdt";
 603                         reg = <0x01c20ca0 0x20>;
 604                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 605                         clocks = <&osc24M>;
 606                 };
 607
 608                 spdif: spdif@1c21000 {
 609                         #sound-dai-cells = <0>;
 610                         compatible = "allwinner,sun8i-h3-spdif";
 611                         reg = <0x01c21000 0x400>;
 612                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 614                         resets = <&ccu RST_BUS_SPDIF>;
 615                         clock-names = "apb", "spdif";
 616                         dmas = <&dma 2>;
 617                         dma-names = "tx";
 618                         status = "disabled";
 619                 };
 620
 621                 pwm: pwm@1c21400 {
 622                         compatible = "allwinner,sun8i-h3-pwm";
 623                         reg = <0x01c21400 0x8>;
 624                         clocks = <&osc24M>;
 625                         #pwm-cells = <3>;
 626                         status = "disabled";
 627                 };
 628
 629                 i2s0: i2s@1c22000 {
 630                         #sound-dai-cells = <0>;
 631                         compatible = "allwinner,sun8i-h3-i2s";
 632                         reg = <0x01c22000 0x400>;
 633                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 634                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 635                         clock-names = "apb", "mod";
 636                         dmas = <&dma 3>, <&dma 3>;
 637                         resets = <&ccu RST_BUS_I2S0>;
 638                         dma-names = "rx", "tx";
 639                         status = "disabled";
 640                 };
 641
 642                 i2s1: i2s@1c22400 {
 643                         #sound-dai-cells = <0>;
 644                         compatible = "allwinner,sun8i-h3-i2s";
 645                         reg = <0x01c22400 0x400>;
 646                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 647                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 648                         clock-names = "apb", "mod";
 649                         dmas = <&dma 4>, <&dma 4>;
 650                         resets = <&ccu RST_BUS_I2S1>;
 651                         dma-names = "rx", "tx";
 652                         status = "disabled";
 653                 };
 654
 655                 codec: codec@1c22c00 {
 656                         #sound-dai-cells = <0>;
 657                         compatible = "allwinner,sun8i-h3-codec";
 658                         reg = <0x01c22c00 0x400>;
 659                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 661                         clock-names = "apb", "codec";
 662                         resets = <&ccu RST_BUS_CODEC>;
 663                         dmas = <&dma 15>, <&dma 15>;
 664                         dma-names = "rx", "tx";
 665                         allwinner,codec-analog-controls = <&codec_analog>;
 666                         status = "disabled";
 667                 };
 668
 669                 uart0: serial@1c28000 {
 670                         compatible = "snps,dw-apb-uart";
 671                         reg = <0x01c28000 0x400>;
 672                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 673                         reg-shift = <2>;
 674                         reg-io-width = <4>;
 675                         clocks = <&ccu CLK_BUS_UART0>;
 676                         resets = <&ccu RST_BUS_UART0>;
 677                         dmas = <&dma 6>, <&dma 6>;
 678                         dma-names = "rx", "tx";
 679                         status = "disabled";
 680                 };
 681
 682                 uart1: serial@1c28400 {
 683                         compatible = "snps,dw-apb-uart";
 684                         reg = <0x01c28400 0x400>;
 685                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 686                         reg-shift = <2>;
 687                         reg-io-width = <4>;
 688                         clocks = <&ccu CLK_BUS_UART1>;
 689                         resets = <&ccu RST_BUS_UART1>;
 690                         dmas = <&dma 7>, <&dma 7>;
 691                         dma-names = "rx", "tx";
 692                         status = "disabled";
 693                 };
 694
 695                 uart2: serial@1c28800 {
 696                         compatible = "snps,dw-apb-uart";
 697                         reg = <0x01c28800 0x400>;
 698                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 699                         reg-shift = <2>;
 700                         reg-io-width = <4>;
 701                         clocks = <&ccu CLK_BUS_UART2>;
 702                         resets = <&ccu RST_BUS_UART2>;
 703                         dmas = <&dma 8>, <&dma 8>;
 704                         dma-names = "rx", "tx";
 705                         status = "disabled";
 706                 };
 707
 708                 uart3: serial@1c28c00 {
 709                         compatible = "snps,dw-apb-uart";
 710                         reg = <0x01c28c00 0x400>;
 711                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 712                         reg-shift = <2>;
 713                         reg-io-width = <4>;
 714                         clocks = <&ccu CLK_BUS_UART3>;
 715                         resets = <&ccu RST_BUS_UART3>;
 716                         dmas = <&dma 9>, <&dma 9>;
 717                         dma-names = "rx", "tx";
 718                         status = "disabled";
 719                 };
 720
 721                 i2c0: i2c@1c2ac00 {
 722                         compatible = "allwinner,sun6i-a31-i2c";
 723                         reg = <0x01c2ac00 0x400>;
 724                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&ccu CLK_BUS_I2C0>;
 726                         resets = <&ccu RST_BUS_I2C0>;
 727                         pinctrl-names = "default";
 728                         pinctrl-0 = <&i2c0_pins>;
 729                         status = "disabled";
 730                         #address-cells = <1>;
 731                         #size-cells = <0>;
 732                 };
 733
 734                 i2c1: i2c@1c2b000 {
 735                         compatible = "allwinner,sun6i-a31-i2c";
 736                         reg = <0x01c2b000 0x400>;
 737                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 738                         clocks = <&ccu CLK_BUS_I2C1>;
 739                         resets = <&ccu RST_BUS_I2C1>;
 740                         pinctrl-names = "default";
 741                         pinctrl-0 = <&i2c1_pins>;
 742                         status = "disabled";
 743                         #address-cells = <1>;
 744                         #size-cells = <0>;
 745                 };
 746
 747                 i2c2: i2c@1c2b400 {
 748                         compatible = "allwinner,sun6i-a31-i2c";
 749                         reg = <0x01c2b400 0x400>;
 750                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 751                         clocks = <&ccu CLK_BUS_I2C2>;
 752                         resets = <&ccu RST_BUS_I2C2>;
 753                         pinctrl-names = "default";
 754                         pinctrl-0 = <&i2c2_pins>;
 755                         status = "disabled";
 756                         #address-cells = <1>;
 757                         #size-cells = <0>;
 758                 };
 759
 760                 gic: interrupt-controller@1c81000 {
 761                         compatible = "arm,gic-400";
 762                         reg = <0x01c81000 0x1000>,
 763                               <0x01c82000 0x2000>,
 764                               <0x01c84000 0x2000>,
 765                               <0x01c86000 0x2000>;
 766                         interrupt-controller;
 767                         #interrupt-cells = <3>;
 768                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 769                 };
 770
 771                 csi: camera@1cb0000 {
 772                         compatible = "allwinner,sun8i-h3-csi";
 773                         reg = <0x01cb0000 0x1000>;
 774                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 775                         clocks = <&ccu CLK_BUS_CSI>,
 776                                  <&ccu CLK_CSI_SCLK>,
 777                                  <&ccu CLK_DRAM_CSI>;
 778                         clock-names = "bus", "mod", "ram";
 779                         resets = <&ccu RST_BUS_CSI>;
 780                         pinctrl-names = "default";
 781                         pinctrl-0 = <&csi_pins>;
 782                         status = "disabled";
 783                 };
 784
 785                 hdmi: hdmi@1ee0000 {
 786                         compatible = "allwinner,sun8i-h3-dw-hdmi",
 787                                      "allwinner,sun8i-a83t-dw-hdmi";
 788                         reg = <0x01ee0000 0x10000>;
 789                         reg-io-width = <1>;
 790                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 791                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 792                                  <&ccu CLK_HDMI>;
 793                         clock-names = "iahb", "isfr", "tmds";
 794                         resets = <&ccu RST_BUS_HDMI1>;
 795                         reset-names = "ctrl";
 796                         phys = <&hdmi_phy>;
 797                         phy-names = "phy";
 798                         status = "disabled";
 799
 800                         ports {
 801                                 #address-cells = <1>;
 802                                 #size-cells = <0>;
 803
 804                                 hdmi_in: port@0 {
 805                                         reg = <0>;
 806
 807                                         hdmi_in_tcon0: endpoint {
 808                                                 remote-endpoint = <&tcon0_out_hdmi>;
 809                                         };
 810                                 };
 811
 812                                 hdmi_out: port@1 {
 813                                         reg = <1>;
 814                                 };
 815                         };
 816                 };
 817
 818                 hdmi_phy: hdmi-phy@1ef0000 {
 819                         compatible = "allwinner,sun8i-h3-hdmi-phy";
 820                         reg = <0x01ef0000 0x10000>;
 821                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 822                                  <&ccu CLK_PLL_VIDEO>;
 823                         clock-names = "bus", "mod", "pll-0";
 824                         resets = <&ccu RST_BUS_HDMI0>;
 825                         reset-names = "phy";
 826                         #phy-cells = <0>;
 827                 };
 828
 829                 rtc: rtc@1f00000 {
 830                         /* compatible is in per SoC .dtsi file */
 831                         reg = <0x01f00000 0x400>;
 832                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 833                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 834                         clock-output-names = "osc32k", "osc32k-out", "iosc";
 835                         clocks = <&osc32k>;
 836                         #clock-cells = <1>;
 837                 };
 838
 839                 r_ccu: clock@1f01400 {
 840                         compatible = "allwinner,sun8i-h3-r-ccu";
 841                         reg = <0x01f01400 0x100>;
 842                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
 843                                  <&ccu CLK_PLL_PERIPH0>;
 844                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 845                         #clock-cells = <1>;
 846                         #reset-cells = <1>;
 847                 };
 848
 849                 codec_analog: codec-analog@1f015c0 {
 850                         compatible = "allwinner,sun8i-h3-codec-analog";
 851                         reg = <0x01f015c0 0x4>;
 852                 };
 853
 854                 ir: ir@1f02000 {
 855                         compatible = "allwinner,sun6i-a31-ir";
 856                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
 857                         clock-names = "apb", "ir";
 858                         resets = <&r_ccu RST_APB0_IR>;
 859                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 860                         reg = <0x01f02000 0x400>;
 861                         status = "disabled";
 862                 };
 863
 864                 r_i2c: i2c@1f02400 {
 865                         compatible = "allwinner,sun6i-a31-i2c";
 866                         reg = <0x01f02400 0x400>;
 867                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 868                         pinctrl-names = "default";
 869                         pinctrl-0 = <&r_i2c_pins>;
 870                         clocks = <&r_ccu CLK_APB0_I2C>;
 871                         resets = <&r_ccu RST_APB0_I2C>;
 872                         status = "disabled";
 873                         #address-cells = <1>;
 874                         #size-cells = <0>;
 875                 };
 876
 877                 r_pio: pinctrl@1f02c00 {
 878                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 879                         reg = <0x01f02c00 0x400>;
 880                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 881                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
 882                         clock-names = "apb", "hosc", "losc";
 883                         gpio-controller;
 884                         #gpio-cells = <3>;
 885                         interrupt-controller;
 886                         #interrupt-cells = <3>;
 887
 888                         r_ir_rx_pin: r-ir-rx-pin {
 889                                 pins = "PL11";
 890                                 function = "s_cir_rx";
 891                         };
 892
 893                         r_i2c_pins: r-i2c-pins {
 894                                 pins = "PL0", "PL1";
 895                                 function = "s_i2c";
 896                         };
 897
 898                         r_pwm_pin: r-pwm-pin {
 899                                 pins = "PL10";
 900                                 function = "s_pwm";
 901                         };
 902                 };
 903
 904                 r_pwm: pwm@1f03800 {
 905                         compatible = "allwinner,sun8i-h3-pwm";
 906                         reg = <0x01f03800 0x8>;
 907                         pinctrl-names = "default";
 908                         pinctrl-0 = <&r_pwm_pin>;
 909                         clocks = <&osc24M>;
 910                         #pwm-cells = <3>;
 911                         status = "disabled";
 912                 };
 913         };
 914 };