arch/arm/boot/dts/sun8i-r40.dtsi

   1 /*
   2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
   3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/clock/sun8i-de2.h>
  46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
  47 #include <dt-bindings/clock/sun8i-tcon-top.h>
  48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
  49 #include <dt-bindings/reset/sun8i-de2.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55         interrupt-parent = <&gic>;
  56
  57         clocks {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 ranges;
  61
  62                 osc24M: osc24M {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <24000000>;
  66                         clock-accuracy = <50000>;
  67                         clock-output-names = "osc24M";
  68                 };
  69
  70                 osc32k: osc32k {
  71                         #clock-cells = <0>;
  72                         compatible = "fixed-clock";
  73                         clock-frequency = <32768>;
  74                         clock-accuracy = <20000>;
  75                         clock-output-names = "ext-osc32k";
  76                 };
  77         };
  78
  79         cpus {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 cpu0: cpu@0 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <0>;
  87                 };
  88
  89                 cpu1: cpu@1 {
  90                         compatible = "arm,cortex-a7";
  91                         device_type = "cpu";
  92                         reg = <1>;
  93                 };
  94
  95                 cpu2: cpu@2 {
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         reg = <2>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         compatible = "arm,cortex-a7";
 103                         device_type = "cpu";
 104                         reg = <3>;
 105                 };
 106         };
 107
 108         de: display-engine {
 109                 compatible = "allwinner,sun8i-r40-display-engine";
 110                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 111                 status = "disabled";
 112         };
 113
 114         thermal-zones {
 115                 cpu_thermal: cpu0-thermal {
 116                         /* milliseconds */
 117                         polling-delay-passive = <0>;
 118                         polling-delay = <0>;
 119                         thermal-sensors = <&ths 0>;
 120                 };
 121
 122                 gpu_thermal: gpu-thermal {
 123                         /* milliseconds */
 124                         polling-delay-passive = <0>;
 125                         polling-delay = <0>;
 126                         thermal-sensors = <&ths 1>;
 127                 };
 128         };
 129
 130         soc {
 131                 compatible = "simple-bus";
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 ranges;
 135
 136                 display_clocks: clock@1000000 {
 137                         compatible = "allwinner,sun8i-r40-de2-clk",
 138                                      "allwinner,sun8i-h3-de2-clk";
 139                         reg = <0x01000000 0x10000>;
 140                         clocks = <&ccu CLK_BUS_DE>,
 141                                  <&ccu CLK_DE>;
 142                         clock-names = "bus",
 143                                       "mod";
 144                         resets = <&ccu RST_BUS_DE>;
 145                         #clock-cells = <1>;
 146                         #reset-cells = <1>;
 147                 };
 148
 149                 mixer0: mixer@1100000 {
 150                         compatible = "allwinner,sun8i-r40-de2-mixer-0";
 151                         reg = <0x01100000 0x100000>;
 152                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 153                                  <&display_clocks CLK_MIXER0>;
 154                         clock-names = "bus",
 155                                       "mod";
 156                         resets = <&display_clocks RST_MIXER0>;
 157
 158                         ports {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161
 162                                 mixer0_out: port@1 {
 163                                         reg = <1>;
 164                                         mixer0_out_tcon_top: endpoint {
 165                                                 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 166                                         };
 167                                 };
 168                         };
 169                 };
 170
 171                 mixer1: mixer@1200000 {
 172                         compatible = "allwinner,sun8i-r40-de2-mixer-1";
 173                         reg = <0x01200000 0x100000>;
 174                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 175                                  <&display_clocks CLK_MIXER1>;
 176                         clock-names = "bus",
 177                                       "mod";
 178                         resets = <&display_clocks RST_WB>;
 179
 180                         ports {
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183
 184                                 mixer1_out: port@1 {
 185                                         reg = <1>;
 186                                         mixer1_out_tcon_top: endpoint {
 187                                                 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
 188                                         };
 189                                 };
 190                         };
 191                 };
 192
 193                 nmi_intc: interrupt-controller@1c00030 {
 194                         compatible = "allwinner,sun7i-a20-sc-nmi";
 195                         interrupt-controller;
 196                         #interrupt-cells = <2>;
 197                         reg = <0x01c00030 0x0c>;
 198                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 199                 };
 200
 201                 spi0: spi@1c05000 {
 202                         compatible = "allwinner,sun8i-r40-spi",
 203                                      "allwinner,sun8i-h3-spi";
 204                         reg = <0x01c05000 0x1000>;
 205                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 206                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 207                         clock-names = "ahb", "mod";
 208                         resets = <&ccu RST_BUS_SPI0>;
 209                         status = "disabled";
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                 };
 213
 214                 spi1: spi@1c06000 {
 215                         compatible = "allwinner,sun8i-r40-spi",
 216                                      "allwinner,sun8i-h3-spi";
 217                         reg = <0x01c06000 0x1000>;
 218                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 220                         clock-names = "ahb", "mod";
 221                         resets = <&ccu RST_BUS_SPI1>;
 222                         status = "disabled";
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                 };
 226
 227                 csi0: csi@1c09000 {
 228                         compatible = "allwinner,sun8i-r40-csi0",
 229                                      "allwinner,sun7i-a20-csi0";
 230                         reg = <0x01c09000 0x1000>;
 231                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
 233                                  <&ccu CLK_DRAM_CSI0>;
 234                         clock-names = "bus", "isp", "ram";
 235                         resets = <&ccu RST_BUS_CSI0>;
 236                         interconnects = <&mbus 5>;
 237                         interconnect-names = "dma-mem";
 238                         status = "disabled";
 239                 };
 240
 241                 mmc0: mmc@1c0f000 {
 242                         compatible = "allwinner,sun8i-r40-mmc",
 243                                      "allwinner,sun50i-a64-mmc";
 244                         reg = <0x01c0f000 0x1000>;
 245                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 246                         clock-names = "ahb", "mmc";
 247                         resets = <&ccu RST_BUS_MMC0>;
 248                         reset-names = "ahb";
 249                         pinctrl-0 = <&mmc0_pins>;
 250                         pinctrl-names = "default";
 251                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 252                         status = "disabled";
 253                         #address-cells = <1>;
 254                         #size-cells = <0>;
 255                 };
 256
 257                 mmc1: mmc@1c10000 {
 258                         compatible = "allwinner,sun8i-r40-mmc",
 259                                      "allwinner,sun50i-a64-mmc";
 260                         reg = <0x01c10000 0x1000>;
 261                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 262                         clock-names = "ahb", "mmc";
 263                         resets = <&ccu RST_BUS_MMC1>;
 264                         reset-names = "ahb";
 265                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 266                         status = "disabled";
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                 };
 270
 271                 mmc2: mmc@1c11000 {
 272                         compatible = "allwinner,sun8i-r40-emmc",
 273                                      "allwinner,sun50i-a64-emmc";
 274                         reg = <0x01c11000 0x1000>;
 275                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 276                         clock-names = "ahb", "mmc";
 277                         resets = <&ccu RST_BUS_MMC2>;
 278                         reset-names = "ahb";
 279                         pinctrl-0 = <&mmc2_pins>;
 280                         pinctrl-names = "default";
 281                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 282                         status = "disabled";
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                 };
 286
 287                 mmc3: mmc@1c12000 {
 288                         compatible = "allwinner,sun8i-r40-mmc",
 289                                      "allwinner,sun50i-a64-mmc";
 290                         reg = <0x01c12000 0x1000>;
 291                         clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
 292                         clock-names = "ahb", "mmc";
 293                         resets = <&ccu RST_BUS_MMC3>;
 294                         reset-names = "ahb";
 295                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 296                         status = "disabled";
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                 };
 300
 301                 usbphy: phy@1c13400 {
 302                         compatible = "allwinner,sun8i-r40-usb-phy";
 303                         reg = <0x01c13400 0x14>,
 304                               <0x01c14800 0x4>,
 305                               <0x01c19800 0x4>,
 306                               <0x01c1c800 0x4>;
 307                         reg-names = "phy_ctrl",
 308                                     "pmu0",
 309                                     "pmu1",
 310                                     "pmu2";
 311                         clocks = <&ccu CLK_USB_PHY0>,
 312                                  <&ccu CLK_USB_PHY1>,
 313                                  <&ccu CLK_USB_PHY2>;
 314                         clock-names = "usb0_phy",
 315                                       "usb1_phy",
 316                                       "usb2_phy";
 317                         resets = <&ccu RST_USB_PHY0>,
 318                                  <&ccu RST_USB_PHY1>,
 319                                  <&ccu RST_USB_PHY2>;
 320                         reset-names = "usb0_reset",
 321                                       "usb1_reset",
 322                                       "usb2_reset";
 323                         status = "disabled";
 324                         #phy-cells = <1>;
 325                 };
 326
 327                 crypto: crypto@1c15000 {
 328                         compatible = "allwinner,sun8i-r40-crypto";
 329                         reg = <0x01c15000 0x1000>;
 330                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 332                         clock-names = "bus", "mod";
 333                         resets = <&ccu RST_BUS_CE>;
 334                 };
 335
 336                 spi2: spi@1c17000 {
 337                         compatible = "allwinner,sun8i-r40-spi",
 338                                      "allwinner,sun8i-h3-spi";
 339                         reg = <0x01c17000 0x1000>;
 340                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 341                         clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
 342                         clock-names = "ahb", "mod";
 343                         resets = <&ccu RST_BUS_SPI2>;
 344                         status = "disabled";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                 };
 348
 349                 ahci: sata@1c18000 {
 350                         compatible = "allwinner,sun8i-r40-ahci";
 351                         reg = <0x01c18000 0x1000>;
 352                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 353                         clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
 354                         resets = <&ccu RST_BUS_SATA>;
 355                         reset-names = "ahci";
 356                         status = "disabled";
 357                 };
 358
 359                 ehci1: usb@1c19000 {
 360                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 361                         reg = <0x01c19000 0x100>;
 362                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 363                         clocks = <&ccu CLK_BUS_EHCI1>;
 364                         resets = <&ccu RST_BUS_EHCI1>;
 365                         phys = <&usbphy 1>;
 366                         phy-names = "usb";
 367                         status = "disabled";
 368                 };
 369
 370                 ohci1: usb@1c19400 {
 371                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 372                         reg = <0x01c19400 0x100>;
 373                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&ccu CLK_BUS_OHCI1>,
 375                                  <&ccu CLK_USB_OHCI1>;
 376                         resets = <&ccu RST_BUS_OHCI1>;
 377                         phys = <&usbphy 1>;
 378                         phy-names = "usb";
 379                         status = "disabled";
 380                 };
 381
 382                 ehci2: usb@1c1c000 {
 383                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 384                         reg = <0x01c1c000 0x100>;
 385                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&ccu CLK_BUS_EHCI2>;
 387                         resets = <&ccu RST_BUS_EHCI2>;
 388                         phys = <&usbphy 2>;
 389                         phy-names = "usb";
 390                         status = "disabled";
 391                 };
 392
 393                 ohci2: usb@1c1c400 {
 394                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
 395                         reg = <0x01c1c400 0x100>;
 396                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 397                         clocks = <&ccu CLK_BUS_OHCI2>,
 398                                  <&ccu CLK_USB_OHCI2>;
 399                         resets = <&ccu RST_BUS_OHCI2>;
 400                         phys = <&usbphy 2>;
 401                         phy-names = "usb";
 402                         status = "disabled";
 403                 };
 404
 405                 spi3: spi@1c1f000 {
 406                         compatible = "allwinner,sun8i-r40-spi",
 407                                      "allwinner,sun8i-h3-spi";
 408                         reg = <0x01c1f000 0x1000>;
 409                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
 411                         clock-names = "ahb", "mod";
 412                         resets = <&ccu RST_BUS_SPI3>;
 413                         status = "disabled";
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                 };
 417
 418                 ccu: clock@1c20000 {
 419                         compatible = "allwinner,sun8i-r40-ccu";
 420                         reg = <0x01c20000 0x400>;
 421                         clocks = <&osc24M>, <&rtc 0>;
 422                         clock-names = "hosc", "losc";
 423                         #clock-cells = <1>;
 424                         #reset-cells = <1>;
 425                 };
 426
 427                 rtc: rtc@1c20400 {
 428                         compatible = "allwinner,sun8i-r40-rtc";
 429                         reg = <0x01c20400 0x400>;
 430                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 431                         clock-output-names = "osc32k", "osc32k-out";
 432                         clocks = <&osc32k>;
 433                         #clock-cells = <1>;
 434                 };
 435
 436                 pio: pinctrl@1c20800 {
 437                         compatible = "allwinner,sun8i-r40-pinctrl";
 438                         reg = <0x01c20800 0x400>;
 439                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
 441                         clock-names = "apb", "hosc", "losc";
 442                         gpio-controller;
 443                         interrupt-controller;
 444                         #interrupt-cells = <3>;
 445                         #gpio-cells = <3>;
 446
 447                         clk_out_a_pin: clk-out-a-pin {
 448                                 pins = "PI12";
 449                                 function = "clk_out_a";
 450                         };
 451
 452                         /omit-if-no-ref/
 453                         csi0_8bits_pins: csi0-8bits-pins {
 454                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 455                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 456                                        "PE11";
 457                                 function = "csi0";
 458                         };
 459
 460                         /omit-if-no-ref/
 461                         csi0_mclk_pin: csi0-mclk-pin {
 462                                 pins = "PE1";
 463                                 function = "csi0";
 464                         };
 465
 466                         gmac_rgmii_pins: gmac-rgmii-pins {
 467                                 pins = "PA0", "PA1", "PA2", "PA3",
 468                                        "PA4", "PA5", "PA6", "PA7",
 469                                        "PA8", "PA10", "PA11", "PA12",
 470                                        "PA13", "PA15", "PA16";
 471                                 function = "gmac";
 472                                 /*
 473                                  * data lines in RGMII mode use DDR mode
 474                                  * and need a higher signal drive strength
 475                                  */
 476                                 drive-strength = <40>;
 477                         };
 478
 479                         i2c0_pins: i2c0-pins {
 480                                 pins = "PB0", "PB1";
 481                                 function = "i2c0";
 482                         };
 483
 484                         i2c1_pins: i2c1-pins {
 485                                 pins = "PB18", "PB19";
 486                                 function = "i2c1";
 487                         };
 488
 489                         i2c2_pins: i2c2-pins {
 490                                 pins = "PB20", "PB21";
 491                                 function = "i2c2";
 492                         };
 493
 494                         i2c3_pins: i2c3-pins {
 495                                 pins = "PI0", "PI1";
 496                                 function = "i2c3";
 497                         };
 498
 499                         i2c4_pins: i2c4-pins {
 500                                 pins = "PI2", "PI3";
 501                                 function = "i2c4";
 502                         };
 503
 504                         mmc0_pins: mmc0-pins {
 505                                 pins = "PF0", "PF1", "PF2",
 506                                        "PF3", "PF4", "PF5";
 507                                 function = "mmc0";
 508                                 drive-strength = <30>;
 509                                 bias-pull-up;
 510                         };
 511
 512                         mmc1_pg_pins: mmc1-pg-pins {
 513                                 pins = "PG0", "PG1", "PG2",
 514                                        "PG3", "PG4", "PG5";
 515                                 function = "mmc1";
 516                                 drive-strength = <30>;
 517                                 bias-pull-up;
 518                         };
 519
 520                         mmc2_pins: mmc2-pins {
 521                                 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
 522                                        "PC10", "PC11", "PC12", "PC13", "PC14",
 523                                        "PC15", "PC24";
 524                                 function = "mmc2";
 525                                 drive-strength = <30>;
 526                                 bias-pull-up;
 527                         };
 528
 529                         /omit-if-no-ref/
 530                         spi0_pc_pins: spi0-pc-pins {
 531                                 pins = "PC0", "PC1", "PC2";
 532                                 function = "spi0";
 533                         };
 534
 535                         /omit-if-no-ref/
 536                         spi0_cs0_pc_pin: spi0-cs0-pc-pin {
 537                                 pins = "PC23";
 538                                 function = "spi0";
 539                         };
 540
 541                         /omit-if-no-ref/
 542                         spi1_pi_pins: spi1-pi-pins {
 543                                 pins = "PI17", "PI18", "PI19";
 544                                 function = "spi1";
 545                         };
 546
 547                         /omit-if-no-ref/
 548                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 549                                 pins = "PI16";
 550                                 function = "spi1";
 551                         };
 552
 553                         /omit-if-no-ref/
 554                         spi1_cs1_pi_pin: spi1-cs1-pi-pin {
 555                                 pins = "PI15";
 556                                 function = "spi1";
 557                         };
 558
 559                         uart0_pb_pins: uart0-pb-pins {
 560                                 pins = "PB22", "PB23";
 561                                 function = "uart0";
 562                         };
 563
 564                         uart3_pg_pins: uart3-pg-pins {
 565                                 pins = "PG6", "PG7";
 566                                 function = "uart3";
 567                         };
 568
 569                         uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
 570                                 pins = "PG8", "PG9";
 571                                 function = "uart3";
 572                         };
 573                 };
 574
 575                 wdt: watchdog@1c20c90 {
 576                         compatible = "allwinner,sun4i-a10-wdt";
 577                         reg = <0x01c20c90 0x10>;
 578                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 579                         clocks = <&osc24M>;
 580                 };
 581
 582                 ths: thermal-sensor@1c24c00 {
 583                         compatible = "allwinner,sun8i-r40-ths";
 584                         reg = <0x01c24c00 0x100>;
 585                         clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
 586                         clock-names = "bus", "mod";
 587                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 588                         resets = <&ccu RST_BUS_THS>;
 589                         /* TODO: add nvmem-cells for calibration */
 590                         #thermal-sensor-cells = <1>;
 591                 };
 592
 593                 uart0: serial@1c28000 {
 594                         compatible = "snps,dw-apb-uart";
 595                         reg = <0x01c28000 0x400>;
 596                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 597                         reg-shift = <2>;
 598                         reg-io-width = <4>;
 599                         clocks = <&ccu CLK_BUS_UART0>;
 600                         resets = <&ccu RST_BUS_UART0>;
 601                         status = "disabled";
 602                 };
 603
 604                 uart1: serial@1c28400 {
 605                         compatible = "snps,dw-apb-uart";
 606                         reg = <0x01c28400 0x400>;
 607                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 608                         reg-shift = <2>;
 609                         reg-io-width = <4>;
 610                         clocks = <&ccu CLK_BUS_UART1>;
 611                         resets = <&ccu RST_BUS_UART1>;
 612                         status = "disabled";
 613                 };
 614
 615                 uart2: serial@1c28800 {
 616                         compatible = "snps,dw-apb-uart";
 617                         reg = <0x01c28800 0x400>;
 618                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 619                         reg-shift = <2>;
 620                         reg-io-width = <4>;
 621                         clocks = <&ccu CLK_BUS_UART2>;
 622                         resets = <&ccu RST_BUS_UART2>;
 623                         status = "disabled";
 624                 };
 625
 626                 uart3: serial@1c28c00 {
 627                         compatible = "snps,dw-apb-uart";
 628                         reg = <0x01c28c00 0x400>;
 629                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 630                         reg-shift = <2>;
 631                         reg-io-width = <4>;
 632                         clocks = <&ccu CLK_BUS_UART3>;
 633                         resets = <&ccu RST_BUS_UART3>;
 634                         status = "disabled";
 635                 };
 636
 637                 uart4: serial@1c29000 {
 638                         compatible = "snps,dw-apb-uart";
 639                         reg = <0x01c29000 0x400>;
 640                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 641                         reg-shift = <2>;
 642                         reg-io-width = <4>;
 643                         clocks = <&ccu CLK_BUS_UART4>;
 644                         resets = <&ccu RST_BUS_UART4>;
 645                         status = "disabled";
 646                 };
 647
 648                 uart5: serial@1c29400 {
 649                         compatible = "snps,dw-apb-uart";
 650                         reg = <0x01c29400 0x400>;
 651                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 652                         reg-shift = <2>;
 653                         reg-io-width = <4>;
 654                         clocks = <&ccu CLK_BUS_UART5>;
 655                         resets = <&ccu RST_BUS_UART5>;
 656                         status = "disabled";
 657                 };
 658
 659                 uart6: serial@1c29800 {
 660                         compatible = "snps,dw-apb-uart";
 661                         reg = <0x01c29800 0x400>;
 662                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 663                         reg-shift = <2>;
 664                         reg-io-width = <4>;
 665                         clocks = <&ccu CLK_BUS_UART6>;
 666                         resets = <&ccu RST_BUS_UART6>;
 667                         status = "disabled";
 668                 };
 669
 670                 uart7: serial@1c29c00 {
 671                         compatible = "snps,dw-apb-uart";
 672                         reg = <0x01c29c00 0x400>;
 673                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 674                         reg-shift = <2>;
 675                         reg-io-width = <4>;
 676                         clocks = <&ccu CLK_BUS_UART7>;
 677                         resets = <&ccu RST_BUS_UART7>;
 678                         status = "disabled";
 679                 };
 680
 681                 i2c0: i2c@1c2ac00 {
 682                         compatible = "allwinner,sun6i-a31-i2c";
 683                         reg = <0x01c2ac00 0x400>;
 684                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 685                         clocks = <&ccu CLK_BUS_I2C0>;
 686                         resets = <&ccu RST_BUS_I2C0>;
 687                         pinctrl-0 = <&i2c0_pins>;
 688                         pinctrl-names = "default";
 689                         status = "disabled";
 690                         #address-cells = <1>;
 691                         #size-cells = <0>;
 692                 };
 693
 694                 i2c1: i2c@1c2b000 {
 695                         compatible = "allwinner,sun6i-a31-i2c";
 696                         reg = <0x01c2b000 0x400>;
 697                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 698                         clocks = <&ccu CLK_BUS_I2C1>;
 699                         resets = <&ccu RST_BUS_I2C1>;
 700                         pinctrl-0 = <&i2c1_pins>;
 701                         pinctrl-names = "default";
 702                         status = "disabled";
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                 };
 706
 707                 i2c2: i2c@1c2b400 {
 708                         compatible = "allwinner,sun6i-a31-i2c";
 709                         reg = <0x01c2b400 0x400>;
 710                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&ccu CLK_BUS_I2C2>;
 712                         resets = <&ccu RST_BUS_I2C2>;
 713                         pinctrl-0 = <&i2c2_pins>;
 714                         pinctrl-names = "default";
 715                         status = "disabled";
 716                         #address-cells = <1>;
 717                         #size-cells = <0>;
 718                 };
 719
 720                 i2c3: i2c@1c2b800 {
 721                         compatible = "allwinner,sun6i-a31-i2c";
 722                         reg = <0x01c2b800 0x400>;
 723                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&ccu CLK_BUS_I2C3>;
 725                         resets = <&ccu RST_BUS_I2C3>;
 726                         pinctrl-0 = <&i2c3_pins>;
 727                         pinctrl-names = "default";
 728                         status = "disabled";
 729                         #address-cells = <1>;
 730                         #size-cells = <0>;
 731                 };
 732
 733                 i2c4: i2c@1c2c000 {
 734                         compatible = "allwinner,sun6i-a31-i2c";
 735                         reg = <0x01c2c000 0x400>;
 736                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 737                         clocks = <&ccu CLK_BUS_I2C4>;
 738                         resets = <&ccu RST_BUS_I2C4>;
 739                         pinctrl-0 = <&i2c4_pins>;
 740                         pinctrl-names = "default";
 741                         status = "disabled";
 742                         #address-cells = <1>;
 743                         #size-cells = <0>;
 744                 };
 745
 746                 gmac: ethernet@1c50000 {
 747                         compatible = "allwinner,sun8i-r40-gmac";
 748                         syscon = <&ccu>;
 749                         reg = <0x01c50000 0x10000>;
 750                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 751                         interrupt-names = "macirq";
 752                         resets = <&ccu RST_BUS_GMAC>;
 753                         reset-names = "stmmaceth";
 754                         clocks = <&ccu CLK_BUS_GMAC>;
 755                         clock-names = "stmmaceth";
 756                         status = "disabled";
 757
 758                         gmac_mdio: mdio {
 759                                 compatible = "snps,dwmac-mdio";
 760                                 #address-cells = <1>;
 761                                 #size-cells = <0>;
 762                         };
 763                 };
 764
 765                 mbus: dram-controller@1c62000 {
 766                         compatible = "allwinner,sun8i-r40-mbus";
 767                         reg = <0x01c62000 0x1000>;
 768                         clocks = <&ccu 155>;
 769                         #address-cells = <1>;
 770                         #size-cells = <1>;
 771                         dma-ranges = <0x00000000 0x40000000 0x80000000>;
 772                         #interconnect-cells = <1>;
 773                 };
 774
 775                 tcon_top: tcon-top@1c70000 {
 776                         compatible = "allwinner,sun8i-r40-tcon-top";
 777                         reg = <0x01c70000 0x1000>;
 778                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 779                                  <&ccu CLK_TCON_TV0>,
 780                                  <&ccu CLK_TVE0>,
 781                                  <&ccu CLK_TCON_TV1>,
 782                                  <&ccu CLK_TVE1>,
 783                                  <&ccu CLK_DSI_DPHY>;
 784                         clock-names = "bus",
 785                                       "tcon-tv0",
 786                                       "tve0",
 787                                       "tcon-tv1",
 788                                       "tve1",
 789                                       "dsi";
 790                         clock-output-names = "tcon-top-tv0",
 791                                              "tcon-top-tv1",
 792                                              "tcon-top-dsi";
 793                         resets = <&ccu RST_BUS_TCON_TOP>;
 794                         #clock-cells = <1>;
 795
 796                         ports {
 797                                 #address-cells = <1>;
 798                                 #size-cells = <0>;
 799
 800                                 tcon_top_mixer0_in: port@0 {
 801                                         reg = <0>;
 802
 803                                         tcon_top_mixer0_in_mixer0: endpoint {
 804                                                 remote-endpoint = <&mixer0_out_tcon_top>;
 805                                         };
 806                                 };
 807
 808                                 tcon_top_mixer0_out: port@1 {
 809                                         #address-cells = <1>;
 810                                         #size-cells = <0>;
 811                                         reg = <1>;
 812
 813                                         tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
 814                                                 reg = <0>;
 815                                         };
 816
 817                                         tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
 818                                                 reg = <1>;
 819                                         };
 820
 821                                         tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
 822                                                 reg = <2>;
 823                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
 824                                         };
 825
 826                                         tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
 827                                                 reg = <3>;
 828                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
 829                                         };
 830                                 };
 831
 832                                 tcon_top_mixer1_in: port@2 {
 833                                         #address-cells = <1>;
 834                                         #size-cells = <0>;
 835                                         reg = <2>;
 836
 837                                         tcon_top_mixer1_in_mixer1: endpoint@1 {
 838                                                 reg = <1>;
 839                                                 remote-endpoint = <&mixer1_out_tcon_top>;
 840                                         };
 841                                 };
 842
 843                                 tcon_top_mixer1_out: port@3 {
 844                                         #address-cells = <1>;
 845                                         #size-cells = <0>;
 846                                         reg = <3>;
 847
 848                                         tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
 849                                                 reg = <0>;
 850                                         };
 851
 852                                         tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
 853                                                 reg = <1>;
 854                                         };
 855
 856                                         tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
 857                                                 reg = <2>;
 858                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
 859                                         };
 860
 861                                         tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
 862                                                 reg = <3>;
 863                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
 864                                         };
 865                                 };
 866
 867                                 tcon_top_hdmi_in: port@4 {
 868                                         #address-cells = <1>;
 869                                         #size-cells = <0>;
 870                                         reg = <4>;
 871
 872                                         tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
 873                                                 reg = <0>;
 874                                                 remote-endpoint = <&tcon_tv0_out_tcon_top>;
 875                                         };
 876
 877                                         tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
 878                                                 reg = <1>;
 879                                                 remote-endpoint = <&tcon_tv1_out_tcon_top>;
 880                                         };
 881                                 };
 882
 883                                 tcon_top_hdmi_out: port@5 {
 884                                         reg = <5>;
 885
 886                                         tcon_top_hdmi_out_hdmi: endpoint {
 887                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 888                                         };
 889                                 };
 890                         };
 891                 };
 892
 893                 tcon_tv0: lcd-controller@1c73000 {
 894                         compatible = "allwinner,sun8i-r40-tcon-tv";
 895                         reg = <0x01c73000 0x1000>;
 896                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
 898                         clock-names = "ahb", "tcon-ch1";
 899                         resets = <&ccu RST_BUS_TCON_TV0>;
 900                         reset-names = "lcd";
 901                         status = "disabled";
 902
 903                         ports {
 904                                 #address-cells = <1>;
 905                                 #size-cells = <0>;
 906
 907                                 tcon_tv0_in: port@0 {
 908                                         #address-cells = <1>;
 909                                         #size-cells = <0>;
 910                                         reg = <0>;
 911
 912                                         tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
 913                                                 reg = <0>;
 914                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
 915                                         };
 916
 917                                         tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
 918                                                 reg = <1>;
 919                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
 920                                         };
 921                                 };
 922
 923                                 tcon_tv0_out: port@1 {
 924                                         #address-cells = <1>;
 925                                         #size-cells = <0>;
 926                                         reg = <1>;
 927
 928                                         tcon_tv0_out_tcon_top: endpoint@1 {
 929                                                 reg = <1>;
 930                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
 931                                         };
 932                                 };
 933                         };
 934                 };
 935
 936                 tcon_tv1: lcd-controller@1c74000 {
 937                         compatible = "allwinner,sun8i-r40-tcon-tv";
 938                         reg = <0x01c74000 0x1000>;
 939                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 940                         clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
 941                         clock-names = "ahb", "tcon-ch1";
 942                         resets = <&ccu RST_BUS_TCON_TV1>;
 943                         reset-names = "lcd";
 944                         status = "disabled";
 945
 946                         ports {
 947                                 #address-cells = <1>;
 948                                 #size-cells = <0>;
 949
 950                                 tcon_tv1_in: port@0 {
 951                                         #address-cells = <1>;
 952                                         #size-cells = <0>;
 953                                         reg = <0>;
 954
 955                                         tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
 956                                                 reg = <0>;
 957                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
 958                                         };
 959
 960                                         tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
 961                                                 reg = <1>;
 962                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
 963                                         };
 964                                 };
 965
 966                                 tcon_tv1_out: port@1 {
 967                                         #address-cells = <1>;
 968                                         #size-cells = <0>;
 969                                         reg = <1>;
 970
 971                                         tcon_tv1_out_tcon_top: endpoint@1 {
 972                                                 reg = <1>;
 973                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
 974                                         };
 975                                 };
 976                         };
 977                 };
 978
 979                 gic: interrupt-controller@1c81000 {
 980                         compatible = "arm,gic-400";
 981                         reg = <0x01c81000 0x1000>,
 982                               <0x01c82000 0x2000>,
 983                               <0x01c84000 0x2000>,
 984                               <0x01c86000 0x2000>;
 985                         interrupt-controller;
 986                         #interrupt-cells = <3>;
 987                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 988                 };
 989
 990                 hdmi: hdmi@1ee0000 {
 991                         compatible = "allwinner,sun8i-r40-dw-hdmi",
 992                                      "allwinner,sun8i-a83t-dw-hdmi";
 993                         reg = <0x01ee0000 0x10000>;
 994                         reg-io-width = <1>;
 995                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 996                         clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
 997                                  <&ccu CLK_HDMI>;
 998                         clock-names = "iahb", "isfr", "tmds";
 999                         resets = <&ccu RST_BUS_HDMI1>;
1000                         reset-names = "ctrl";
1001                         phys = <&hdmi_phy>;
1002                         phy-names = "phy";
1003                         status = "disabled";
1004
1005                         ports {
1006                                 #address-cells = <1>;
1007                                 #size-cells = <0>;
1008
1009                                 hdmi_in: port@0 {
1010                                         reg = <0>;
1011
1012                                         hdmi_in_tcon_top: endpoint {
1013                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1014                                         };
1015                                 };
1016
1017                                 hdmi_out: port@1 {
1018                                         reg = <1>;
1019                                 };
1020                         };
1021                 };
1022
1023                 hdmi_phy: hdmi-phy@1ef0000 {
1024                         compatible = "allwinner,sun8i-r40-hdmi-phy";
1025                         reg = <0x01ef0000 0x10000>;
1026                         clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1027                                  <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1028                         clock-names = "bus", "mod", "pll-0", "pll-1";
1029                         resets = <&ccu RST_BUS_HDMI0>;
1030                         reset-names = "phy";
1031                         #phy-cells = <0>;
1032                 };
1033         };
1034
1035         pmu {
1036                 compatible = "arm,cortex-a7-pmu";
1037                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1038                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1039                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1040                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1041                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1042         };
1043
1044         timer {
1045                 compatible = "arm,armv7-timer";
1046                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1047                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1048                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1049                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1050         };
1051 };