2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
50 #include <dt-bindings/thermal/thermal.h>
55 interrupt-parent = <&gic>;
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 clock-accuracy = <50000>;
67 clock-output-names = "osc24M";
72 compatible = "fixed-clock";
73 clock-frequency = <32768>;
74 clock-accuracy = <20000>;
75 clock-output-names = "ext-osc32k";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
96 compatible = "arm,cortex-a7";
102 compatible = "arm,cortex-a7";
109 compatible = "allwinner,sun8i-r40-display-engine";
110 allwinner,pipelines = <&mixer0>, <&mixer1>;
115 cpu_thermal: cpu0-thermal {
117 polling-delay-passive = <0>;
119 thermal-sensors = <&ths 0>;
122 gpu_thermal: gpu-thermal {
124 polling-delay-passive = <0>;
126 thermal-sensors = <&ths 1>;
131 compatible = "simple-bus";
132 #address-cells = <1>;
136 display_clocks: clock@1000000 {
137 compatible = "allwinner,sun8i-r40-de2-clk",
138 "allwinner,sun8i-h3-de2-clk";
139 reg = <0x01000000 0x10000>;
140 clocks = <&ccu CLK_BUS_DE>,
144 resets = <&ccu RST_BUS_DE>;
149 mixer0: mixer@1100000 {
150 compatible = "allwinner,sun8i-r40-de2-mixer-0";
151 reg = <0x01100000 0x100000>;
152 clocks = <&display_clocks CLK_BUS_MIXER0>,
153 <&display_clocks CLK_MIXER0>;
156 resets = <&display_clocks RST_MIXER0>;
159 #address-cells = <1>;
164 mixer0_out_tcon_top: endpoint {
165 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
171 mixer1: mixer@1200000 {
172 compatible = "allwinner,sun8i-r40-de2-mixer-1";
173 reg = <0x01200000 0x100000>;
174 clocks = <&display_clocks CLK_BUS_MIXER1>,
175 <&display_clocks CLK_MIXER1>;
178 resets = <&display_clocks RST_WB>;
181 #address-cells = <1>;
186 mixer1_out_tcon_top: endpoint {
187 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
193 deinterlace: deinterlace@1400000 {
194 compatible = "allwinner,sun8i-r40-deinterlace",
195 "allwinner,sun8i-h3-deinterlace";
196 reg = <0x01400000 0x20000>;
197 clocks = <&ccu CLK_BUS_DEINTERLACE>,
198 <&ccu CLK_DEINTERLACE>,
200 * NOTE: Contrary to what datasheet claims,
201 * DRAM deinterlace gate doesn't exist and
202 * it's shared with CSI1.
204 <&ccu CLK_DRAM_CSI1>;
205 clock-names = "bus", "mod", "ram";
206 resets = <&ccu RST_BUS_DEINTERLACE>;
207 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
208 interconnects = <&mbus 9>;
209 interconnect-names = "dma-mem";
212 syscon: system-control@1c00000 {
213 compatible = "allwinner,sun8i-r40-system-control",
214 "allwinner,sun4i-a10-system-control";
215 reg = <0x01c00000 0x30>;
216 #address-cells = <1>;
220 sram_c: sram@1d00000 {
221 compatible = "mmio-sram";
222 reg = <0x01d00000 0xd0000>;
223 #address-cells = <1>;
225 ranges = <0 0x01d00000 0xd0000>;
227 ve_sram: sram-section@0 {
228 compatible = "allwinner,sun8i-r40-sram-c1",
229 "allwinner,sun4i-a10-sram-c1";
230 reg = <0x000000 0x80000>;
235 nmi_intc: interrupt-controller@1c00030 {
236 compatible = "allwinner,sun7i-a20-sc-nmi";
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 reg = <0x01c00030 0x0c>;
240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
243 dma: dma-controller@1c02000 {
244 compatible = "allwinner,sun8i-r40-dma",
245 "allwinner,sun50i-a64-dma";
246 reg = <0x01c02000 0x1000>;
247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&ccu CLK_BUS_DMA>;
251 resets = <&ccu RST_BUS_DMA>;
256 compatible = "allwinner,sun8i-r40-spi",
257 "allwinner,sun8i-h3-spi";
258 reg = <0x01c05000 0x1000>;
259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
261 clock-names = "ahb", "mod";
262 resets = <&ccu RST_BUS_SPI0>;
264 #address-cells = <1>;
269 compatible = "allwinner,sun8i-r40-spi",
270 "allwinner,sun8i-h3-spi";
271 reg = <0x01c06000 0x1000>;
272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
274 clock-names = "ahb", "mod";
275 resets = <&ccu RST_BUS_SPI1>;
277 #address-cells = <1>;
282 compatible = "allwinner,sun8i-r40-csi0",
283 "allwinner,sun7i-a20-csi0";
284 reg = <0x01c09000 0x1000>;
285 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
287 <&ccu CLK_DRAM_CSI0>;
288 clock-names = "bus", "isp", "ram";
289 resets = <&ccu RST_BUS_CSI0>;
290 interconnects = <&mbus 5>;
291 interconnect-names = "dma-mem";
295 video-codec@1c0e000 {
296 compatible = "allwinner,sun8i-r40-video-engine";
297 reg = <0x01c0e000 0x1000>;
298 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
300 clock-names = "ahb", "mod", "ram";
301 resets = <&ccu RST_BUS_VE>;
302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
303 allwinner,sram = <&ve_sram 1>;
307 compatible = "allwinner,sun8i-r40-mmc",
308 "allwinner,sun50i-a64-mmc";
309 reg = <0x01c0f000 0x1000>;
310 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
311 clock-names = "ahb", "mmc";
312 resets = <&ccu RST_BUS_MMC0>;
314 pinctrl-0 = <&mmc0_pins>;
315 pinctrl-names = "default";
316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
323 compatible = "allwinner,sun8i-r40-mmc",
324 "allwinner,sun50i-a64-mmc";
325 reg = <0x01c10000 0x1000>;
326 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
327 clock-names = "ahb", "mmc";
328 resets = <&ccu RST_BUS_MMC1>;
330 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
337 compatible = "allwinner,sun8i-r40-emmc",
338 "allwinner,sun50i-a64-emmc";
339 reg = <0x01c11000 0x1000>;
340 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
341 clock-names = "ahb", "mmc";
342 resets = <&ccu RST_BUS_MMC2>;
344 pinctrl-0 = <&mmc2_pins>;
345 pinctrl-names = "default";
346 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
353 compatible = "allwinner,sun8i-r40-mmc",
354 "allwinner,sun50i-a64-mmc";
355 reg = <0x01c12000 0x1000>;
356 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
357 clock-names = "ahb", "mmc";
358 resets = <&ccu RST_BUS_MMC3>;
360 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
366 usbphy: phy@1c13400 {
367 compatible = "allwinner,sun8i-r40-usb-phy";
368 reg = <0x01c13400 0x14>,
372 reg-names = "phy_ctrl",
376 clocks = <&ccu CLK_USB_PHY0>,
379 clock-names = "usb0_phy",
382 resets = <&ccu RST_USB_PHY0>,
385 reset-names = "usb0_reset",
392 crypto: crypto@1c15000 {
393 compatible = "allwinner,sun8i-r40-crypto";
394 reg = <0x01c15000 0x1000>;
395 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
397 clock-names = "bus", "mod";
398 resets = <&ccu RST_BUS_CE>;
402 compatible = "allwinner,sun8i-r40-spi",
403 "allwinner,sun8i-h3-spi";
404 reg = <0x01c17000 0x1000>;
405 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
407 clock-names = "ahb", "mod";
408 resets = <&ccu RST_BUS_SPI2>;
410 #address-cells = <1>;
415 compatible = "allwinner,sun8i-r40-ahci";
416 reg = <0x01c18000 0x1000>;
417 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
419 resets = <&ccu RST_BUS_SATA>;
420 reset-names = "ahci";
425 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
426 reg = <0x01c19000 0x100>;
427 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&ccu CLK_BUS_EHCI1>;
429 resets = <&ccu RST_BUS_EHCI1>;
436 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
437 reg = <0x01c19400 0x100>;
438 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&ccu CLK_BUS_OHCI1>,
440 <&ccu CLK_USB_OHCI1>;
441 resets = <&ccu RST_BUS_OHCI1>;
448 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
449 reg = <0x01c1c000 0x100>;
450 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&ccu CLK_BUS_EHCI2>;
452 resets = <&ccu RST_BUS_EHCI2>;
459 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
460 reg = <0x01c1c400 0x100>;
461 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&ccu CLK_BUS_OHCI2>,
463 <&ccu CLK_USB_OHCI2>;
464 resets = <&ccu RST_BUS_OHCI2>;
471 compatible = "allwinner,sun8i-r40-spi",
472 "allwinner,sun8i-h3-spi";
473 reg = <0x01c1f000 0x1000>;
474 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
476 clock-names = "ahb", "mod";
477 resets = <&ccu RST_BUS_SPI3>;
479 #address-cells = <1>;
484 compatible = "allwinner,sun8i-r40-ccu";
485 reg = <0x01c20000 0x400>;
486 clocks = <&osc24M>, <&rtc 0>;
487 clock-names = "hosc", "losc";
493 compatible = "allwinner,sun8i-r40-rtc";
494 reg = <0x01c20400 0x400>;
495 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
496 clock-output-names = "osc32k", "osc32k-out";
501 pio: pinctrl@1c20800 {
502 compatible = "allwinner,sun8i-r40-pinctrl";
503 reg = <0x01c20800 0x400>;
504 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
506 clock-names = "apb", "hosc", "losc";
508 interrupt-controller;
509 #interrupt-cells = <3>;
512 clk_out_a_pin: clk-out-a-pin {
514 function = "clk_out_a";
518 csi0_8bits_pins: csi0-8bits-pins {
519 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
520 "PE6", "PE7", "PE8", "PE9", "PE10",
526 csi0_mclk_pin: csi0-mclk-pin {
531 gmac_rgmii_pins: gmac-rgmii-pins {
532 pins = "PA0", "PA1", "PA2", "PA3",
533 "PA4", "PA5", "PA6", "PA7",
534 "PA8", "PA10", "PA11", "PA12",
535 "PA13", "PA15", "PA16";
538 * data lines in RGMII mode use DDR mode
539 * and need a higher signal drive strength
541 drive-strength = <40>;
544 i2c0_pins: i2c0-pins {
549 i2c1_pins: i2c1-pins {
550 pins = "PB18", "PB19";
554 i2c2_pins: i2c2-pins {
555 pins = "PB20", "PB21";
559 i2c3_pins: i2c3-pins {
564 i2c4_pins: i2c4-pins {
579 mmc0_pins: mmc0-pins {
580 pins = "PF0", "PF1", "PF2",
583 drive-strength = <30>;
587 mmc1_pg_pins: mmc1-pg-pins {
588 pins = "PG0", "PG1", "PG2",
591 drive-strength = <30>;
595 mmc2_pins: mmc2-pins {
596 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
597 "PC10", "PC11", "PC12", "PC13", "PC14",
600 drive-strength = <30>;
605 spi0_pc_pins: spi0-pc-pins {
606 pins = "PC0", "PC1", "PC2";
611 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
617 spi1_pi_pins: spi1-pi-pins {
618 pins = "PI17", "PI18", "PI19";
623 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
629 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
634 uart0_pb_pins: uart0-pb-pins {
635 pins = "PB22", "PB23";
639 uart3_pg_pins: uart3-pg-pins {
644 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
650 wdt: watchdog@1c20c90 {
651 compatible = "allwinner,sun4i-a10-wdt";
652 reg = <0x01c20c90 0x10>;
653 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
658 compatible = "allwinner,sun8i-r40-ir",
659 "allwinner,sun6i-a31-ir";
660 reg = <0x01c21800 0x400>;
661 pinctrl-0 = <&ir0_pins>;
662 pinctrl-names = "default";
663 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
664 clock-names = "apb", "ir";
665 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
666 resets = <&ccu RST_BUS_IR0>;
671 compatible = "allwinner,sun8i-r40-ir",
672 "allwinner,sun6i-a31-ir";
673 reg = <0x01c21c00 0x400>;
674 pinctrl-0 = <&ir1_pins>;
675 pinctrl-names = "default";
676 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
677 clock-names = "apb", "ir";
678 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
679 resets = <&ccu RST_BUS_IR1>;
683 ths: thermal-sensor@1c24c00 {
684 compatible = "allwinner,sun8i-r40-ths";
685 reg = <0x01c24c00 0x100>;
686 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
687 clock-names = "bus", "mod";
688 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
689 resets = <&ccu RST_BUS_THS>;
690 /* TODO: add nvmem-cells for calibration */
691 #thermal-sensor-cells = <1>;
694 uart0: serial@1c28000 {
695 compatible = "snps,dw-apb-uart";
696 reg = <0x01c28000 0x400>;
697 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&ccu CLK_BUS_UART0>;
701 resets = <&ccu RST_BUS_UART0>;
705 uart1: serial@1c28400 {
706 compatible = "snps,dw-apb-uart";
707 reg = <0x01c28400 0x400>;
708 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&ccu CLK_BUS_UART1>;
712 resets = <&ccu RST_BUS_UART1>;
716 uart2: serial@1c28800 {
717 compatible = "snps,dw-apb-uart";
718 reg = <0x01c28800 0x400>;
719 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&ccu CLK_BUS_UART2>;
723 resets = <&ccu RST_BUS_UART2>;
727 uart3: serial@1c28c00 {
728 compatible = "snps,dw-apb-uart";
729 reg = <0x01c28c00 0x400>;
730 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&ccu CLK_BUS_UART3>;
734 resets = <&ccu RST_BUS_UART3>;
738 uart4: serial@1c29000 {
739 compatible = "snps,dw-apb-uart";
740 reg = <0x01c29000 0x400>;
741 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&ccu CLK_BUS_UART4>;
745 resets = <&ccu RST_BUS_UART4>;
749 uart5: serial@1c29400 {
750 compatible = "snps,dw-apb-uart";
751 reg = <0x01c29400 0x400>;
752 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&ccu CLK_BUS_UART5>;
756 resets = <&ccu RST_BUS_UART5>;
760 uart6: serial@1c29800 {
761 compatible = "snps,dw-apb-uart";
762 reg = <0x01c29800 0x400>;
763 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&ccu CLK_BUS_UART6>;
767 resets = <&ccu RST_BUS_UART6>;
771 uart7: serial@1c29c00 {
772 compatible = "snps,dw-apb-uart";
773 reg = <0x01c29c00 0x400>;
774 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&ccu CLK_BUS_UART7>;
778 resets = <&ccu RST_BUS_UART7>;
783 compatible = "allwinner,sun6i-a31-i2c";
784 reg = <0x01c2ac00 0x400>;
785 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&ccu CLK_BUS_I2C0>;
787 resets = <&ccu RST_BUS_I2C0>;
788 pinctrl-0 = <&i2c0_pins>;
789 pinctrl-names = "default";
791 #address-cells = <1>;
796 compatible = "allwinner,sun6i-a31-i2c";
797 reg = <0x01c2b000 0x400>;
798 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&ccu CLK_BUS_I2C1>;
800 resets = <&ccu RST_BUS_I2C1>;
801 pinctrl-0 = <&i2c1_pins>;
802 pinctrl-names = "default";
804 #address-cells = <1>;
809 compatible = "allwinner,sun6i-a31-i2c";
810 reg = <0x01c2b400 0x400>;
811 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&ccu CLK_BUS_I2C2>;
813 resets = <&ccu RST_BUS_I2C2>;
814 pinctrl-0 = <&i2c2_pins>;
815 pinctrl-names = "default";
817 #address-cells = <1>;
822 compatible = "allwinner,sun6i-a31-i2c";
823 reg = <0x01c2b800 0x400>;
824 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&ccu CLK_BUS_I2C3>;
826 resets = <&ccu RST_BUS_I2C3>;
827 pinctrl-0 = <&i2c3_pins>;
828 pinctrl-names = "default";
830 #address-cells = <1>;
835 compatible = "allwinner,sun6i-a31-i2c";
836 reg = <0x01c2c000 0x400>;
837 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&ccu CLK_BUS_I2C4>;
839 resets = <&ccu RST_BUS_I2C4>;
840 pinctrl-0 = <&i2c4_pins>;
841 pinctrl-names = "default";
843 #address-cells = <1>;
848 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
849 reg = <0x01c40000 0x10000>;
850 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
857 interrupt-names = "gp",
864 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
865 clock-names = "bus", "core";
866 resets = <&ccu RST_BUS_GPU>;
869 gmac: ethernet@1c50000 {
870 compatible = "allwinner,sun8i-r40-gmac";
872 reg = <0x01c50000 0x10000>;
873 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
874 interrupt-names = "macirq";
875 resets = <&ccu RST_BUS_GMAC>;
876 reset-names = "stmmaceth";
877 clocks = <&ccu CLK_BUS_GMAC>;
878 clock-names = "stmmaceth";
882 compatible = "snps,dwmac-mdio";
883 #address-cells = <1>;
888 mbus: dram-controller@1c62000 {
889 compatible = "allwinner,sun8i-r40-mbus";
890 reg = <0x01c62000 0x1000>;
892 #address-cells = <1>;
894 dma-ranges = <0x00000000 0x40000000 0x80000000>;
895 #interconnect-cells = <1>;
898 tcon_top: tcon-top@1c70000 {
899 compatible = "allwinner,sun8i-r40-tcon-top";
900 reg = <0x01c70000 0x1000>;
901 clocks = <&ccu CLK_BUS_TCON_TOP>,
913 clock-output-names = "tcon-top-tv0",
916 resets = <&ccu RST_BUS_TCON_TOP>;
920 #address-cells = <1>;
923 tcon_top_mixer0_in: port@0 {
926 tcon_top_mixer0_in_mixer0: endpoint {
927 remote-endpoint = <&mixer0_out_tcon_top>;
931 tcon_top_mixer0_out: port@1 {
932 #address-cells = <1>;
936 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
940 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
944 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
946 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
949 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
951 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
955 tcon_top_mixer1_in: port@2 {
956 #address-cells = <1>;
960 tcon_top_mixer1_in_mixer1: endpoint@1 {
962 remote-endpoint = <&mixer1_out_tcon_top>;
966 tcon_top_mixer1_out: port@3 {
967 #address-cells = <1>;
971 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
975 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
979 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
981 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
984 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
986 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
990 tcon_top_hdmi_in: port@4 {
991 #address-cells = <1>;
995 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
997 remote-endpoint = <&tcon_tv0_out_tcon_top>;
1000 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
1002 remote-endpoint = <&tcon_tv1_out_tcon_top>;
1006 tcon_top_hdmi_out: port@5 {
1009 tcon_top_hdmi_out_hdmi: endpoint {
1010 remote-endpoint = <&hdmi_in_tcon_top>;
1016 tcon_tv0: lcd-controller@1c73000 {
1017 compatible = "allwinner,sun8i-r40-tcon-tv";
1018 reg = <0x01c73000 0x1000>;
1019 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
1021 clock-names = "ahb", "tcon-ch1";
1022 resets = <&ccu RST_BUS_TCON_TV0>;
1023 reset-names = "lcd";
1024 status = "disabled";
1027 #address-cells = <1>;
1030 tcon_tv0_in: port@0 {
1031 #address-cells = <1>;
1035 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1037 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1040 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
1042 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1046 tcon_tv0_out: port@1 {
1047 #address-cells = <1>;
1051 tcon_tv0_out_tcon_top: endpoint@1 {
1053 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1059 tcon_tv1: lcd-controller@1c74000 {
1060 compatible = "allwinner,sun8i-r40-tcon-tv";
1061 reg = <0x01c74000 0x1000>;
1062 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
1064 clock-names = "ahb", "tcon-ch1";
1065 resets = <&ccu RST_BUS_TCON_TV1>;
1066 reset-names = "lcd";
1067 status = "disabled";
1070 #address-cells = <1>;
1073 tcon_tv1_in: port@0 {
1074 #address-cells = <1>;
1078 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1080 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
1083 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
1085 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
1089 tcon_tv1_out: port@1 {
1090 #address-cells = <1>;
1094 tcon_tv1_out_tcon_top: endpoint@1 {
1096 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
1102 gic: interrupt-controller@1c81000 {
1103 compatible = "arm,gic-400";
1104 reg = <0x01c81000 0x1000>,
1105 <0x01c82000 0x2000>,
1106 <0x01c84000 0x2000>,
1107 <0x01c86000 0x2000>;
1108 interrupt-controller;
1109 #interrupt-cells = <3>;
1110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1113 hdmi: hdmi@1ee0000 {
1114 compatible = "allwinner,sun8i-r40-dw-hdmi",
1115 "allwinner,sun8i-a83t-dw-hdmi";
1116 reg = <0x01ee0000 0x10000>;
1118 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
1121 clock-names = "iahb", "isfr", "tmds";
1122 resets = <&ccu RST_BUS_HDMI1>;
1123 reset-names = "ctrl";
1126 status = "disabled";
1129 #address-cells = <1>;
1135 hdmi_in_tcon_top: endpoint {
1136 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1146 hdmi_phy: hdmi-phy@1ef0000 {
1147 compatible = "allwinner,sun8i-r40-hdmi-phy";
1148 reg = <0x01ef0000 0x10000>;
1149 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1150 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1151 clock-names = "bus", "mod", "pll-0", "pll-1";
1152 resets = <&ccu RST_BUS_HDMI0>;
1153 reset-names = "phy";
1159 compatible = "arm,cortex-a7-pmu";
1160 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1164 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1168 compatible = "arm,armv7-timer";
1169 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1170 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1171 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1172 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;