2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
50 #include <dt-bindings/thermal/thermal.h>
55 interrupt-parent = <&gic>;
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 clock-accuracy = <50000>;
67 clock-output-names = "osc24M";
72 compatible = "fixed-clock";
73 clock-frequency = <32768>;
74 clock-accuracy = <20000>;
75 clock-output-names = "ext-osc32k";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
96 compatible = "arm,cortex-a7";
102 compatible = "arm,cortex-a7";
109 compatible = "allwinner,sun8i-r40-display-engine";
110 allwinner,pipelines = <&mixer0>, <&mixer1>;
115 cpu_thermal: cpu0-thermal {
117 polling-delay-passive = <0>;
119 thermal-sensors = <&ths 0>;
122 gpu_thermal: gpu-thermal {
124 polling-delay-passive = <0>;
126 thermal-sensors = <&ths 1>;
131 compatible = "simple-bus";
132 #address-cells = <1>;
136 display_clocks: clock@1000000 {
137 compatible = "allwinner,sun8i-r40-de2-clk",
138 "allwinner,sun8i-h3-de2-clk";
139 reg = <0x01000000 0x10000>;
140 clocks = <&ccu CLK_BUS_DE>,
144 resets = <&ccu RST_BUS_DE>;
149 mixer0: mixer@1100000 {
150 compatible = "allwinner,sun8i-r40-de2-mixer-0";
151 reg = <0x01100000 0x100000>;
152 clocks = <&display_clocks CLK_BUS_MIXER0>,
153 <&display_clocks CLK_MIXER0>;
156 resets = <&display_clocks RST_MIXER0>;
159 #address-cells = <1>;
164 mixer0_out_tcon_top: endpoint {
165 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
171 mixer1: mixer@1200000 {
172 compatible = "allwinner,sun8i-r40-de2-mixer-1";
173 reg = <0x01200000 0x100000>;
174 clocks = <&display_clocks CLK_BUS_MIXER1>,
175 <&display_clocks CLK_MIXER1>;
178 resets = <&display_clocks RST_WB>;
181 #address-cells = <1>;
186 mixer1_out_tcon_top: endpoint {
187 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
193 nmi_intc: interrupt-controller@1c00030 {
194 compatible = "allwinner,sun7i-a20-sc-nmi";
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 reg = <0x01c00030 0x0c>;
198 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
202 compatible = "allwinner,sun8i-r40-spi",
203 "allwinner,sun8i-h3-spi";
204 reg = <0x01c05000 0x1000>;
205 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
207 clock-names = "ahb", "mod";
208 resets = <&ccu RST_BUS_SPI0>;
210 #address-cells = <1>;
215 compatible = "allwinner,sun8i-r40-spi",
216 "allwinner,sun8i-h3-spi";
217 reg = <0x01c06000 0x1000>;
218 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
220 clock-names = "ahb", "mod";
221 resets = <&ccu RST_BUS_SPI1>;
223 #address-cells = <1>;
228 compatible = "allwinner,sun8i-r40-csi0",
229 "allwinner,sun7i-a20-csi0";
230 reg = <0x01c09000 0x1000>;
231 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
233 <&ccu CLK_DRAM_CSI0>;
234 clock-names = "bus", "isp", "ram";
235 resets = <&ccu RST_BUS_CSI0>;
236 interconnects = <&mbus 5>;
237 interconnect-names = "dma-mem";
242 compatible = "allwinner,sun8i-r40-mmc",
243 "allwinner,sun50i-a64-mmc";
244 reg = <0x01c0f000 0x1000>;
245 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
246 clock-names = "ahb", "mmc";
247 resets = <&ccu RST_BUS_MMC0>;
249 pinctrl-0 = <&mmc0_pins>;
250 pinctrl-names = "default";
251 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
253 #address-cells = <1>;
258 compatible = "allwinner,sun8i-r40-mmc",
259 "allwinner,sun50i-a64-mmc";
260 reg = <0x01c10000 0x1000>;
261 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
262 clock-names = "ahb", "mmc";
263 resets = <&ccu RST_BUS_MMC1>;
265 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
267 #address-cells = <1>;
272 compatible = "allwinner,sun8i-r40-emmc",
273 "allwinner,sun50i-a64-emmc";
274 reg = <0x01c11000 0x1000>;
275 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
276 clock-names = "ahb", "mmc";
277 resets = <&ccu RST_BUS_MMC2>;
279 pinctrl-0 = <&mmc2_pins>;
280 pinctrl-names = "default";
281 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
283 #address-cells = <1>;
288 compatible = "allwinner,sun8i-r40-mmc",
289 "allwinner,sun50i-a64-mmc";
290 reg = <0x01c12000 0x1000>;
291 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
292 clock-names = "ahb", "mmc";
293 resets = <&ccu RST_BUS_MMC3>;
295 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
297 #address-cells = <1>;
301 usbphy: phy@1c13400 {
302 compatible = "allwinner,sun8i-r40-usb-phy";
303 reg = <0x01c13400 0x14>,
307 reg-names = "phy_ctrl",
311 clocks = <&ccu CLK_USB_PHY0>,
314 clock-names = "usb0_phy",
317 resets = <&ccu RST_USB_PHY0>,
320 reset-names = "usb0_reset",
327 crypto: crypto@1c15000 {
328 compatible = "allwinner,sun8i-r40-crypto";
329 reg = <0x01c15000 0x1000>;
330 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
332 clock-names = "bus", "mod";
333 resets = <&ccu RST_BUS_CE>;
337 compatible = "allwinner,sun8i-r40-spi",
338 "allwinner,sun8i-h3-spi";
339 reg = <0x01c17000 0x1000>;
340 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
342 clock-names = "ahb", "mod";
343 resets = <&ccu RST_BUS_SPI2>;
345 #address-cells = <1>;
350 compatible = "allwinner,sun8i-r40-ahci";
351 reg = <0x01c18000 0x1000>;
352 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
354 resets = <&ccu RST_BUS_SATA>;
355 reset-names = "ahci";
360 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
361 reg = <0x01c19000 0x100>;
362 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&ccu CLK_BUS_EHCI1>;
364 resets = <&ccu RST_BUS_EHCI1>;
371 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
372 reg = <0x01c19400 0x100>;
373 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&ccu CLK_BUS_OHCI1>,
375 <&ccu CLK_USB_OHCI1>;
376 resets = <&ccu RST_BUS_OHCI1>;
383 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
384 reg = <0x01c1c000 0x100>;
385 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ccu CLK_BUS_EHCI2>;
387 resets = <&ccu RST_BUS_EHCI2>;
394 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
395 reg = <0x01c1c400 0x100>;
396 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&ccu CLK_BUS_OHCI2>,
398 <&ccu CLK_USB_OHCI2>;
399 resets = <&ccu RST_BUS_OHCI2>;
406 compatible = "allwinner,sun8i-r40-spi",
407 "allwinner,sun8i-h3-spi";
408 reg = <0x01c1f000 0x1000>;
409 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
411 clock-names = "ahb", "mod";
412 resets = <&ccu RST_BUS_SPI3>;
414 #address-cells = <1>;
419 compatible = "allwinner,sun8i-r40-ccu";
420 reg = <0x01c20000 0x400>;
421 clocks = <&osc24M>, <&rtc 0>;
422 clock-names = "hosc", "losc";
428 compatible = "allwinner,sun8i-r40-rtc";
429 reg = <0x01c20400 0x400>;
430 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
431 clock-output-names = "osc32k", "osc32k-out";
436 pio: pinctrl@1c20800 {
437 compatible = "allwinner,sun8i-r40-pinctrl";
438 reg = <0x01c20800 0x400>;
439 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
441 clock-names = "apb", "hosc", "losc";
443 interrupt-controller;
444 #interrupt-cells = <3>;
447 clk_out_a_pin: clk-out-a-pin {
449 function = "clk_out_a";
453 csi0_8bits_pins: csi0-8bits-pins {
454 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
455 "PE6", "PE7", "PE8", "PE9", "PE10",
461 csi0_mclk_pin: csi0-mclk-pin {
466 gmac_rgmii_pins: gmac-rgmii-pins {
467 pins = "PA0", "PA1", "PA2", "PA3",
468 "PA4", "PA5", "PA6", "PA7",
469 "PA8", "PA10", "PA11", "PA12",
470 "PA13", "PA15", "PA16";
473 * data lines in RGMII mode use DDR mode
474 * and need a higher signal drive strength
476 drive-strength = <40>;
479 i2c0_pins: i2c0-pins {
484 i2c1_pins: i2c1-pins {
485 pins = "PB18", "PB19";
489 i2c2_pins: i2c2-pins {
490 pins = "PB20", "PB21";
494 i2c3_pins: i2c3-pins {
499 i2c4_pins: i2c4-pins {
504 mmc0_pins: mmc0-pins {
505 pins = "PF0", "PF1", "PF2",
508 drive-strength = <30>;
512 mmc1_pg_pins: mmc1-pg-pins {
513 pins = "PG0", "PG1", "PG2",
516 drive-strength = <30>;
520 mmc2_pins: mmc2-pins {
521 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
522 "PC10", "PC11", "PC12", "PC13", "PC14",
525 drive-strength = <30>;
530 spi0_pc_pins: spi0-pc-pins {
531 pins = "PC0", "PC1", "PC2";
536 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
542 spi1_pi_pins: spi1-pi-pins {
543 pins = "PI17", "PI18", "PI19";
548 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
554 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
559 uart0_pb_pins: uart0-pb-pins {
560 pins = "PB22", "PB23";
564 uart3_pg_pins: uart3-pg-pins {
569 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
575 wdt: watchdog@1c20c90 {
576 compatible = "allwinner,sun4i-a10-wdt";
577 reg = <0x01c20c90 0x10>;
578 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
582 ths: thermal-sensor@1c24c00 {
583 compatible = "allwinner,sun8i-r40-ths";
584 reg = <0x01c24c00 0x100>;
585 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
586 clock-names = "bus", "mod";
587 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
588 resets = <&ccu RST_BUS_THS>;
589 /* TODO: add nvmem-cells for calibration */
590 #thermal-sensor-cells = <1>;
593 uart0: serial@1c28000 {
594 compatible = "snps,dw-apb-uart";
595 reg = <0x01c28000 0x400>;
596 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&ccu CLK_BUS_UART0>;
600 resets = <&ccu RST_BUS_UART0>;
604 uart1: serial@1c28400 {
605 compatible = "snps,dw-apb-uart";
606 reg = <0x01c28400 0x400>;
607 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&ccu CLK_BUS_UART1>;
611 resets = <&ccu RST_BUS_UART1>;
615 uart2: serial@1c28800 {
616 compatible = "snps,dw-apb-uart";
617 reg = <0x01c28800 0x400>;
618 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&ccu CLK_BUS_UART2>;
622 resets = <&ccu RST_BUS_UART2>;
626 uart3: serial@1c28c00 {
627 compatible = "snps,dw-apb-uart";
628 reg = <0x01c28c00 0x400>;
629 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&ccu CLK_BUS_UART3>;
633 resets = <&ccu RST_BUS_UART3>;
637 uart4: serial@1c29000 {
638 compatible = "snps,dw-apb-uart";
639 reg = <0x01c29000 0x400>;
640 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&ccu CLK_BUS_UART4>;
644 resets = <&ccu RST_BUS_UART4>;
648 uart5: serial@1c29400 {
649 compatible = "snps,dw-apb-uart";
650 reg = <0x01c29400 0x400>;
651 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&ccu CLK_BUS_UART5>;
655 resets = <&ccu RST_BUS_UART5>;
659 uart6: serial@1c29800 {
660 compatible = "snps,dw-apb-uart";
661 reg = <0x01c29800 0x400>;
662 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&ccu CLK_BUS_UART6>;
666 resets = <&ccu RST_BUS_UART6>;
670 uart7: serial@1c29c00 {
671 compatible = "snps,dw-apb-uart";
672 reg = <0x01c29c00 0x400>;
673 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&ccu CLK_BUS_UART7>;
677 resets = <&ccu RST_BUS_UART7>;
682 compatible = "allwinner,sun6i-a31-i2c";
683 reg = <0x01c2ac00 0x400>;
684 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&ccu CLK_BUS_I2C0>;
686 resets = <&ccu RST_BUS_I2C0>;
687 pinctrl-0 = <&i2c0_pins>;
688 pinctrl-names = "default";
690 #address-cells = <1>;
695 compatible = "allwinner,sun6i-a31-i2c";
696 reg = <0x01c2b000 0x400>;
697 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&ccu CLK_BUS_I2C1>;
699 resets = <&ccu RST_BUS_I2C1>;
700 pinctrl-0 = <&i2c1_pins>;
701 pinctrl-names = "default";
703 #address-cells = <1>;
708 compatible = "allwinner,sun6i-a31-i2c";
709 reg = <0x01c2b400 0x400>;
710 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&ccu CLK_BUS_I2C2>;
712 resets = <&ccu RST_BUS_I2C2>;
713 pinctrl-0 = <&i2c2_pins>;
714 pinctrl-names = "default";
716 #address-cells = <1>;
721 compatible = "allwinner,sun6i-a31-i2c";
722 reg = <0x01c2b800 0x400>;
723 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&ccu CLK_BUS_I2C3>;
725 resets = <&ccu RST_BUS_I2C3>;
726 pinctrl-0 = <&i2c3_pins>;
727 pinctrl-names = "default";
729 #address-cells = <1>;
734 compatible = "allwinner,sun6i-a31-i2c";
735 reg = <0x01c2c000 0x400>;
736 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&ccu CLK_BUS_I2C4>;
738 resets = <&ccu RST_BUS_I2C4>;
739 pinctrl-0 = <&i2c4_pins>;
740 pinctrl-names = "default";
742 #address-cells = <1>;
746 gmac: ethernet@1c50000 {
747 compatible = "allwinner,sun8i-r40-gmac";
749 reg = <0x01c50000 0x10000>;
750 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
751 interrupt-names = "macirq";
752 resets = <&ccu RST_BUS_GMAC>;
753 reset-names = "stmmaceth";
754 clocks = <&ccu CLK_BUS_GMAC>;
755 clock-names = "stmmaceth";
759 compatible = "snps,dwmac-mdio";
760 #address-cells = <1>;
765 mbus: dram-controller@1c62000 {
766 compatible = "allwinner,sun8i-r40-mbus";
767 reg = <0x01c62000 0x1000>;
769 #address-cells = <1>;
771 dma-ranges = <0x00000000 0x40000000 0x80000000>;
772 #interconnect-cells = <1>;
775 tcon_top: tcon-top@1c70000 {
776 compatible = "allwinner,sun8i-r40-tcon-top";
777 reg = <0x01c70000 0x1000>;
778 clocks = <&ccu CLK_BUS_TCON_TOP>,
790 clock-output-names = "tcon-top-tv0",
793 resets = <&ccu RST_BUS_TCON_TOP>;
797 #address-cells = <1>;
800 tcon_top_mixer0_in: port@0 {
803 tcon_top_mixer0_in_mixer0: endpoint {
804 remote-endpoint = <&mixer0_out_tcon_top>;
808 tcon_top_mixer0_out: port@1 {
809 #address-cells = <1>;
813 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
817 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
821 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
823 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
826 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
828 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
832 tcon_top_mixer1_in: port@2 {
833 #address-cells = <1>;
837 tcon_top_mixer1_in_mixer1: endpoint@1 {
839 remote-endpoint = <&mixer1_out_tcon_top>;
843 tcon_top_mixer1_out: port@3 {
844 #address-cells = <1>;
848 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
852 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
856 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
858 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
861 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
863 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
867 tcon_top_hdmi_in: port@4 {
868 #address-cells = <1>;
872 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
874 remote-endpoint = <&tcon_tv0_out_tcon_top>;
877 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
879 remote-endpoint = <&tcon_tv1_out_tcon_top>;
883 tcon_top_hdmi_out: port@5 {
886 tcon_top_hdmi_out_hdmi: endpoint {
887 remote-endpoint = <&hdmi_in_tcon_top>;
893 tcon_tv0: lcd-controller@1c73000 {
894 compatible = "allwinner,sun8i-r40-tcon-tv";
895 reg = <0x01c73000 0x1000>;
896 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
898 clock-names = "ahb", "tcon-ch1";
899 resets = <&ccu RST_BUS_TCON_TV0>;
904 #address-cells = <1>;
907 tcon_tv0_in: port@0 {
908 #address-cells = <1>;
912 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
914 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
917 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
919 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
923 tcon_tv0_out: port@1 {
924 #address-cells = <1>;
928 tcon_tv0_out_tcon_top: endpoint@1 {
930 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
936 tcon_tv1: lcd-controller@1c74000 {
937 compatible = "allwinner,sun8i-r40-tcon-tv";
938 reg = <0x01c74000 0x1000>;
939 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
941 clock-names = "ahb", "tcon-ch1";
942 resets = <&ccu RST_BUS_TCON_TV1>;
947 #address-cells = <1>;
950 tcon_tv1_in: port@0 {
951 #address-cells = <1>;
955 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
957 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
960 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
962 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
966 tcon_tv1_out: port@1 {
967 #address-cells = <1>;
971 tcon_tv1_out_tcon_top: endpoint@1 {
973 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
979 gic: interrupt-controller@1c81000 {
980 compatible = "arm,gic-400";
981 reg = <0x01c81000 0x1000>,
985 interrupt-controller;
986 #interrupt-cells = <3>;
987 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
991 compatible = "allwinner,sun8i-r40-dw-hdmi",
992 "allwinner,sun8i-a83t-dw-hdmi";
993 reg = <0x01ee0000 0x10000>;
995 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
998 clock-names = "iahb", "isfr", "tmds";
999 resets = <&ccu RST_BUS_HDMI1>;
1000 reset-names = "ctrl";
1003 status = "disabled";
1006 #address-cells = <1>;
1012 hdmi_in_tcon_top: endpoint {
1013 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1023 hdmi_phy: hdmi-phy@1ef0000 {
1024 compatible = "allwinner,sun8i-r40-hdmi-phy";
1025 reg = <0x01ef0000 0x10000>;
1026 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1027 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1028 clock-names = "bus", "mod", "pll-0", "pll-1";
1029 resets = <&ccu RST_BUS_HDMI0>;
1030 reset-names = "phy";
1036 compatible = "arm,cortex-a7-pmu";
1037 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1041 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1045 compatible = "arm,armv7-timer";
1046 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1047 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1048 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1049 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;