2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
54 interrupt-parent = <&gic>;
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-accuracy = <50000>;
66 clock-output-names = "osc24M";
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
73 clock-accuracy = <20000>;
74 clock-output-names = "ext-osc32k";
83 compatible = "arm,cortex-a7";
89 compatible = "arm,cortex-a7";
95 compatible = "arm,cortex-a7";
101 compatible = "arm,cortex-a7";
108 compatible = "allwinner,sun8i-r40-display-engine";
109 allwinner,pipelines = <&mixer0>, <&mixer1>;
114 compatible = "simple-bus";
115 #address-cells = <1>;
119 display_clocks: clock@1000000 {
120 compatible = "allwinner,sun8i-r40-de2-clk",
121 "allwinner,sun8i-h3-de2-clk";
122 reg = <0x01000000 0x100000>;
123 clocks = <&ccu CLK_BUS_DE>,
127 resets = <&ccu RST_BUS_DE>;
132 mixer0: mixer@1100000 {
133 compatible = "allwinner,sun8i-r40-de2-mixer-0";
134 reg = <0x01100000 0x100000>;
135 clocks = <&display_clocks CLK_BUS_MIXER0>,
136 <&display_clocks CLK_MIXER0>;
139 resets = <&display_clocks RST_MIXER0>;
142 #address-cells = <1>;
147 mixer0_out_tcon_top: endpoint {
148 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
154 mixer1: mixer@1200000 {
155 compatible = "allwinner,sun8i-r40-de2-mixer-1";
156 reg = <0x01200000 0x100000>;
157 clocks = <&display_clocks CLK_BUS_MIXER1>,
158 <&display_clocks CLK_MIXER1>;
161 resets = <&display_clocks RST_WB>;
164 #address-cells = <1>;
169 mixer1_out_tcon_top: endpoint {
170 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
176 nmi_intc: interrupt-controller@1c00030 {
177 compatible = "allwinner,sun7i-a20-sc-nmi";
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 reg = <0x01c00030 0x0c>;
181 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
185 compatible = "allwinner,sun8i-r40-csi0",
186 "allwinner,sun7i-a20-csi0";
187 reg = <0x01c09000 0x1000>;
188 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
190 <&ccu CLK_DRAM_CSI0>;
191 clock-names = "bus", "isp", "ram";
192 resets = <&ccu RST_BUS_CSI0>;
193 interconnects = <&mbus 5>;
194 interconnect-names = "dma-mem";
199 compatible = "allwinner,sun8i-r40-mmc",
200 "allwinner,sun50i-a64-mmc";
201 reg = <0x01c0f000 0x1000>;
202 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
203 clock-names = "ahb", "mmc";
204 resets = <&ccu RST_BUS_MMC0>;
206 pinctrl-0 = <&mmc0_pins>;
207 pinctrl-names = "default";
208 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
210 #address-cells = <1>;
215 compatible = "allwinner,sun8i-r40-mmc",
216 "allwinner,sun50i-a64-mmc";
217 reg = <0x01c10000 0x1000>;
218 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
219 clock-names = "ahb", "mmc";
220 resets = <&ccu RST_BUS_MMC1>;
222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>;
229 compatible = "allwinner,sun8i-r40-emmc",
230 "allwinner,sun50i-a64-emmc";
231 reg = <0x01c11000 0x1000>;
232 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
233 clock-names = "ahb", "mmc";
234 resets = <&ccu RST_BUS_MMC2>;
236 pinctrl-0 = <&mmc2_pins>;
237 pinctrl-names = "default";
238 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
240 #address-cells = <1>;
245 compatible = "allwinner,sun8i-r40-mmc",
246 "allwinner,sun50i-a64-mmc";
247 reg = <0x01c12000 0x1000>;
248 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
249 clock-names = "ahb", "mmc";
250 resets = <&ccu RST_BUS_MMC3>;
252 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
258 usbphy: phy@1c13400 {
259 compatible = "allwinner,sun8i-r40-usb-phy";
260 reg = <0x01c13400 0x14>,
264 reg-names = "phy_ctrl",
268 clocks = <&ccu CLK_USB_PHY0>,
271 clock-names = "usb0_phy",
274 resets = <&ccu RST_USB_PHY0>,
277 reset-names = "usb0_reset",
284 crypto: crypto@1c15000 {
285 compatible = "allwinner,sun8i-r40-crypto";
286 reg = <0x01c15000 0x1000>;
287 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
289 clock-names = "bus", "mod";
290 resets = <&ccu RST_BUS_CE>;
294 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
295 reg = <0x01c19000 0x100>;
296 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&ccu CLK_BUS_EHCI1>;
298 resets = <&ccu RST_BUS_EHCI1>;
305 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
306 reg = <0x01c19400 0x100>;
307 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&ccu CLK_BUS_OHCI1>,
309 <&ccu CLK_USB_OHCI1>;
310 resets = <&ccu RST_BUS_OHCI1>;
317 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
318 reg = <0x01c1c000 0x100>;
319 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&ccu CLK_BUS_EHCI2>;
321 resets = <&ccu RST_BUS_EHCI2>;
328 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
329 reg = <0x01c1c400 0x100>;
330 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&ccu CLK_BUS_OHCI2>,
332 <&ccu CLK_USB_OHCI2>;
333 resets = <&ccu RST_BUS_OHCI2>;
340 compatible = "allwinner,sun8i-r40-ccu";
341 reg = <0x01c20000 0x400>;
342 clocks = <&osc24M>, <&rtc 0>;
343 clock-names = "hosc", "losc";
349 compatible = "allwinner,sun8i-r40-rtc";
350 reg = <0x01c20400 0x400>;
351 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
352 clock-output-names = "osc32k", "osc32k-out";
357 pio: pinctrl@1c20800 {
358 compatible = "allwinner,sun8i-r40-pinctrl";
359 reg = <0x01c20800 0x400>;
360 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
362 clock-names = "apb", "hosc", "losc";
364 interrupt-controller;
365 #interrupt-cells = <3>;
368 clk_out_a_pin: clk-out-a-pin {
370 function = "clk_out_a";
374 csi0_8bits_pins: csi0-8bits-pins {
375 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
376 "PE6", "PE7", "PE8", "PE9", "PE10",
382 csi0_mclk_pin: csi0-mclk-pin {
387 gmac_rgmii_pins: gmac-rgmii-pins {
388 pins = "PA0", "PA1", "PA2", "PA3",
389 "PA4", "PA5", "PA6", "PA7",
390 "PA8", "PA10", "PA11", "PA12",
391 "PA13", "PA15", "PA16";
394 * data lines in RGMII mode use DDR mode
395 * and need a higher signal drive strength
397 drive-strength = <40>;
400 i2c0_pins: i2c0-pins {
405 i2c1_pins: i2c1-pins {
406 pins = "PB18", "PB19";
410 i2c2_pins: i2c2-pins {
411 pins = "PB20", "PB21";
415 i2c3_pins: i2c3-pins {
420 i2c4_pins: i2c4-pins {
425 mmc0_pins: mmc0-pins {
426 pins = "PF0", "PF1", "PF2",
429 drive-strength = <30>;
433 mmc1_pg_pins: mmc1-pg-pins {
434 pins = "PG0", "PG1", "PG2",
437 drive-strength = <30>;
441 mmc2_pins: mmc2-pins {
442 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
443 "PC10", "PC11", "PC12", "PC13", "PC14",
446 drive-strength = <30>;
451 spi0_pc_pins: spi0-pc-pins {
452 pins = "PC0", "PC1", "PC2";
457 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
463 spi1_pi_pins: spi1-pi-pins {
464 pins = "PI17", "PI18", "PI19";
469 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
475 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
480 uart0_pb_pins: uart0-pb-pins {
481 pins = "PB22", "PB23";
485 uart3_pg_pins: uart3-pg-pins {
490 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
496 wdt: watchdog@1c20c90 {
497 compatible = "allwinner,sun4i-a10-wdt";
498 reg = <0x01c20c90 0x10>;
499 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
503 uart0: serial@1c28000 {
504 compatible = "snps,dw-apb-uart";
505 reg = <0x01c28000 0x400>;
506 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&ccu CLK_BUS_UART0>;
510 resets = <&ccu RST_BUS_UART0>;
514 uart1: serial@1c28400 {
515 compatible = "snps,dw-apb-uart";
516 reg = <0x01c28400 0x400>;
517 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&ccu CLK_BUS_UART1>;
521 resets = <&ccu RST_BUS_UART1>;
525 uart2: serial@1c28800 {
526 compatible = "snps,dw-apb-uart";
527 reg = <0x01c28800 0x400>;
528 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&ccu CLK_BUS_UART2>;
532 resets = <&ccu RST_BUS_UART2>;
536 uart3: serial@1c28c00 {
537 compatible = "snps,dw-apb-uart";
538 reg = <0x01c28c00 0x400>;
539 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&ccu CLK_BUS_UART3>;
543 resets = <&ccu RST_BUS_UART3>;
547 uart4: serial@1c29000 {
548 compatible = "snps,dw-apb-uart";
549 reg = <0x01c29000 0x400>;
550 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ccu CLK_BUS_UART4>;
554 resets = <&ccu RST_BUS_UART4>;
558 uart5: serial@1c29400 {
559 compatible = "snps,dw-apb-uart";
560 reg = <0x01c29400 0x400>;
561 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&ccu CLK_BUS_UART5>;
565 resets = <&ccu RST_BUS_UART5>;
569 uart6: serial@1c29800 {
570 compatible = "snps,dw-apb-uart";
571 reg = <0x01c29800 0x400>;
572 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&ccu CLK_BUS_UART6>;
576 resets = <&ccu RST_BUS_UART6>;
580 uart7: serial@1c29c00 {
581 compatible = "snps,dw-apb-uart";
582 reg = <0x01c29c00 0x400>;
583 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&ccu CLK_BUS_UART7>;
587 resets = <&ccu RST_BUS_UART7>;
592 compatible = "allwinner,sun6i-a31-i2c";
593 reg = <0x01c2ac00 0x400>;
594 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&ccu CLK_BUS_I2C0>;
596 resets = <&ccu RST_BUS_I2C0>;
597 pinctrl-0 = <&i2c0_pins>;
598 pinctrl-names = "default";
600 #address-cells = <1>;
605 compatible = "allwinner,sun6i-a31-i2c";
606 reg = <0x01c2b000 0x400>;
607 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&ccu CLK_BUS_I2C1>;
609 resets = <&ccu RST_BUS_I2C1>;
610 pinctrl-0 = <&i2c1_pins>;
611 pinctrl-names = "default";
613 #address-cells = <1>;
618 compatible = "allwinner,sun6i-a31-i2c";
619 reg = <0x01c2b400 0x400>;
620 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&ccu CLK_BUS_I2C2>;
622 resets = <&ccu RST_BUS_I2C2>;
623 pinctrl-0 = <&i2c2_pins>;
624 pinctrl-names = "default";
626 #address-cells = <1>;
631 compatible = "allwinner,sun6i-a31-i2c";
632 reg = <0x01c2b800 0x400>;
633 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&ccu CLK_BUS_I2C3>;
635 resets = <&ccu RST_BUS_I2C3>;
636 pinctrl-0 = <&i2c3_pins>;
637 pinctrl-names = "default";
639 #address-cells = <1>;
644 compatible = "allwinner,sun6i-a31-i2c";
645 reg = <0x01c2c000 0x400>;
646 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&ccu CLK_BUS_I2C4>;
648 resets = <&ccu RST_BUS_I2C4>;
649 pinctrl-0 = <&i2c4_pins>;
650 pinctrl-names = "default";
652 #address-cells = <1>;
657 compatible = "allwinner,sun8i-r40-spi",
658 "allwinner,sun8i-h3-spi";
659 reg = <0x01c05000 0x1000>;
660 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
662 clock-names = "ahb", "mod";
663 resets = <&ccu RST_BUS_SPI0>;
665 #address-cells = <1>;
670 compatible = "allwinner,sun8i-r40-spi",
671 "allwinner,sun8i-h3-spi";
672 reg = <0x01c06000 0x1000>;
673 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
675 clock-names = "ahb", "mod";
676 resets = <&ccu RST_BUS_SPI1>;
678 #address-cells = <1>;
683 compatible = "allwinner,sun8i-r40-spi",
684 "allwinner,sun8i-h3-spi";
685 reg = <0x01c07000 0x1000>;
686 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
688 clock-names = "ahb", "mod";
689 resets = <&ccu RST_BUS_SPI2>;
691 #address-cells = <1>;
696 compatible = "allwinner,sun8i-r40-spi",
697 "allwinner,sun8i-h3-spi";
698 reg = <0x01c0f000 0x1000>;
699 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
701 clock-names = "ahb", "mod";
702 resets = <&ccu RST_BUS_SPI3>;
704 #address-cells = <1>;
709 compatible = "allwinner,sun8i-r40-ahci";
710 reg = <0x01c18000 0x1000>;
711 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
713 resets = <&ccu RST_BUS_SATA>;
714 reset-names = "ahci";
719 gmac: ethernet@1c50000 {
720 compatible = "allwinner,sun8i-r40-gmac";
722 reg = <0x01c50000 0x10000>;
723 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "macirq";
725 resets = <&ccu RST_BUS_GMAC>;
726 reset-names = "stmmaceth";
727 clocks = <&ccu CLK_BUS_GMAC>;
728 clock-names = "stmmaceth";
732 compatible = "snps,dwmac-mdio";
733 #address-cells = <1>;
738 mbus: dram-controller@1c62000 {
739 compatible = "allwinner,sun8i-r40-mbus";
740 reg = <0x01c62000 0x1000>;
742 dma-ranges = <0x00000000 0x40000000 0x80000000>;
743 #interconnect-cells = <1>;
746 tcon_top: tcon-top@1c70000 {
747 compatible = "allwinner,sun8i-r40-tcon-top";
748 reg = <0x01c70000 0x1000>;
749 clocks = <&ccu CLK_BUS_TCON_TOP>,
761 clock-output-names = "tcon-top-tv0",
764 resets = <&ccu RST_BUS_TCON_TOP>;
768 #address-cells = <1>;
771 tcon_top_mixer0_in: port@0 {
774 tcon_top_mixer0_in_mixer0: endpoint {
775 remote-endpoint = <&mixer0_out_tcon_top>;
779 tcon_top_mixer0_out: port@1 {
780 #address-cells = <1>;
784 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
788 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
792 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
794 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
797 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
799 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
803 tcon_top_mixer1_in: port@2 {
804 #address-cells = <1>;
808 tcon_top_mixer1_in_mixer1: endpoint@1 {
810 remote-endpoint = <&mixer1_out_tcon_top>;
814 tcon_top_mixer1_out: port@3 {
815 #address-cells = <1>;
819 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
823 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
827 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
829 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
832 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
834 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
838 tcon_top_hdmi_in: port@4 {
839 #address-cells = <1>;
843 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
845 remote-endpoint = <&tcon_tv0_out_tcon_top>;
848 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
850 remote-endpoint = <&tcon_tv1_out_tcon_top>;
854 tcon_top_hdmi_out: port@5 {
857 tcon_top_hdmi_out_hdmi: endpoint {
858 remote-endpoint = <&hdmi_in_tcon_top>;
864 tcon_tv0: lcd-controller@1c73000 {
865 compatible = "allwinner,sun8i-r40-tcon-tv";
866 reg = <0x01c73000 0x1000>;
867 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
869 clock-names = "ahb", "tcon-ch1";
870 resets = <&ccu RST_BUS_TCON_TV0>;
875 #address-cells = <1>;
878 tcon_tv0_in: port@0 {
879 #address-cells = <1>;
883 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
885 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
888 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
890 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
894 tcon_tv0_out: port@1 {
895 #address-cells = <1>;
899 tcon_tv0_out_tcon_top: endpoint@1 {
901 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
907 tcon_tv1: lcd-controller@1c74000 {
908 compatible = "allwinner,sun8i-r40-tcon-tv";
909 reg = <0x01c74000 0x1000>;
910 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
912 clock-names = "ahb", "tcon-ch1";
913 resets = <&ccu RST_BUS_TCON_TV1>;
918 #address-cells = <1>;
921 tcon_tv1_in: port@0 {
922 #address-cells = <1>;
926 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
928 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
931 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
933 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
937 tcon_tv1_out: port@1 {
938 #address-cells = <1>;
942 tcon_tv1_out_tcon_top: endpoint@1 {
944 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
950 gic: interrupt-controller@1c81000 {
951 compatible = "arm,gic-400";
952 reg = <0x01c81000 0x1000>,
956 interrupt-controller;
957 #interrupt-cells = <3>;
958 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
962 compatible = "allwinner,sun8i-r40-dw-hdmi",
963 "allwinner,sun8i-a83t-dw-hdmi";
964 reg = <0x01ee0000 0x10000>;
966 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
969 clock-names = "iahb", "isfr", "tmds";
970 resets = <&ccu RST_BUS_HDMI1>;
971 reset-names = "ctrl";
977 #address-cells = <1>;
983 hdmi_in_tcon_top: endpoint {
984 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
994 hdmi_phy: hdmi-phy@1ef0000 {
995 compatible = "allwinner,sun8i-r40-hdmi-phy";
996 reg = <0x01ef0000 0x10000>;
997 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
998 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
999 clock-names = "bus", "mod", "pll-0", "pll-1";
1000 resets = <&ccu RST_BUS_HDMI0>;
1001 reset-names = "phy";
1007 compatible = "arm,cortex-a7-pmu";
1008 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1010 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1011 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1012 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1016 compatible = "arm,armv7-timer";
1017 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1018 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1019 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1020 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;