Merge tag 'iio-fixes-for-5.6a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / sun8i-r40.dtsi
1 /*
2  * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3  * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
4  *
5  * This file is dual-licensed: you can use it either under the terms
6  * of the GPL or the X11 license, at your option. Note that this dual
7  * licensing only applies to this file, and not this project as a
8  * whole.
9  *
10  *  a) This file is free software; you can redistribute it and/or
11  *     modify it under the terms of the GNU General Public License as
12  *     published by the Free Software Foundation; either version 2 of the
13  *     License, or (at your option) any later version.
14  *
15  *     This file is distributed in the hope that it will be useful,
16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *     GNU General Public License for more details.
19  *
20  * Or, alternatively,
21  *
22  *  b) Permission is hereby granted, free of charge, to any person
23  *     obtaining a copy of this software and associated documentation
24  *     files (the "Software"), to deal in the Software without
25  *     restriction, including without limitation the rights to use,
26  *     copy, modify, merge, publish, distribute, sublicense, and/or
27  *     sell copies of the Software, and to permit persons to whom the
28  *     Software is furnished to do so, subject to the following
29  *     conditions:
30  *
31  *     The above copyright notice and this permission notice shall be
32  *     included in all copies or substantial portions of the Software.
33  *
34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41  *     OTHER DEALINGS IN THE SOFTWARE.
42  */
43
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
50
51 / {
52         #address-cells = <1>;
53         #size-cells = <1>;
54         interrupt-parent = <&gic>;
55
56         clocks {
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 ranges;
60
61                 osc24M: osc24M {
62                         #clock-cells = <0>;
63                         compatible = "fixed-clock";
64                         clock-frequency = <24000000>;
65                         clock-accuracy = <50000>;
66                         clock-output-names = "osc24M";
67                 };
68
69                 osc32k: osc32k {
70                         #clock-cells = <0>;
71                         compatible = "fixed-clock";
72                         clock-frequency = <32768>;
73                         clock-accuracy = <20000>;
74                         clock-output-names = "ext-osc32k";
75                 };
76         };
77
78         cpus {
79                 #address-cells = <1>;
80                 #size-cells = <0>;
81
82                 cpu0: cpu@0 {
83                         compatible = "arm,cortex-a7";
84                         device_type = "cpu";
85                         reg = <0>;
86                 };
87
88                 cpu1: cpu@1 {
89                         compatible = "arm,cortex-a7";
90                         device_type = "cpu";
91                         reg = <1>;
92                 };
93
94                 cpu2: cpu@2 {
95                         compatible = "arm,cortex-a7";
96                         device_type = "cpu";
97                         reg = <2>;
98                 };
99
100                 cpu3: cpu@3 {
101                         compatible = "arm,cortex-a7";
102                         device_type = "cpu";
103                         reg = <3>;
104                 };
105         };
106
107         de: display-engine {
108                 compatible = "allwinner,sun8i-r40-display-engine";
109                 allwinner,pipelines = <&mixer0>, <&mixer1>;
110                 status = "disabled";
111         };
112
113         soc {
114                 compatible = "simple-bus";
115                 #address-cells = <1>;
116                 #size-cells = <1>;
117                 ranges;
118
119                 display_clocks: clock@1000000 {
120                         compatible = "allwinner,sun8i-r40-de2-clk",
121                                      "allwinner,sun8i-h3-de2-clk";
122                         reg = <0x01000000 0x100000>;
123                         clocks = <&ccu CLK_BUS_DE>,
124                                  <&ccu CLK_DE>;
125                         clock-names = "bus",
126                                       "mod";
127                         resets = <&ccu RST_BUS_DE>;
128                         #clock-cells = <1>;
129                         #reset-cells = <1>;
130                 };
131
132                 mixer0: mixer@1100000 {
133                         compatible = "allwinner,sun8i-r40-de2-mixer-0";
134                         reg = <0x01100000 0x100000>;
135                         clocks = <&display_clocks CLK_BUS_MIXER0>,
136                                  <&display_clocks CLK_MIXER0>;
137                         clock-names = "bus",
138                                       "mod";
139                         resets = <&display_clocks RST_MIXER0>;
140
141                         ports {
142                                 #address-cells = <1>;
143                                 #size-cells = <0>;
144
145                                 mixer0_out: port@1 {
146                                         reg = <1>;
147                                         mixer0_out_tcon_top: endpoint {
148                                                 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
149                                         };
150                                 };
151                         };
152                 };
153
154                 mixer1: mixer@1200000 {
155                         compatible = "allwinner,sun8i-r40-de2-mixer-1";
156                         reg = <0x01200000 0x100000>;
157                         clocks = <&display_clocks CLK_BUS_MIXER1>,
158                                  <&display_clocks CLK_MIXER1>;
159                         clock-names = "bus",
160                                       "mod";
161                         resets = <&display_clocks RST_WB>;
162
163                         ports {
164                                 #address-cells = <1>;
165                                 #size-cells = <0>;
166
167                                 mixer1_out: port@1 {
168                                         reg = <1>;
169                                         mixer1_out_tcon_top: endpoint {
170                                                 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
171                                         };
172                                 };
173                         };
174                 };
175
176                 nmi_intc: interrupt-controller@1c00030 {
177                         compatible = "allwinner,sun7i-a20-sc-nmi";
178                         interrupt-controller;
179                         #interrupt-cells = <2>;
180                         reg = <0x01c00030 0x0c>;
181                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
182                 };
183
184                 csi0: csi@1c09000 {
185                         compatible = "allwinner,sun8i-r40-csi0",
186                                      "allwinner,sun7i-a20-csi0";
187                         reg = <0x01c09000 0x1000>;
188                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
189                         clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
190                                  <&ccu CLK_DRAM_CSI0>;
191                         clock-names = "bus", "isp", "ram";
192                         resets = <&ccu RST_BUS_CSI0>;
193                         interconnects = <&mbus 5>;
194                         interconnect-names = "dma-mem";
195                         status = "disabled";
196                 };
197
198                 mmc0: mmc@1c0f000 {
199                         compatible = "allwinner,sun8i-r40-mmc",
200                                      "allwinner,sun50i-a64-mmc";
201                         reg = <0x01c0f000 0x1000>;
202                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
203                         clock-names = "ahb", "mmc";
204                         resets = <&ccu RST_BUS_MMC0>;
205                         reset-names = "ahb";
206                         pinctrl-0 = <&mmc0_pins>;
207                         pinctrl-names = "default";
208                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
209                         status = "disabled";
210                         #address-cells = <1>;
211                         #size-cells = <0>;
212                 };
213
214                 mmc1: mmc@1c10000 {
215                         compatible = "allwinner,sun8i-r40-mmc",
216                                      "allwinner,sun50i-a64-mmc";
217                         reg = <0x01c10000 0x1000>;
218                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
219                         clock-names = "ahb", "mmc";
220                         resets = <&ccu RST_BUS_MMC1>;
221                         reset-names = "ahb";
222                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
223                         status = "disabled";
224                         #address-cells = <1>;
225                         #size-cells = <0>;
226                 };
227
228                 mmc2: mmc@1c11000 {
229                         compatible = "allwinner,sun8i-r40-emmc",
230                                      "allwinner,sun50i-a64-emmc";
231                         reg = <0x01c11000 0x1000>;
232                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
233                         clock-names = "ahb", "mmc";
234                         resets = <&ccu RST_BUS_MMC2>;
235                         reset-names = "ahb";
236                         pinctrl-0 = <&mmc2_pins>;
237                         pinctrl-names = "default";
238                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
239                         status = "disabled";
240                         #address-cells = <1>;
241                         #size-cells = <0>;
242                 };
243
244                 mmc3: mmc@1c12000 {
245                         compatible = "allwinner,sun8i-r40-mmc",
246                                      "allwinner,sun50i-a64-mmc";
247                         reg = <0x01c12000 0x1000>;
248                         clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
249                         clock-names = "ahb", "mmc";
250                         resets = <&ccu RST_BUS_MMC3>;
251                         reset-names = "ahb";
252                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
253                         status = "disabled";
254                         #address-cells = <1>;
255                         #size-cells = <0>;
256                 };
257
258                 usbphy: phy@1c13400 {
259                         compatible = "allwinner,sun8i-r40-usb-phy";
260                         reg = <0x01c13400 0x14>,
261                               <0x01c14800 0x4>,
262                               <0x01c19800 0x4>,
263                               <0x01c1c800 0x4>;
264                         reg-names = "phy_ctrl",
265                                     "pmu0",
266                                     "pmu1",
267                                     "pmu2";
268                         clocks = <&ccu CLK_USB_PHY0>,
269                                  <&ccu CLK_USB_PHY1>,
270                                  <&ccu CLK_USB_PHY2>;
271                         clock-names = "usb0_phy",
272                                       "usb1_phy",
273                                       "usb2_phy";
274                         resets = <&ccu RST_USB_PHY0>,
275                                  <&ccu RST_USB_PHY1>,
276                                  <&ccu RST_USB_PHY2>;
277                         reset-names = "usb0_reset",
278                                       "usb1_reset",
279                                       "usb2_reset";
280                         status = "disabled";
281                         #phy-cells = <1>;
282                 };
283
284                 crypto: crypto@1c15000 {
285                         compatible = "allwinner,sun8i-r40-crypto";
286                         reg = <0x01c15000 0x1000>;
287                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
288                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
289                         clock-names = "bus", "mod";
290                         resets = <&ccu RST_BUS_CE>;
291                 };
292
293                 ehci1: usb@1c19000 {
294                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
295                         reg = <0x01c19000 0x100>;
296                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
297                         clocks = <&ccu CLK_BUS_EHCI1>;
298                         resets = <&ccu RST_BUS_EHCI1>;
299                         phys = <&usbphy 1>;
300                         phy-names = "usb";
301                         status = "disabled";
302                 };
303
304                 ohci1: usb@1c19400 {
305                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
306                         reg = <0x01c19400 0x100>;
307                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
308                         clocks = <&ccu CLK_BUS_OHCI1>,
309                                  <&ccu CLK_USB_OHCI1>;
310                         resets = <&ccu RST_BUS_OHCI1>;
311                         phys = <&usbphy 1>;
312                         phy-names = "usb";
313                         status = "disabled";
314                 };
315
316                 ehci2: usb@1c1c000 {
317                         compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
318                         reg = <0x01c1c000 0x100>;
319                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
320                         clocks = <&ccu CLK_BUS_EHCI2>;
321                         resets = <&ccu RST_BUS_EHCI2>;
322                         phys = <&usbphy 2>;
323                         phy-names = "usb";
324                         status = "disabled";
325                 };
326
327                 ohci2: usb@1c1c400 {
328                         compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
329                         reg = <0x01c1c400 0x100>;
330                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
331                         clocks = <&ccu CLK_BUS_OHCI2>,
332                                  <&ccu CLK_USB_OHCI2>;
333                         resets = <&ccu RST_BUS_OHCI2>;
334                         phys = <&usbphy 2>;
335                         phy-names = "usb";
336                         status = "disabled";
337                 };
338
339                 ccu: clock@1c20000 {
340                         compatible = "allwinner,sun8i-r40-ccu";
341                         reg = <0x01c20000 0x400>;
342                         clocks = <&osc24M>, <&rtc 0>;
343                         clock-names = "hosc", "losc";
344                         #clock-cells = <1>;
345                         #reset-cells = <1>;
346                 };
347
348                 rtc: rtc@1c20400 {
349                         compatible = "allwinner,sun8i-r40-rtc";
350                         reg = <0x01c20400 0x400>;
351                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
352                         clock-output-names = "osc32k", "osc32k-out";
353                         clocks = <&osc32k>;
354                         #clock-cells = <1>;
355                 };
356
357                 pio: pinctrl@1c20800 {
358                         compatible = "allwinner,sun8i-r40-pinctrl";
359                         reg = <0x01c20800 0x400>;
360                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
361                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
362                         clock-names = "apb", "hosc", "losc";
363                         gpio-controller;
364                         interrupt-controller;
365                         #interrupt-cells = <3>;
366                         #gpio-cells = <3>;
367
368                         clk_out_a_pin: clk-out-a-pin {
369                                 pins = "PI12";
370                                 function = "clk_out_a";
371                         };
372
373                         /omit-if-no-ref/
374                         csi0_8bits_pins: csi0-8bits-pins {
375                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
376                                        "PE6", "PE7", "PE8", "PE9", "PE10",
377                                        "PE11";
378                                 function = "csi0";
379                         };
380
381                         /omit-if-no-ref/
382                         csi0_mclk_pin: csi0-mclk-pin {
383                                 pins = "PE1";
384                                 function = "csi0";
385                         };
386
387                         gmac_rgmii_pins: gmac-rgmii-pins {
388                                 pins = "PA0", "PA1", "PA2", "PA3",
389                                        "PA4", "PA5", "PA6", "PA7",
390                                        "PA8", "PA10", "PA11", "PA12",
391                                        "PA13", "PA15", "PA16";
392                                 function = "gmac";
393                                 /*
394                                  * data lines in RGMII mode use DDR mode
395                                  * and need a higher signal drive strength
396                                  */
397                                 drive-strength = <40>;
398                         };
399
400                         i2c0_pins: i2c0-pins {
401                                 pins = "PB0", "PB1";
402                                 function = "i2c0";
403                         };
404
405                         i2c1_pins: i2c1-pins {
406                                 pins = "PB18", "PB19";
407                                 function = "i2c1";
408                         };
409
410                         i2c2_pins: i2c2-pins {
411                                 pins = "PB20", "PB21";
412                                 function = "i2c2";
413                         };
414
415                         i2c3_pins: i2c3-pins {
416                                 pins = "PI0", "PI1";
417                                 function = "i2c3";
418                         };
419
420                         i2c4_pins: i2c4-pins {
421                                 pins = "PI2", "PI3";
422                                 function = "i2c4";
423                         };
424
425                         mmc0_pins: mmc0-pins {
426                                 pins = "PF0", "PF1", "PF2",
427                                        "PF3", "PF4", "PF5";
428                                 function = "mmc0";
429                                 drive-strength = <30>;
430                                 bias-pull-up;
431                         };
432
433                         mmc1_pg_pins: mmc1-pg-pins {
434                                 pins = "PG0", "PG1", "PG2",
435                                        "PG3", "PG4", "PG5";
436                                 function = "mmc1";
437                                 drive-strength = <30>;
438                                 bias-pull-up;
439                         };
440
441                         mmc2_pins: mmc2-pins {
442                                 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
443                                        "PC10", "PC11", "PC12", "PC13", "PC14",
444                                        "PC15", "PC24";
445                                 function = "mmc2";
446                                 drive-strength = <30>;
447                                 bias-pull-up;
448                         };
449
450                         /omit-if-no-ref/
451                         spi0_pc_pins: spi0-pc-pins {
452                                 pins = "PC0", "PC1", "PC2";
453                                 function = "spi0";
454                         };
455
456                         /omit-if-no-ref/
457                         spi0_cs0_pc_pin: spi0-cs0-pc-pin {
458                                 pins = "PC23";
459                                 function = "spi0";
460                         };
461
462                         /omit-if-no-ref/
463                         spi1_pi_pins: spi1-pi-pins {
464                                 pins = "PI17", "PI18", "PI19";
465                                 function = "spi1";
466                         };
467
468                         /omit-if-no-ref/
469                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
470                                 pins = "PI16";
471                                 function = "spi1";
472                         };
473
474                         /omit-if-no-ref/
475                         spi1_cs1_pi_pin: spi1-cs1-pi-pin {
476                                 pins = "PI15";
477                                 function = "spi1";
478                         };
479
480                         uart0_pb_pins: uart0-pb-pins {
481                                 pins = "PB22", "PB23";
482                                 function = "uart0";
483                         };
484
485                         uart3_pg_pins: uart3-pg-pins {
486                                 pins = "PG6", "PG7";
487                                 function = "uart3";
488                         };
489
490                         uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
491                                 pins = "PG8", "PG9";
492                                 function = "uart3";
493                         };
494                 };
495
496                 wdt: watchdog@1c20c90 {
497                         compatible = "allwinner,sun4i-a10-wdt";
498                         reg = <0x01c20c90 0x10>;
499                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
500                         clocks = <&osc24M>;
501                 };
502
503                 uart0: serial@1c28000 {
504                         compatible = "snps,dw-apb-uart";
505                         reg = <0x01c28000 0x400>;
506                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
507                         reg-shift = <2>;
508                         reg-io-width = <4>;
509                         clocks = <&ccu CLK_BUS_UART0>;
510                         resets = <&ccu RST_BUS_UART0>;
511                         status = "disabled";
512                 };
513
514                 uart1: serial@1c28400 {
515                         compatible = "snps,dw-apb-uart";
516                         reg = <0x01c28400 0x400>;
517                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
518                         reg-shift = <2>;
519                         reg-io-width = <4>;
520                         clocks = <&ccu CLK_BUS_UART1>;
521                         resets = <&ccu RST_BUS_UART1>;
522                         status = "disabled";
523                 };
524
525                 uart2: serial@1c28800 {
526                         compatible = "snps,dw-apb-uart";
527                         reg = <0x01c28800 0x400>;
528                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
529                         reg-shift = <2>;
530                         reg-io-width = <4>;
531                         clocks = <&ccu CLK_BUS_UART2>;
532                         resets = <&ccu RST_BUS_UART2>;
533                         status = "disabled";
534                 };
535
536                 uart3: serial@1c28c00 {
537                         compatible = "snps,dw-apb-uart";
538                         reg = <0x01c28c00 0x400>;
539                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
540                         reg-shift = <2>;
541                         reg-io-width = <4>;
542                         clocks = <&ccu CLK_BUS_UART3>;
543                         resets = <&ccu RST_BUS_UART3>;
544                         status = "disabled";
545                 };
546
547                 uart4: serial@1c29000 {
548                         compatible = "snps,dw-apb-uart";
549                         reg = <0x01c29000 0x400>;
550                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
551                         reg-shift = <2>;
552                         reg-io-width = <4>;
553                         clocks = <&ccu CLK_BUS_UART4>;
554                         resets = <&ccu RST_BUS_UART4>;
555                         status = "disabled";
556                 };
557
558                 uart5: serial@1c29400 {
559                         compatible = "snps,dw-apb-uart";
560                         reg = <0x01c29400 0x400>;
561                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
562                         reg-shift = <2>;
563                         reg-io-width = <4>;
564                         clocks = <&ccu CLK_BUS_UART5>;
565                         resets = <&ccu RST_BUS_UART5>;
566                         status = "disabled";
567                 };
568
569                 uart6: serial@1c29800 {
570                         compatible = "snps,dw-apb-uart";
571                         reg = <0x01c29800 0x400>;
572                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
573                         reg-shift = <2>;
574                         reg-io-width = <4>;
575                         clocks = <&ccu CLK_BUS_UART6>;
576                         resets = <&ccu RST_BUS_UART6>;
577                         status = "disabled";
578                 };
579
580                 uart7: serial@1c29c00 {
581                         compatible = "snps,dw-apb-uart";
582                         reg = <0x01c29c00 0x400>;
583                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
584                         reg-shift = <2>;
585                         reg-io-width = <4>;
586                         clocks = <&ccu CLK_BUS_UART7>;
587                         resets = <&ccu RST_BUS_UART7>;
588                         status = "disabled";
589                 };
590
591                 i2c0: i2c@1c2ac00 {
592                         compatible = "allwinner,sun6i-a31-i2c";
593                         reg = <0x01c2ac00 0x400>;
594                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
595                         clocks = <&ccu CLK_BUS_I2C0>;
596                         resets = <&ccu RST_BUS_I2C0>;
597                         pinctrl-0 = <&i2c0_pins>;
598                         pinctrl-names = "default";
599                         status = "disabled";
600                         #address-cells = <1>;
601                         #size-cells = <0>;
602                 };
603
604                 i2c1: i2c@1c2b000 {
605                         compatible = "allwinner,sun6i-a31-i2c";
606                         reg = <0x01c2b000 0x400>;
607                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
608                         clocks = <&ccu CLK_BUS_I2C1>;
609                         resets = <&ccu RST_BUS_I2C1>;
610                         pinctrl-0 = <&i2c1_pins>;
611                         pinctrl-names = "default";
612                         status = "disabled";
613                         #address-cells = <1>;
614                         #size-cells = <0>;
615                 };
616
617                 i2c2: i2c@1c2b400 {
618                         compatible = "allwinner,sun6i-a31-i2c";
619                         reg = <0x01c2b400 0x400>;
620                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
621                         clocks = <&ccu CLK_BUS_I2C2>;
622                         resets = <&ccu RST_BUS_I2C2>;
623                         pinctrl-0 = <&i2c2_pins>;
624                         pinctrl-names = "default";
625                         status = "disabled";
626                         #address-cells = <1>;
627                         #size-cells = <0>;
628                 };
629
630                 i2c3: i2c@1c2b800 {
631                         compatible = "allwinner,sun6i-a31-i2c";
632                         reg = <0x01c2b800 0x400>;
633                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
634                         clocks = <&ccu CLK_BUS_I2C3>;
635                         resets = <&ccu RST_BUS_I2C3>;
636                         pinctrl-0 = <&i2c3_pins>;
637                         pinctrl-names = "default";
638                         status = "disabled";
639                         #address-cells = <1>;
640                         #size-cells = <0>;
641                 };
642
643                 i2c4: i2c@1c2c000 {
644                         compatible = "allwinner,sun6i-a31-i2c";
645                         reg = <0x01c2c000 0x400>;
646                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
647                         clocks = <&ccu CLK_BUS_I2C4>;
648                         resets = <&ccu RST_BUS_I2C4>;
649                         pinctrl-0 = <&i2c4_pins>;
650                         pinctrl-names = "default";
651                         status = "disabled";
652                         #address-cells = <1>;
653                         #size-cells = <0>;
654                 };
655
656                 spi0: spi@1c05000 {
657                         compatible = "allwinner,sun8i-r40-spi",
658                                      "allwinner,sun8i-h3-spi";
659                         reg = <0x01c05000 0x1000>;
660                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
661                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
662                         clock-names = "ahb", "mod";
663                         resets = <&ccu RST_BUS_SPI0>;
664                         status = "disabled";
665                         #address-cells = <1>;
666                         #size-cells = <0>;
667                 };
668
669                 spi1: spi@1c06000 {
670                         compatible = "allwinner,sun8i-r40-spi",
671                                      "allwinner,sun8i-h3-spi";
672                         reg = <0x01c06000 0x1000>;
673                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
674                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
675                         clock-names = "ahb", "mod";
676                         resets = <&ccu RST_BUS_SPI1>;
677                         status = "disabled";
678                         #address-cells = <1>;
679                         #size-cells = <0>;
680                 };
681
682                 spi2: spi@1c07000 {
683                         compatible = "allwinner,sun8i-r40-spi",
684                                      "allwinner,sun8i-h3-spi";
685                         reg = <0x01c07000 0x1000>;
686                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
687                         clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
688                         clock-names = "ahb", "mod";
689                         resets = <&ccu RST_BUS_SPI2>;
690                         status = "disabled";
691                         #address-cells = <1>;
692                         #size-cells = <0>;
693                 };
694
695                 spi3: spi@1c0f000 {
696                         compatible = "allwinner,sun8i-r40-spi",
697                                      "allwinner,sun8i-h3-spi";
698                         reg = <0x01c0f000 0x1000>;
699                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
700                         clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
701                         clock-names = "ahb", "mod";
702                         resets = <&ccu RST_BUS_SPI3>;
703                         status = "disabled";
704                         #address-cells = <1>;
705                         #size-cells = <0>;
706                 };
707
708                 ahci: sata@1c18000 {
709                         compatible = "allwinner,sun8i-r40-ahci";
710                         reg = <0x01c18000 0x1000>;
711                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
712                         clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
713                         resets = <&ccu RST_BUS_SATA>;
714                         reset-names = "ahci";
715                         status = "disabled";
716
717                 };
718
719                 gmac: ethernet@1c50000 {
720                         compatible = "allwinner,sun8i-r40-gmac";
721                         syscon = <&ccu>;
722                         reg = <0x01c50000 0x10000>;
723                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
724                         interrupt-names = "macirq";
725                         resets = <&ccu RST_BUS_GMAC>;
726                         reset-names = "stmmaceth";
727                         clocks = <&ccu CLK_BUS_GMAC>;
728                         clock-names = "stmmaceth";
729                         status = "disabled";
730
731                         gmac_mdio: mdio {
732                                 compatible = "snps,dwmac-mdio";
733                                 #address-cells = <1>;
734                                 #size-cells = <0>;
735                         };
736                 };
737
738                 mbus: dram-controller@1c62000 {
739                         compatible = "allwinner,sun8i-r40-mbus";
740                         reg = <0x01c62000 0x1000>;
741                         clocks = <&ccu 155>;
742                         dma-ranges = <0x00000000 0x40000000 0x80000000>;
743                         #interconnect-cells = <1>;
744                 };
745
746                 tcon_top: tcon-top@1c70000 {
747                         compatible = "allwinner,sun8i-r40-tcon-top";
748                         reg = <0x01c70000 0x1000>;
749                         clocks = <&ccu CLK_BUS_TCON_TOP>,
750                                  <&ccu CLK_TCON_TV0>,
751                                  <&ccu CLK_TVE0>,
752                                  <&ccu CLK_TCON_TV1>,
753                                  <&ccu CLK_TVE1>,
754                                  <&ccu CLK_DSI_DPHY>;
755                         clock-names = "bus",
756                                       "tcon-tv0",
757                                       "tve0",
758                                       "tcon-tv1",
759                                       "tve1",
760                                       "dsi";
761                         clock-output-names = "tcon-top-tv0",
762                                              "tcon-top-tv1",
763                                              "tcon-top-dsi";
764                         resets = <&ccu RST_BUS_TCON_TOP>;
765                         #clock-cells = <1>;
766
767                         ports {
768                                 #address-cells = <1>;
769                                 #size-cells = <0>;
770
771                                 tcon_top_mixer0_in: port@0 {
772                                         reg = <0>;
773
774                                         tcon_top_mixer0_in_mixer0: endpoint {
775                                                 remote-endpoint = <&mixer0_out_tcon_top>;
776                                         };
777                                 };
778
779                                 tcon_top_mixer0_out: port@1 {
780                                         #address-cells = <1>;
781                                         #size-cells = <0>;
782                                         reg = <1>;
783
784                                         tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
785                                                 reg = <0>;
786                                         };
787
788                                         tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
789                                                 reg = <1>;
790                                         };
791
792                                         tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
793                                                 reg = <2>;
794                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
795                                         };
796
797                                         tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
798                                                 reg = <3>;
799                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
800                                         };
801                                 };
802
803                                 tcon_top_mixer1_in: port@2 {
804                                         #address-cells = <1>;
805                                         #size-cells = <0>;
806                                         reg = <2>;
807
808                                         tcon_top_mixer1_in_mixer1: endpoint@1 {
809                                                 reg = <1>;
810                                                 remote-endpoint = <&mixer1_out_tcon_top>;
811                                         };
812                                 };
813
814                                 tcon_top_mixer1_out: port@3 {
815                                         #address-cells = <1>;
816                                         #size-cells = <0>;
817                                         reg = <3>;
818
819                                         tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
820                                                 reg = <0>;
821                                         };
822
823                                         tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
824                                                 reg = <1>;
825                                         };
826
827                                         tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
828                                                 reg = <2>;
829                                                 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
830                                         };
831
832                                         tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
833                                                 reg = <3>;
834                                                 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
835                                         };
836                                 };
837
838                                 tcon_top_hdmi_in: port@4 {
839                                         #address-cells = <1>;
840                                         #size-cells = <0>;
841                                         reg = <4>;
842
843                                         tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
844                                                 reg = <0>;
845                                                 remote-endpoint = <&tcon_tv0_out_tcon_top>;
846                                         };
847
848                                         tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
849                                                 reg = <1>;
850                                                 remote-endpoint = <&tcon_tv1_out_tcon_top>;
851                                         };
852                                 };
853
854                                 tcon_top_hdmi_out: port@5 {
855                                         reg = <5>;
856
857                                         tcon_top_hdmi_out_hdmi: endpoint {
858                                                 remote-endpoint = <&hdmi_in_tcon_top>;
859                                         };
860                                 };
861                         };
862                 };
863
864                 tcon_tv0: lcd-controller@1c73000 {
865                         compatible = "allwinner,sun8i-r40-tcon-tv";
866                         reg = <0x01c73000 0x1000>;
867                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
868                         clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
869                         clock-names = "ahb", "tcon-ch1";
870                         resets = <&ccu RST_BUS_TCON_TV0>;
871                         reset-names = "lcd";
872                         status = "disabled";
873
874                         ports {
875                                 #address-cells = <1>;
876                                 #size-cells = <0>;
877
878                                 tcon_tv0_in: port@0 {
879                                         #address-cells = <1>;
880                                         #size-cells = <0>;
881                                         reg = <0>;
882
883                                         tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
884                                                 reg = <0>;
885                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
886                                         };
887
888                                         tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
889                                                 reg = <1>;
890                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
891                                         };
892                                 };
893
894                                 tcon_tv0_out: port@1 {
895                                         #address-cells = <1>;
896                                         #size-cells = <0>;
897                                         reg = <1>;
898
899                                         tcon_tv0_out_tcon_top: endpoint@1 {
900                                                 reg = <1>;
901                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
902                                         };
903                                 };
904                         };
905                 };
906
907                 tcon_tv1: lcd-controller@1c74000 {
908                         compatible = "allwinner,sun8i-r40-tcon-tv";
909                         reg = <0x01c74000 0x1000>;
910                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
911                         clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
912                         clock-names = "ahb", "tcon-ch1";
913                         resets = <&ccu RST_BUS_TCON_TV1>;
914                         reset-names = "lcd";
915                         status = "disabled";
916
917                         ports {
918                                 #address-cells = <1>;
919                                 #size-cells = <0>;
920
921                                 tcon_tv1_in: port@0 {
922                                         #address-cells = <1>;
923                                         #size-cells = <0>;
924                                         reg = <0>;
925
926                                         tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
927                                                 reg = <0>;
928                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
929                                         };
930
931                                         tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
932                                                 reg = <1>;
933                                                 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
934                                         };
935                                 };
936
937                                 tcon_tv1_out: port@1 {
938                                         #address-cells = <1>;
939                                         #size-cells = <0>;
940                                         reg = <1>;
941
942                                         tcon_tv1_out_tcon_top: endpoint@1 {
943                                                 reg = <1>;
944                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
945                                         };
946                                 };
947                         };
948                 };
949
950                 gic: interrupt-controller@1c81000 {
951                         compatible = "arm,gic-400";
952                         reg = <0x01c81000 0x1000>,
953                               <0x01c82000 0x2000>,
954                               <0x01c84000 0x2000>,
955                               <0x01c86000 0x2000>;
956                         interrupt-controller;
957                         #interrupt-cells = <3>;
958                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
959                 };
960
961                 hdmi: hdmi@1ee0000 {
962                         compatible = "allwinner,sun8i-r40-dw-hdmi",
963                                      "allwinner,sun8i-a83t-dw-hdmi";
964                         reg = <0x01ee0000 0x10000>;
965                         reg-io-width = <1>;
966                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
967                         clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
968                                  <&ccu CLK_HDMI>;
969                         clock-names = "iahb", "isfr", "tmds";
970                         resets = <&ccu RST_BUS_HDMI1>;
971                         reset-names = "ctrl";
972                         phys = <&hdmi_phy>;
973                         phy-names = "phy";
974                         status = "disabled";
975
976                         ports {
977                                 #address-cells = <1>;
978                                 #size-cells = <0>;
979
980                                 hdmi_in: port@0 {
981                                         reg = <0>;
982
983                                         hdmi_in_tcon_top: endpoint {
984                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
985                                         };
986                                 };
987
988                                 hdmi_out: port@1 {
989                                         reg = <1>;
990                                 };
991                         };
992                 };
993
994                 hdmi_phy: hdmi-phy@1ef0000 {
995                         compatible = "allwinner,sun8i-r40-hdmi-phy";
996                         reg = <0x01ef0000 0x10000>;
997                         clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
998                                  <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
999                         clock-names = "bus", "mod", "pll-0", "pll-1";
1000                         resets = <&ccu RST_BUS_HDMI0>;
1001                         reset-names = "phy";
1002                         #phy-cells = <0>;
1003                 };
1004         };
1005
1006         pmu {
1007                 compatible = "arm,cortex-a7-pmu";
1008                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1009                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1010                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1011                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1012                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1013         };
1014
1015         timer {
1016                 compatible = "arm,armv7-timer";
1017                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1018                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1019                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1020                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1021         };
1022 };