2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
50 #include <dt-bindings/thermal/thermal.h>
55 interrupt-parent = <&gic>;
64 compatible = "fixed-clock";
65 clock-frequency = <24000000>;
66 clock-accuracy = <50000>;
67 clock-output-names = "osc24M";
72 compatible = "fixed-clock";
73 clock-frequency = <32768>;
74 clock-accuracy = <20000>;
75 clock-output-names = "ext-osc32k";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
96 compatible = "arm,cortex-a7";
102 compatible = "arm,cortex-a7";
109 compatible = "allwinner,sun8i-r40-display-engine";
110 allwinner,pipelines = <&mixer0>, <&mixer1>;
115 cpu_thermal: cpu0-thermal {
117 polling-delay-passive = <0>;
119 thermal-sensors = <&ths 0>;
122 gpu_thermal: gpu-thermal {
124 polling-delay-passive = <0>;
126 thermal-sensors = <&ths 1>;
131 compatible = "simple-bus";
132 #address-cells = <1>;
136 display_clocks: clock@1000000 {
137 compatible = "allwinner,sun8i-r40-de2-clk",
138 "allwinner,sun8i-h3-de2-clk";
139 reg = <0x01000000 0x10000>;
140 clocks = <&ccu CLK_BUS_DE>,
144 resets = <&ccu RST_BUS_DE>;
149 mixer0: mixer@1100000 {
150 compatible = "allwinner,sun8i-r40-de2-mixer-0";
151 reg = <0x01100000 0x100000>;
152 clocks = <&display_clocks CLK_BUS_MIXER0>,
153 <&display_clocks CLK_MIXER0>;
156 resets = <&display_clocks RST_MIXER0>;
159 #address-cells = <1>;
164 mixer0_out_tcon_top: endpoint {
165 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
171 mixer1: mixer@1200000 {
172 compatible = "allwinner,sun8i-r40-de2-mixer-1";
173 reg = <0x01200000 0x100000>;
174 clocks = <&display_clocks CLK_BUS_MIXER1>,
175 <&display_clocks CLK_MIXER1>;
178 resets = <&display_clocks RST_WB>;
181 #address-cells = <1>;
186 mixer1_out_tcon_top: endpoint {
187 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
193 deinterlace: deinterlace@1400000 {
194 compatible = "allwinner,sun8i-r40-deinterlace",
195 "allwinner,sun8i-h3-deinterlace";
196 reg = <0x01400000 0x20000>;
197 clocks = <&ccu CLK_BUS_DEINTERLACE>,
198 <&ccu CLK_DEINTERLACE>,
200 * NOTE: Contrary to what datasheet claims,
201 * DRAM deinterlace gate doesn't exist and
202 * it's shared with CSI1.
204 <&ccu CLK_DRAM_CSI1>;
205 clock-names = "bus", "mod", "ram";
206 resets = <&ccu RST_BUS_DEINTERLACE>;
207 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
208 interconnects = <&mbus 9>;
209 interconnect-names = "dma-mem";
212 syscon: system-control@1c00000 {
213 compatible = "allwinner,sun8i-r40-system-control",
214 "allwinner,sun4i-a10-system-control";
215 reg = <0x01c00000 0x30>;
216 #address-cells = <1>;
220 sram_c: sram@1d00000 {
221 compatible = "mmio-sram";
222 reg = <0x01d00000 0xd0000>;
223 #address-cells = <1>;
225 ranges = <0 0x01d00000 0xd0000>;
227 ve_sram: sram-section@0 {
228 compatible = "allwinner,sun8i-r40-sram-c1",
229 "allwinner,sun4i-a10-sram-c1";
230 reg = <0x000000 0x80000>;
235 nmi_intc: interrupt-controller@1c00030 {
236 compatible = "allwinner,sun7i-a20-sc-nmi";
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 reg = <0x01c00030 0x0c>;
240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
243 dma: dma-controller@1c02000 {
244 compatible = "allwinner,sun8i-r40-dma",
245 "allwinner,sun50i-a64-dma";
246 reg = <0x01c02000 0x1000>;
247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&ccu CLK_BUS_DMA>;
251 resets = <&ccu RST_BUS_DMA>;
256 compatible = "allwinner,sun8i-r40-spi",
257 "allwinner,sun8i-h3-spi";
258 reg = <0x01c05000 0x1000>;
259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
261 clock-names = "ahb", "mod";
262 resets = <&ccu RST_BUS_SPI0>;
264 #address-cells = <1>;
269 compatible = "allwinner,sun8i-r40-spi",
270 "allwinner,sun8i-h3-spi";
271 reg = <0x01c06000 0x1000>;
272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
274 clock-names = "ahb", "mod";
275 resets = <&ccu RST_BUS_SPI1>;
277 #address-cells = <1>;
282 compatible = "allwinner,sun8i-r40-csi0",
283 "allwinner,sun7i-a20-csi0";
284 reg = <0x01c09000 0x1000>;
285 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
287 <&ccu CLK_DRAM_CSI0>;
288 clock-names = "bus", "isp", "ram";
289 resets = <&ccu RST_BUS_CSI0>;
290 interconnects = <&mbus 5>;
291 interconnect-names = "dma-mem";
295 video-codec@1c0e000 {
296 compatible = "allwinner,sun8i-r40-video-engine";
297 reg = <0x01c0e000 0x1000>;
298 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
300 clock-names = "ahb", "mod", "ram";
301 resets = <&ccu RST_BUS_VE>;
302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
303 allwinner,sram = <&ve_sram 1>;
307 compatible = "allwinner,sun8i-r40-mmc",
308 "allwinner,sun50i-a64-mmc";
309 reg = <0x01c0f000 0x1000>;
310 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
311 clock-names = "ahb", "mmc";
312 resets = <&ccu RST_BUS_MMC0>;
314 pinctrl-0 = <&mmc0_pins>;
315 pinctrl-names = "default";
316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
323 compatible = "allwinner,sun8i-r40-mmc",
324 "allwinner,sun50i-a64-mmc";
325 reg = <0x01c10000 0x1000>;
326 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
327 clock-names = "ahb", "mmc";
328 resets = <&ccu RST_BUS_MMC1>;
330 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
337 compatible = "allwinner,sun8i-r40-emmc",
338 "allwinner,sun50i-a64-emmc";
339 reg = <0x01c11000 0x1000>;
340 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
341 clock-names = "ahb", "mmc";
342 resets = <&ccu RST_BUS_MMC2>;
344 pinctrl-0 = <&mmc2_pins>;
345 pinctrl-names = "default";
346 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
353 compatible = "allwinner,sun8i-r40-mmc",
354 "allwinner,sun50i-a64-mmc";
355 reg = <0x01c12000 0x1000>;
356 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
357 clock-names = "ahb", "mmc";
358 resets = <&ccu RST_BUS_MMC3>;
360 pinctrl-0 = <&mmc3_pins>;
361 pinctrl-names = "default";
362 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
368 usbphy: phy@1c13400 {
369 compatible = "allwinner,sun8i-r40-usb-phy";
370 reg = <0x01c13400 0x14>,
374 reg-names = "phy_ctrl",
378 clocks = <&ccu CLK_USB_PHY0>,
381 clock-names = "usb0_phy",
384 resets = <&ccu RST_USB_PHY0>,
387 reset-names = "usb0_reset",
394 crypto: crypto@1c15000 {
395 compatible = "allwinner,sun8i-r40-crypto";
396 reg = <0x01c15000 0x1000>;
397 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
399 clock-names = "bus", "mod";
400 resets = <&ccu RST_BUS_CE>;
404 compatible = "allwinner,sun8i-r40-spi",
405 "allwinner,sun8i-h3-spi";
406 reg = <0x01c17000 0x1000>;
407 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
409 clock-names = "ahb", "mod";
410 resets = <&ccu RST_BUS_SPI2>;
412 #address-cells = <1>;
417 compatible = "allwinner,sun8i-r40-ahci";
418 reg = <0x01c18000 0x1000>;
419 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
421 resets = <&ccu RST_BUS_SATA>;
422 reset-names = "ahci";
427 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
428 reg = <0x01c19000 0x100>;
429 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&ccu CLK_BUS_EHCI1>;
431 resets = <&ccu RST_BUS_EHCI1>;
438 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
439 reg = <0x01c19400 0x100>;
440 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&ccu CLK_BUS_OHCI1>,
442 <&ccu CLK_USB_OHCI1>;
443 resets = <&ccu RST_BUS_OHCI1>;
450 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
451 reg = <0x01c1c000 0x100>;
452 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&ccu CLK_BUS_EHCI2>;
454 resets = <&ccu RST_BUS_EHCI2>;
461 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
462 reg = <0x01c1c400 0x100>;
463 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&ccu CLK_BUS_OHCI2>,
465 <&ccu CLK_USB_OHCI2>;
466 resets = <&ccu RST_BUS_OHCI2>;
473 compatible = "allwinner,sun8i-r40-spi",
474 "allwinner,sun8i-h3-spi";
475 reg = <0x01c1f000 0x1000>;
476 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
478 clock-names = "ahb", "mod";
479 resets = <&ccu RST_BUS_SPI3>;
481 #address-cells = <1>;
486 compatible = "allwinner,sun8i-r40-ccu";
487 reg = <0x01c20000 0x400>;
488 clocks = <&osc24M>, <&rtc 0>;
489 clock-names = "hosc", "losc";
495 compatible = "allwinner,sun8i-r40-rtc";
496 reg = <0x01c20400 0x400>;
497 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
498 clock-output-names = "osc32k", "osc32k-out";
503 pio: pinctrl@1c20800 {
504 compatible = "allwinner,sun8i-r40-pinctrl";
505 reg = <0x01c20800 0x400>;
506 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
508 clock-names = "apb", "hosc", "losc";
510 interrupt-controller;
511 #interrupt-cells = <3>;
514 clk_out_a_pin: clk-out-a-pin {
516 function = "clk_out_a";
520 csi0_8bits_pins: csi0-8bits-pins {
521 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
522 "PE6", "PE7", "PE8", "PE9", "PE10",
528 csi0_mclk_pin: csi0-mclk-pin {
533 gmac_rgmii_pins: gmac-rgmii-pins {
534 pins = "PA0", "PA1", "PA2", "PA3",
535 "PA4", "PA5", "PA6", "PA7",
536 "PA8", "PA10", "PA11", "PA12",
537 "PA13", "PA15", "PA16";
540 * data lines in RGMII mode use DDR mode
541 * and need a higher signal drive strength
543 drive-strength = <40>;
546 i2c0_pins: i2c0-pins {
551 i2c1_pins: i2c1-pins {
552 pins = "PB18", "PB19";
556 i2c2_pins: i2c2-pins {
557 pins = "PB20", "PB21";
561 i2c3_pins: i2c3-pins {
566 i2c4_pins: i2c4-pins {
581 mmc0_pins: mmc0-pins {
582 pins = "PF0", "PF1", "PF2",
585 drive-strength = <30>;
589 mmc1_pg_pins: mmc1-pg-pins {
590 pins = "PG0", "PG1", "PG2",
593 drive-strength = <30>;
597 mmc2_pins: mmc2-pins {
598 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
599 "PC10", "PC11", "PC12", "PC13", "PC14",
602 drive-strength = <30>;
607 mmc3_pins: mmc3-pins {
608 pins = "PI4", "PI5", "PI6",
611 drive-strength = <30>;
616 spi0_pc_pins: spi0-pc-pins {
617 pins = "PC0", "PC1", "PC2";
622 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
628 spi1_pi_pins: spi1-pi-pins {
629 pins = "PI17", "PI18", "PI19";
634 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
640 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
646 uart0_pb_pins: uart0-pb-pins {
647 pins = "PB22", "PB23";
652 uart2_pi_pins: uart2-pi-pins {
653 pins = "PI18", "PI19";
658 uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
659 pins = "PI16", "PI17";
664 uart3_pg_pins: uart3-pg-pins {
670 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
676 uart4_pg_pins: uart4-pg-pins {
677 pins = "PG10", "PG11";
682 uart5_ph_pins: uart5-ph-pins {
688 uart7_pi_pins: uart7-pi-pins {
689 pins = "PI20", "PI21";
695 compatible = "allwinner,sun4i-a10-timer";
696 reg = <0x01c20c00 0x90>;
697 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
706 wdt: watchdog@1c20c90 {
707 compatible = "allwinner,sun4i-a10-wdt";
708 reg = <0x01c20c90 0x10>;
709 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
714 compatible = "allwinner,sun8i-r40-ir",
715 "allwinner,sun6i-a31-ir";
716 reg = <0x01c21800 0x400>;
717 pinctrl-0 = <&ir0_pins>;
718 pinctrl-names = "default";
719 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
720 clock-names = "apb", "ir";
721 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
722 resets = <&ccu RST_BUS_IR0>;
727 compatible = "allwinner,sun8i-r40-ir",
728 "allwinner,sun6i-a31-ir";
729 reg = <0x01c21c00 0x400>;
730 pinctrl-0 = <&ir1_pins>;
731 pinctrl-names = "default";
732 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
733 clock-names = "apb", "ir";
734 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
735 resets = <&ccu RST_BUS_IR1>;
739 ths: thermal-sensor@1c24c00 {
740 compatible = "allwinner,sun8i-r40-ths";
741 reg = <0x01c24c00 0x100>;
742 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
743 clock-names = "bus", "mod";
744 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
745 resets = <&ccu RST_BUS_THS>;
746 /* TODO: add nvmem-cells for calibration */
747 #thermal-sensor-cells = <1>;
750 uart0: serial@1c28000 {
751 compatible = "snps,dw-apb-uart";
752 reg = <0x01c28000 0x400>;
753 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&ccu CLK_BUS_UART0>;
757 resets = <&ccu RST_BUS_UART0>;
761 uart1: serial@1c28400 {
762 compatible = "snps,dw-apb-uart";
763 reg = <0x01c28400 0x400>;
764 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&ccu CLK_BUS_UART1>;
768 resets = <&ccu RST_BUS_UART1>;
772 uart2: serial@1c28800 {
773 compatible = "snps,dw-apb-uart";
774 reg = <0x01c28800 0x400>;
775 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&ccu CLK_BUS_UART2>;
779 resets = <&ccu RST_BUS_UART2>;
783 uart3: serial@1c28c00 {
784 compatible = "snps,dw-apb-uart";
785 reg = <0x01c28c00 0x400>;
786 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&ccu CLK_BUS_UART3>;
790 resets = <&ccu RST_BUS_UART3>;
794 uart4: serial@1c29000 {
795 compatible = "snps,dw-apb-uart";
796 reg = <0x01c29000 0x400>;
797 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&ccu CLK_BUS_UART4>;
801 resets = <&ccu RST_BUS_UART4>;
805 uart5: serial@1c29400 {
806 compatible = "snps,dw-apb-uart";
807 reg = <0x01c29400 0x400>;
808 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&ccu CLK_BUS_UART5>;
812 resets = <&ccu RST_BUS_UART5>;
816 uart6: serial@1c29800 {
817 compatible = "snps,dw-apb-uart";
818 reg = <0x01c29800 0x400>;
819 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&ccu CLK_BUS_UART6>;
823 resets = <&ccu RST_BUS_UART6>;
827 uart7: serial@1c29c00 {
828 compatible = "snps,dw-apb-uart";
829 reg = <0x01c29c00 0x400>;
830 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&ccu CLK_BUS_UART7>;
834 resets = <&ccu RST_BUS_UART7>;
839 compatible = "allwinner,sun6i-a31-i2c";
840 reg = <0x01c2ac00 0x400>;
841 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&ccu CLK_BUS_I2C0>;
843 resets = <&ccu RST_BUS_I2C0>;
844 pinctrl-0 = <&i2c0_pins>;
845 pinctrl-names = "default";
847 #address-cells = <1>;
852 compatible = "allwinner,sun6i-a31-i2c";
853 reg = <0x01c2b000 0x400>;
854 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&ccu CLK_BUS_I2C1>;
856 resets = <&ccu RST_BUS_I2C1>;
857 pinctrl-0 = <&i2c1_pins>;
858 pinctrl-names = "default";
860 #address-cells = <1>;
865 compatible = "allwinner,sun6i-a31-i2c";
866 reg = <0x01c2b400 0x400>;
867 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&ccu CLK_BUS_I2C2>;
869 resets = <&ccu RST_BUS_I2C2>;
870 pinctrl-0 = <&i2c2_pins>;
871 pinctrl-names = "default";
873 #address-cells = <1>;
878 compatible = "allwinner,sun6i-a31-i2c";
879 reg = <0x01c2b800 0x400>;
880 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&ccu CLK_BUS_I2C3>;
882 resets = <&ccu RST_BUS_I2C3>;
883 pinctrl-0 = <&i2c3_pins>;
884 pinctrl-names = "default";
886 #address-cells = <1>;
891 compatible = "allwinner,sun6i-a31-i2c";
892 reg = <0x01c2c000 0x400>;
893 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&ccu CLK_BUS_I2C4>;
895 resets = <&ccu RST_BUS_I2C4>;
896 pinctrl-0 = <&i2c4_pins>;
897 pinctrl-names = "default";
899 #address-cells = <1>;
904 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
905 reg = <0x01c40000 0x10000>;
906 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
913 interrupt-names = "gp",
920 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
921 clock-names = "bus", "core";
922 resets = <&ccu RST_BUS_GPU>;
925 gmac: ethernet@1c50000 {
926 compatible = "allwinner,sun8i-r40-gmac";
928 reg = <0x01c50000 0x10000>;
929 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
930 interrupt-names = "macirq";
931 resets = <&ccu RST_BUS_GMAC>;
932 reset-names = "stmmaceth";
933 clocks = <&ccu CLK_BUS_GMAC>;
934 clock-names = "stmmaceth";
938 compatible = "snps,dwmac-mdio";
939 #address-cells = <1>;
944 mbus: dram-controller@1c62000 {
945 compatible = "allwinner,sun8i-r40-mbus";
946 reg = <0x01c62000 0x1000>;
948 #address-cells = <1>;
950 dma-ranges = <0x00000000 0x40000000 0x80000000>;
951 #interconnect-cells = <1>;
954 tcon_top: tcon-top@1c70000 {
955 compatible = "allwinner,sun8i-r40-tcon-top";
956 reg = <0x01c70000 0x1000>;
957 clocks = <&ccu CLK_BUS_TCON_TOP>,
969 clock-output-names = "tcon-top-tv0",
972 resets = <&ccu RST_BUS_TCON_TOP>;
976 #address-cells = <1>;
979 tcon_top_mixer0_in: port@0 {
982 tcon_top_mixer0_in_mixer0: endpoint {
983 remote-endpoint = <&mixer0_out_tcon_top>;
987 tcon_top_mixer0_out: port@1 {
988 #address-cells = <1>;
992 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
996 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
1000 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
1002 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
1005 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
1007 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
1011 tcon_top_mixer1_in: port@2 {
1012 #address-cells = <1>;
1016 tcon_top_mixer1_in_mixer1: endpoint@1 {
1018 remote-endpoint = <&mixer1_out_tcon_top>;
1022 tcon_top_mixer1_out: port@3 {
1023 #address-cells = <1>;
1027 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1031 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
1035 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
1037 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
1040 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
1042 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
1046 tcon_top_hdmi_in: port@4 {
1047 #address-cells = <1>;
1051 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
1053 remote-endpoint = <&tcon_tv0_out_tcon_top>;
1056 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
1058 remote-endpoint = <&tcon_tv1_out_tcon_top>;
1062 tcon_top_hdmi_out: port@5 {
1065 tcon_top_hdmi_out_hdmi: endpoint {
1066 remote-endpoint = <&hdmi_in_tcon_top>;
1072 tcon_tv0: lcd-controller@1c73000 {
1073 compatible = "allwinner,sun8i-r40-tcon-tv";
1074 reg = <0x01c73000 0x1000>;
1075 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
1077 clock-names = "ahb", "tcon-ch1";
1078 resets = <&ccu RST_BUS_TCON_TV0>;
1079 reset-names = "lcd";
1080 status = "disabled";
1083 #address-cells = <1>;
1086 tcon_tv0_in: port@0 {
1087 #address-cells = <1>;
1091 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1093 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1096 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
1098 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1102 tcon_tv0_out: port@1 {
1103 #address-cells = <1>;
1107 tcon_tv0_out_tcon_top: endpoint@1 {
1109 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1115 tcon_tv1: lcd-controller@1c74000 {
1116 compatible = "allwinner,sun8i-r40-tcon-tv";
1117 reg = <0x01c74000 0x1000>;
1118 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
1120 clock-names = "ahb", "tcon-ch1";
1121 resets = <&ccu RST_BUS_TCON_TV1>;
1122 reset-names = "lcd";
1123 status = "disabled";
1126 #address-cells = <1>;
1129 tcon_tv1_in: port@0 {
1130 #address-cells = <1>;
1134 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1136 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
1139 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
1141 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
1145 tcon_tv1_out: port@1 {
1146 #address-cells = <1>;
1150 tcon_tv1_out_tcon_top: endpoint@1 {
1152 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
1158 gic: interrupt-controller@1c81000 {
1159 compatible = "arm,gic-400";
1160 reg = <0x01c81000 0x1000>,
1161 <0x01c82000 0x2000>,
1162 <0x01c84000 0x2000>,
1163 <0x01c86000 0x2000>;
1164 interrupt-controller;
1165 #interrupt-cells = <3>;
1166 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1169 hdmi: hdmi@1ee0000 {
1170 compatible = "allwinner,sun8i-r40-dw-hdmi",
1171 "allwinner,sun8i-a83t-dw-hdmi";
1172 reg = <0x01ee0000 0x10000>;
1174 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1175 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
1177 clock-names = "iahb", "isfr", "tmds";
1178 resets = <&ccu RST_BUS_HDMI1>;
1179 reset-names = "ctrl";
1182 status = "disabled";
1185 #address-cells = <1>;
1191 hdmi_in_tcon_top: endpoint {
1192 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1202 hdmi_phy: hdmi-phy@1ef0000 {
1203 compatible = "allwinner,sun8i-r40-hdmi-phy";
1204 reg = <0x01ef0000 0x10000>;
1205 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1206 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1207 clock-names = "bus", "mod", "pll-0", "pll-1";
1208 resets = <&ccu RST_BUS_HDMI0>;
1209 reset-names = "phy";
1215 compatible = "arm,cortex-a7-pmu";
1216 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1220 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1224 compatible = "arm,armv7-timer";
1225 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1226 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1227 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1228 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;