2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp_table0 {
48 compatible = "operating-points-v2";
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
58 opp-hz = /bits/ 64 <816000000>;
59 opp-microvolt = <1100000 1100000 1300000>;
60 clock-latency-ns = <244144>; /* 8 32k periods */
64 opp-hz = /bits/ 64 <1008000000>;
65 opp-microvolt = <1200000 1200000 1300000>;
66 clock-latency-ns = <244144>; /* 8 32k periods */
75 compatible = "arm,cortex-a7";
78 clocks = <&ccu CLK_CPUX>;
80 operating-points-v2 = <&cpu0_opp_table>;
85 compatible = "arm,cortex-a7";
88 clocks = <&ccu CLK_CPUX>;
90 operating-points-v2 = <&cpu0_opp_table>;
95 compatible = "arm,cortex-a7";
98 clocks = <&ccu CLK_CPUX>;
100 operating-points-v2 = <&cpu0_opp_table>;
101 #cooling-cells = <2>;
105 compatible = "arm,cortex-a7";
108 clocks = <&ccu CLK_CPUX>;
110 operating-points-v2 = <&cpu0_opp_table>;
111 #cooling-cells = <2>;
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
125 compatible = "arm,armv7-timer";
126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
133 deinterlace: deinterlace@1400000 {
134 compatible = "allwinner,sun8i-h3-deinterlace";
135 reg = <0x01400000 0x20000>;
136 clocks = <&ccu CLK_BUS_DEINTERLACE>,
137 <&ccu CLK_DEINTERLACE>,
138 <&ccu CLK_DRAM_DEINTERLACE>;
139 clock-names = "bus", "mod", "ram";
140 resets = <&ccu RST_BUS_DEINTERLACE>;
141 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
142 interconnects = <&mbus 9>;
143 interconnect-names = "dma-mem";
146 syscon: system-control@1c00000 {
147 compatible = "allwinner,sun8i-h3-system-control";
148 reg = <0x01c00000 0x1000>;
149 #address-cells = <1>;
153 sram_c: sram@1d00000 {
154 compatible = "mmio-sram";
155 reg = <0x01d00000 0x80000>;
156 #address-cells = <1>;
158 ranges = <0 0x01d00000 0x80000>;
160 ve_sram: sram-section@0 {
161 compatible = "allwinner,sun8i-h3-sram-c1",
162 "allwinner,sun4i-a10-sram-c1";
163 reg = <0x000000 0x80000>;
168 video-codec@1c0e000 {
169 compatible = "allwinner,sun8i-h3-video-engine";
170 reg = <0x01c0e000 0x1000>;
171 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
173 clock-names = "ahb", "mod", "ram";
174 resets = <&ccu RST_BUS_VE>;
175 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
176 allwinner,sram = <&ve_sram 1>;
179 crypto: crypto@1c15000 {
180 compatible = "allwinner,sun8i-h3-crypto";
181 reg = <0x01c15000 0x1000>;
182 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
184 clock-names = "bus", "mod";
185 resets = <&ccu RST_BUS_CE>;
189 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
190 reg = <0x01c40000 0x10000>;
191 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-names = "gp",
205 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
206 clock-names = "bus", "core";
207 resets = <&ccu RST_BUS_GPU>;
209 assigned-clocks = <&ccu CLK_GPU>;
210 assigned-clock-rates = <384000000>;
213 ths: thermal-sensor@1c25000 {
214 compatible = "allwinner,sun8i-h3-ths";
215 reg = <0x01c25000 0x400>;
216 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
217 resets = <&ccu RST_BUS_THS>;
218 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
219 clock-names = "bus", "mod";
220 nvmem-cells = <&ths_calibration>;
221 nvmem-cell-names = "calibration";
222 #thermal-sensor-cells = <0>;
227 cpu_thermal: cpu-thermal {
228 polling-delay-passive = <0>;
230 thermal-sensors = <&ths 0>;
233 cpu_hot_trip: cpu-hot {
234 temperature = <80000>;
239 cpu_very_hot_trip: cpu-very-hot {
240 temperature = <100000>;
248 trip = <&cpu_hot_trip>;
249 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
260 compatible = "allwinner,sun8i-h3-ccu";
264 compatible = "allwinner,sun8i-h3-de2-clk";
268 compatible = "allwinner,sun7i-a20-mmc";
269 clocks = <&ccu CLK_BUS_MMC0>,
271 <&ccu CLK_MMC0_OUTPUT>,
272 <&ccu CLK_MMC0_SAMPLE>;
280 compatible = "allwinner,sun7i-a20-mmc";
281 clocks = <&ccu CLK_BUS_MMC1>,
283 <&ccu CLK_MMC1_OUTPUT>,
284 <&ccu CLK_MMC1_SAMPLE>;
292 compatible = "allwinner,sun7i-a20-mmc";
293 clocks = <&ccu CLK_BUS_MMC2>,
295 <&ccu CLK_MMC2_OUTPUT>,
296 <&ccu CLK_MMC2_SAMPLE>;
304 compatible = "allwinner,sun8i-h3-pinctrl";
308 compatible = "allwinner,sun8i-h3-rtc";
312 compatible = "allwinner,sun8i-h3-sid";