arch/arm/boot/dts/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 / {
  48         interrupt-parent = <&gic>;
  49         #address-cells = <1>;
  50         #size-cells = <1>;
  51
  52         aliases {
  53         };
  54
  55         chosen {
  56         };
  57
  58         cpus {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 cpu@0 {
  63                         compatible = "arm,cortex-a7";
  64                         device_type = "cpu";
  65                         reg = <0>;
  66                 };
  67
  68                 cpu@1 {
  69                         compatible = "arm,cortex-a7";
  70                         device_type = "cpu";
  71                         reg = <1>;
  72                 };
  73
  74                 cpu@2 {
  75                         compatible = "arm,cortex-a7";
  76                         device_type = "cpu";
  77                         reg = <2>;
  78                 };
  79
  80                 cpu@3 {
  81                         compatible = "arm,cortex-a7";
  82                         device_type = "cpu";
  83                         reg = <3>;
  84                 };
  85
  86                 cpu@100 {
  87                         compatible = "arm,cortex-a7";
  88                         device_type = "cpu";
  89                         reg = <0x100>;
  90                 };
  91
  92                 cpu@101 {
  93                         compatible = "arm,cortex-a7";
  94                         device_type = "cpu";
  95                         reg = <0x101>;
  96                 };
  97
  98                 cpu@102 {
  99                         compatible = "arm,cortex-a7";
 100                         device_type = "cpu";
 101                         reg = <0x102>;
 102                 };
 103
 104                 cpu@103 {
 105                         compatible = "arm,cortex-a7";
 106                         device_type = "cpu";
 107                         reg = <0x103>;
 108                 };
 109         };
 110
 111         timer {
 112                 compatible = "arm,armv7-timer";
 113                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 114                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 115                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 117         };
 118
 119         clocks {
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 ranges;
 123
 124                 /* TODO: PRCM block has a mux for this. */
 125                 osc24M: osc24M_clk {
 126                         #clock-cells = <0>;
 127                         compatible = "fixed-clock";
 128                         clock-frequency = <24000000>;
 129                         clock-accuracy = <50000>;
 130                         clock-output-names = "osc24M";
 131                 };
 132
 133                 /*
 134                  * This is called "internal OSC" in some places.
 135                  * It is an internal RC-based oscillator.
 136                  * TODO: Its controls are in the PRCM block.
 137                  */
 138                 osc16M: osc16M_clk {
 139                         #clock-cells = <0>;
 140                         compatible = "fixed-clock";
 141                         clock-frequency = <16000000>;
 142                         clock-output-names = "osc16M";
 143                 };
 144
 145                 osc16Md512: osc16Md512_clk {
 146                         #clock-cells = <0>;
 147                         compatible = "fixed-factor-clock";
 148                         clock-div = <512>;
 149                         clock-mult = <1>;
 150                         clocks = <&osc16M>;
 151                         clock-output-names = "osc16M-d512";
 152                 };
 153         };
 154
 155         memory {
 156                 reg = <0x40000000 0x80000000>;
 157                 device_type = "memory";
 158         };
 159
 160         soc {
 161                 compatible = "simple-bus";
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 ranges;
 165
 166                 ccu: clock@1c20000 {
 167                         compatible = "allwinner,sun8i-a83t-ccu";
 168                         reg = <0x01c20000 0x400>;
 169                         clocks = <&osc24M>, <&osc16Md512>;
 170                         clock-names = "hosc", "losc";
 171                         #clock-cells = <1>;
 172                         #reset-cells = <1>;
 173                 };
 174
 175                 pio: pinctrl@1c20800 {
 176                         compatible = "allwinner,sun8i-a83t-pinctrl";
 177                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 180                         reg = <0x01c20800 0x400>;
 181                         clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
 182                         clock-names = "apb", "hosc", "losc";
 183                         gpio-controller;
 184                         interrupt-controller;
 185                         #interrupt-cells = <3>;
 186                         #gpio-cells = <3>;
 187
 188                         mmc0_pins: mmc0-pins {
 189                                 pins = "PF0", "PF1", "PF2",
 190                                        "PF3", "PF4", "PF5";
 191                                 function = "mmc0";
 192                                 drive-strength = <30>;
 193                                 bias-pull-up;
 194                         };
 195
 196                         uart0_pb_pins: uart0-pb-pins {
 197                                 pins = "PB9", "PB10";
 198                                 function = "uart0";
 199                         };
 200
 201                         uart0_pf_pins: uart0-pf-pins {
 202                                 pins = "PF2", "PF4";
 203                                 function = "uart0";
 204                         };
 205                 };
 206
 207                 timer@1c20c00 {
 208                         compatible = "allwinner,sun4i-a10-timer";
 209                         reg = <0x01c20c00 0xa0>;
 210                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&osc24M>;
 213                 };
 214
 215                 watchdog@1c20ca0 {
 216                         compatible = "allwinner,sun6i-a31-wdt";
 217                         reg = <0x01c20ca0 0x20>;
 218                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&osc24M>;
 220                 };
 221
 222                 uart0: serial@01c28000 {
 223                         compatible = "snps,dw-apb-uart";
 224                         reg = <0x01c28000 0x400>;
 225                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 226                         reg-shift = <2>;
 227                         reg-io-width = <4>;
 228                         clocks = <&ccu 53>;
 229                         resets = <&ccu 40>;
 230                         status = "disabled";
 231                 };
 232
 233                 gic: interrupt-controller@1c81000 {
 234                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 235                         reg = <0x01c81000 0x1000>,
 236                               <0x01c82000 0x2000>,
 237                               <0x01c84000 0x2000>,
 238                               <0x01c86000 0x2000>;
 239                         interrupt-controller;
 240                         #interrupt-cells = <3>;
 241                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 242                 };
 243         };
 244 };