2 * Copyright 2015 Vishnu Patekar
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 interrupt-parent = <&gic>;
63 compatible = "arm,cortex-a7";
69 compatible = "arm,cortex-a7";
75 compatible = "arm,cortex-a7";
81 compatible = "arm,cortex-a7";
87 compatible = "arm,cortex-a7";
93 compatible = "arm,cortex-a7";
99 compatible = "arm,cortex-a7";
105 compatible = "arm,cortex-a7";
112 compatible = "arm,armv7-timer";
113 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
120 #address-cells = <1>;
124 /* TODO: PRCM block has a mux for this. */
127 compatible = "fixed-clock";
128 clock-frequency = <24000000>;
129 clock-accuracy = <50000>;
130 clock-output-names = "osc24M";
134 * This is called "internal OSC" in some places.
135 * It is an internal RC-based oscillator.
136 * TODO: Its controls are in the PRCM block.
140 compatible = "fixed-clock";
141 clock-frequency = <16000000>;
142 clock-output-names = "osc16M";
145 osc16Md512: osc16Md512_clk {
147 compatible = "fixed-factor-clock";
151 clock-output-names = "osc16M-d512";
156 reg = <0x40000000 0x80000000>;
157 device_type = "memory";
161 compatible = "simple-bus";
162 #address-cells = <1>;
167 compatible = "allwinner,sun8i-a83t-ccu";
168 reg = <0x01c20000 0x400>;
169 clocks = <&osc24M>, <&osc16Md512>;
170 clock-names = "hosc", "losc";
175 pio: pinctrl@1c20800 {
176 compatible = "allwinner,sun8i-a83t-pinctrl";
177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
180 reg = <0x01c20800 0x400>;
181 clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
182 clock-names = "apb", "hosc", "losc";
184 interrupt-controller;
185 #interrupt-cells = <3>;
188 mmc0_pins: mmc0-pins {
189 pins = "PF0", "PF1", "PF2",
192 drive-strength = <30>;
196 uart0_pb_pins: uart0-pb-pins {
197 pins = "PB9", "PB10";
201 uart0_pf_pins: uart0-pf-pins {
208 compatible = "allwinner,sun4i-a10-timer";
209 reg = <0x01c20c00 0xa0>;
210 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
216 compatible = "allwinner,sun6i-a31-wdt";
217 reg = <0x01c20ca0 0x20>;
218 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
222 uart0: serial@01c28000 {
223 compatible = "snps,dw-apb-uart";
224 reg = <0x01c28000 0x400>;
225 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
233 gic: interrupt-controller@1c81000 {
234 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
235 reg = <0x01c81000 0x1000>,
239 interrupt-controller;
240 #interrupt-cells = <3>;
241 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;