arch/arm/boot/dts/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
  48 #include <dt-bindings/clock/sun8i-de2.h>
  49 #include <dt-bindings/clock/sun8i-r-ccu.h>
  50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
  51 #include <dt-bindings/reset/sun8i-de2.h>
  52 #include <dt-bindings/reset/sun8i-r-ccu.h>
  53 #include <dt-bindings/thermal/thermal.h>
  54
  55 / {
  56         interrupt-parent = <&gic>;
  57         #address-cells = <1>;
  58         #size-cells = <1>;
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@0 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         clocks = <&ccu CLK_C0CPUX>;
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                         cci-control-port = <&cci_control0>;
  70                         enable-method = "allwinner,sun8i-a83t-smp";
  71                         reg = <0>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu@1 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         clocks = <&ccu CLK_C0CPUX>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         cci-control-port = <&cci_control0>;
  81                         enable-method = "allwinner,sun8i-a83t-smp";
  82                         reg = <1>;
  83                         #cooling-cells = <2>;
  84                 };
  85
  86                 cpu@2 {
  87                         compatible = "arm,cortex-a7";
  88                         device_type = "cpu";
  89                         clocks = <&ccu CLK_C0CPUX>;
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                         cci-control-port = <&cci_control0>;
  92                         enable-method = "allwinner,sun8i-a83t-smp";
  93                         reg = <2>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu@3 {
  98                         compatible = "arm,cortex-a7";
  99                         device_type = "cpu";
 100                         clocks = <&ccu CLK_C0CPUX>;
 101                         operating-points-v2 = <&cpu0_opp_table>;
 102                         cci-control-port = <&cci_control0>;
 103                         enable-method = "allwinner,sun8i-a83t-smp";
 104                         reg = <3>;
 105                         #cooling-cells = <2>;
 106                 };
 107
 108                 cpu100: cpu@100 {
 109                         compatible = "arm,cortex-a7";
 110                         device_type = "cpu";
 111                         clocks = <&ccu CLK_C1CPUX>;
 112                         operating-points-v2 = <&cpu1_opp_table>;
 113                         cci-control-port = <&cci_control1>;
 114                         enable-method = "allwinner,sun8i-a83t-smp";
 115                         reg = <0x100>;
 116                         #cooling-cells = <2>;
 117                 };
 118
 119                 cpu@101 {
 120                         compatible = "arm,cortex-a7";
 121                         device_type = "cpu";
 122                         clocks = <&ccu CLK_C1CPUX>;
 123                         operating-points-v2 = <&cpu1_opp_table>;
 124                         cci-control-port = <&cci_control1>;
 125                         enable-method = "allwinner,sun8i-a83t-smp";
 126                         reg = <0x101>;
 127                         #cooling-cells = <2>;
 128                 };
 129
 130                 cpu@102 {
 131                         compatible = "arm,cortex-a7";
 132                         device_type = "cpu";
 133                         clocks = <&ccu CLK_C1CPUX>;
 134                         operating-points-v2 = <&cpu1_opp_table>;
 135                         cci-control-port = <&cci_control1>;
 136                         enable-method = "allwinner,sun8i-a83t-smp";
 137                         reg = <0x102>;
 138                         #cooling-cells = <2>;
 139                 };
 140
 141                 cpu@103 {
 142                         compatible = "arm,cortex-a7";
 143                         device_type = "cpu";
 144                         clocks = <&ccu CLK_C1CPUX>;
 145                         operating-points-v2 = <&cpu1_opp_table>;
 146                         cci-control-port = <&cci_control1>;
 147                         enable-method = "allwinner,sun8i-a83t-smp";
 148                         reg = <0x103>;
 149                         #cooling-cells = <2>;
 150                 };
 151         };
 152
 153         timer {
 154                 compatible = "arm,armv7-timer";
 155                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 157                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 158                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 159         };
 160
 161         clocks {
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 ranges;
 165
 166                 /* TODO: PRCM block has a mux for this. */
 167                 osc24M: osc24M_clk {
 168                         #clock-cells = <0>;
 169                         compatible = "fixed-clock";
 170                         clock-frequency = <24000000>;
 171                         clock-accuracy = <50000>;
 172                         clock-output-names = "osc24M";
 173                 };
 174
 175                 /*
 176                  * This is called "internal OSC" in some places.
 177                  * It is an internal RC-based oscillator.
 178                  * TODO: Its controls are in the PRCM block.
 179                  */
 180                 osc16M: osc16M_clk {
 181                         #clock-cells = <0>;
 182                         compatible = "fixed-clock";
 183                         clock-frequency = <16000000>;
 184                         clock-output-names = "osc16M";
 185                 };
 186
 187                 osc16Md512: osc16Md512_clk {
 188                         #clock-cells = <0>;
 189                         compatible = "fixed-factor-clock";
 190                         clock-div = <512>;
 191                         clock-mult = <1>;
 192                         clocks = <&osc16M>;
 193                         clock-output-names = "osc16M-d512";
 194                 };
 195         };
 196
 197         de: display-engine {
 198                 compatible = "allwinner,sun8i-a83t-display-engine";
 199                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 200                 status = "disabled";
 201         };
 202
 203         cpu0_opp_table: opp_table0 {
 204                 compatible = "operating-points-v2";
 205                 opp-shared;
 206
 207                 opp-480000000 {
 208                         opp-hz = /bits/ 64 <480000000>;
 209                         opp-microvolt = <840000>;
 210                         clock-latency-ns = <244144>; /* 8 32k periods */
 211                 };
 212
 213                 opp-600000000 {
 214                         opp-hz = /bits/ 64 <600000000>;
 215                         opp-microvolt = <840000>;
 216                         clock-latency-ns = <244144>; /* 8 32k periods */
 217                 };
 218
 219                 opp-720000000 {
 220                         opp-hz = /bits/ 64 <720000000>;
 221                         opp-microvolt = <840000>;
 222                         clock-latency-ns = <244144>; /* 8 32k periods */
 223                 };
 224
 225                 opp-864000000 {
 226                         opp-hz = /bits/ 64 <864000000>;
 227                         opp-microvolt = <840000>;
 228                         clock-latency-ns = <244144>; /* 8 32k periods */
 229                 };
 230
 231                 opp-912000000 {
 232                         opp-hz = /bits/ 64 <912000000>;
 233                         opp-microvolt = <840000>;
 234                         clock-latency-ns = <244144>; /* 8 32k periods */
 235                 };
 236
 237                 opp-1008000000 {
 238                         opp-hz = /bits/ 64 <1008000000>;
 239                         opp-microvolt = <840000>;
 240                         clock-latency-ns = <244144>; /* 8 32k periods */
 241                 };
 242
 243                 opp-1128000000 {
 244                         opp-hz = /bits/ 64 <1128000000>;
 245                         opp-microvolt = <840000>;
 246                         clock-latency-ns = <244144>; /* 8 32k periods */
 247                 };
 248
 249                 opp-1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <840000>;
 252                         clock-latency-ns = <244144>; /* 8 32k periods */
 253                 };
 254         };
 255
 256         cpu1_opp_table: opp_table1 {
 257                 compatible = "operating-points-v2";
 258                 opp-shared;
 259
 260                 opp-480000000 {
 261                         opp-hz = /bits/ 64 <480000000>;
 262                         opp-microvolt = <840000>;
 263                         clock-latency-ns = <244144>; /* 8 32k periods */
 264                 };
 265
 266                 opp-600000000 {
 267                         opp-hz = /bits/ 64 <600000000>;
 268                         opp-microvolt = <840000>;
 269                         clock-latency-ns = <244144>; /* 8 32k periods */
 270                 };
 271
 272                 opp-720000000 {
 273                         opp-hz = /bits/ 64 <720000000>;
 274                         opp-microvolt = <840000>;
 275                         clock-latency-ns = <244144>; /* 8 32k periods */
 276                 };
 277
 278                 opp-864000000 {
 279                         opp-hz = /bits/ 64 <864000000>;
 280                         opp-microvolt = <840000>;
 281                         clock-latency-ns = <244144>; /* 8 32k periods */
 282                 };
 283
 284                 opp-912000000 {
 285                         opp-hz = /bits/ 64 <912000000>;
 286                         opp-microvolt = <840000>;
 287                         clock-latency-ns = <244144>; /* 8 32k periods */
 288                 };
 289
 290                 opp-1008000000 {
 291                         opp-hz = /bits/ 64 <1008000000>;
 292                         opp-microvolt = <840000>;
 293                         clock-latency-ns = <244144>; /* 8 32k periods */
 294                 };
 295
 296                 opp-1128000000 {
 297                         opp-hz = /bits/ 64 <1128000000>;
 298                         opp-microvolt = <840000>;
 299                         clock-latency-ns = <244144>; /* 8 32k periods */
 300                 };
 301
 302                 opp-1200000000 {
 303                         opp-hz = /bits/ 64 <1200000000>;
 304                         opp-microvolt = <840000>;
 305                         clock-latency-ns = <244144>; /* 8 32k periods */
 306                 };
 307         };
 308
 309         soc {
 310                 compatible = "simple-bus";
 311                 #address-cells = <1>;
 312                 #size-cells = <1>;
 313                 ranges;
 314
 315                 display_clocks: clock@1000000 {
 316                         compatible = "allwinner,sun8i-a83t-de2-clk";
 317                         reg = <0x01000000 0x100000>;
 318                         clocks = <&ccu CLK_BUS_DE>,
 319                                  <&ccu CLK_PLL_DE>;
 320                         clock-names = "bus",
 321                                       "mod";
 322                         resets = <&ccu RST_BUS_DE>;
 323                         #clock-cells = <1>;
 324                         #reset-cells = <1>;
 325                 };
 326
 327                 mixer0: mixer@1100000 {
 328                         compatible = "allwinner,sun8i-a83t-de2-mixer-0";
 329                         reg = <0x01100000 0x100000>;
 330                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 331                                  <&display_clocks CLK_MIXER0>;
 332                         clock-names = "bus",
 333                                       "mod";
 334                         resets = <&display_clocks RST_MIXER0>;
 335
 336                         ports {
 337                                 #address-cells = <1>;
 338                                 #size-cells = <0>;
 339
 340                                 mixer0_out: port@1 {
 341                                         #address-cells = <1>;
 342                                         #size-cells = <0>;
 343                                         reg = <1>;
 344
 345                                         mixer0_out_tcon0: endpoint@0 {
 346                                                 reg = <0>;
 347                                                 remote-endpoint = <&tcon0_in_mixer0>;
 348                                         };
 349
 350                                         mixer0_out_tcon1: endpoint@1 {
 351                                                 reg = <1>;
 352                                                 remote-endpoint = <&tcon1_in_mixer0>;
 353                                         };
 354                                 };
 355                         };
 356                 };
 357
 358                 mixer1: mixer@1200000 {
 359                         compatible = "allwinner,sun8i-a83t-de2-mixer-1";
 360                         reg = <0x01200000 0x100000>;
 361                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 362                                  <&display_clocks CLK_MIXER1>;
 363                         clock-names = "bus",
 364                                       "mod";
 365                         resets = <&display_clocks RST_WB>;
 366
 367                         ports {
 368                                 #address-cells = <1>;
 369                                 #size-cells = <0>;
 370
 371                                 mixer1_out: port@1 {
 372                                         #address-cells = <1>;
 373                                         #size-cells = <0>;
 374                                         reg = <1>;
 375
 376                                         mixer1_out_tcon0: endpoint@0 {
 377                                                 reg = <0>;
 378                                                 remote-endpoint = <&tcon0_in_mixer1>;
 379                                         };
 380
 381                                         mixer1_out_tcon1: endpoint@1 {
 382                                                 reg = <1>;
 383                                                 remote-endpoint = <&tcon1_in_mixer1>;
 384                                         };
 385                                 };
 386                         };
 387                 };
 388
 389                 cpucfg@1700000 {
 390                         compatible = "allwinner,sun8i-a83t-cpucfg";
 391                         reg = <0x01700000 0x400>;
 392                 };
 393
 394                 cci@1790000 {
 395                         compatible = "arm,cci-400";
 396                         #address-cells = <1>;
 397                         #size-cells = <1>;
 398                         reg = <0x01790000 0x10000>;
 399                         ranges = <0x0 0x01790000 0x10000>;
 400
 401                         cci_control0: slave-if@4000 {
 402                                 compatible = "arm,cci-400-ctrl-if";
 403                                 interface-type = "ace";
 404                                 reg = <0x4000 0x1000>;
 405                         };
 406
 407                         cci_control1: slave-if@5000 {
 408                                 compatible = "arm,cci-400-ctrl-if";
 409                                 interface-type = "ace";
 410                                 reg = <0x5000 0x1000>;
 411                         };
 412
 413                         pmu@9000 {
 414                                 compatible = "arm,cci-400-pmu,r1";
 415                                 reg = <0x9000 0x5000>;
 416                                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 417                                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 418                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 419                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 420                                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 421                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 423                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 424                         };
 425                 };
 426
 427                 syscon: syscon@1c00000 {
 428                         compatible = "allwinner,sun8i-a83t-system-controller",
 429                                 "syscon";
 430                         reg = <0x01c00000 0x1000>;
 431                 };
 432
 433                 dma: dma-controller@1c02000 {
 434                         compatible = "allwinner,sun8i-a83t-dma";
 435                         reg = <0x01c02000 0x1000>;
 436                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 437                         clocks = <&ccu CLK_BUS_DMA>;
 438                         resets = <&ccu RST_BUS_DMA>;
 439                         #dma-cells = <1>;
 440                 };
 441
 442                 tcon0: lcd-controller@1c0c000 {
 443                         compatible = "allwinner,sun8i-a83t-tcon-lcd";
 444                         reg = <0x01c0c000 0x1000>;
 445                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 447                         clock-names = "ahb", "tcon-ch0";
 448                         clock-output-names = "tcon-pixel-clock";
 449                         #clock-cells = <0>;
 450                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 451                         reset-names = "lcd", "lvds";
 452
 453                         ports {
 454                                 #address-cells = <1>;
 455                                 #size-cells = <0>;
 456
 457                                 tcon0_in: port@0 {
 458                                         #address-cells = <1>;
 459                                         #size-cells = <0>;
 460                                         reg = <0>;
 461
 462                                         tcon0_in_mixer0: endpoint@0 {
 463                                                 reg = <0>;
 464                                                 remote-endpoint = <&mixer0_out_tcon0>;
 465                                         };
 466
 467                                         tcon0_in_mixer1: endpoint@1 {
 468                                                 reg = <1>;
 469                                                 remote-endpoint = <&mixer1_out_tcon0>;
 470                                         };
 471                                 };
 472
 473                                 tcon0_out: port@1 {
 474                                         reg = <1>;
 475                                 };
 476                         };
 477                 };
 478
 479                 tcon1: lcd-controller@1c0d000 {
 480                         compatible = "allwinner,sun8i-a83t-tcon-tv";
 481                         reg = <0x01c0d000 0x1000>;
 482                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 483                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 484                         clock-names = "ahb", "tcon-ch1";
 485                         resets = <&ccu RST_BUS_TCON1>;
 486                         reset-names = "lcd";
 487
 488                         ports {
 489                                 #address-cells = <1>;
 490                                 #size-cells = <0>;
 491
 492                                 tcon1_in: port@0 {
 493                                         #address-cells = <1>;
 494                                         #size-cells = <0>;
 495                                         reg = <0>;
 496
 497                                         tcon1_in_mixer0: endpoint@0 {
 498                                                 reg = <0>;
 499                                                 remote-endpoint = <&mixer0_out_tcon1>;
 500                                         };
 501
 502                                         tcon1_in_mixer1: endpoint@1 {
 503                                                 reg = <1>;
 504                                                 remote-endpoint = <&mixer1_out_tcon1>;
 505                                         };
 506                                 };
 507
 508                                 tcon1_out: port@1 {
 509                                         #address-cells = <1>;
 510                                         #size-cells = <0>;
 511                                         reg = <1>;
 512
 513                                         tcon1_out_hdmi: endpoint@1 {
 514                                                 reg = <1>;
 515                                                 remote-endpoint = <&hdmi_in_tcon1>;
 516                                         };
 517                                 };
 518                         };
 519                 };
 520
 521                 mmc0: mmc@1c0f000 {
 522                         compatible = "allwinner,sun8i-a83t-mmc",
 523                                      "allwinner,sun7i-a20-mmc";
 524                         reg = <0x01c0f000 0x1000>;
 525                         clocks = <&ccu CLK_BUS_MMC0>,
 526                                  <&ccu CLK_MMC0>,
 527                                  <&ccu CLK_MMC0_OUTPUT>,
 528                                  <&ccu CLK_MMC0_SAMPLE>;
 529                         clock-names = "ahb",
 530                                       "mmc",
 531                                       "output",
 532                                       "sample";
 533                         resets = <&ccu RST_BUS_MMC0>;
 534                         reset-names = "ahb";
 535                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 536                         status = "disabled";
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                 };
 540
 541                 mmc1: mmc@1c10000 {
 542                         compatible = "allwinner,sun8i-a83t-mmc",
 543                                      "allwinner,sun7i-a20-mmc";
 544                         reg = <0x01c10000 0x1000>;
 545                         clocks = <&ccu CLK_BUS_MMC1>,
 546                                  <&ccu CLK_MMC1>,
 547                                  <&ccu CLK_MMC1_OUTPUT>,
 548                                  <&ccu CLK_MMC1_SAMPLE>;
 549                         clock-names = "ahb",
 550                                       "mmc",
 551                                       "output",
 552                                       "sample";
 553                         resets = <&ccu RST_BUS_MMC1>;
 554                         reset-names = "ahb";
 555                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 556                         pinctrl-names = "default";
 557                         pinctrl-0 = <&mmc1_pins>;
 558                         status = "disabled";
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                 };
 562
 563                 mmc2: mmc@1c11000 {
 564                         compatible = "allwinner,sun8i-a83t-emmc";
 565                         reg = <0x01c11000 0x1000>;
 566                         clocks = <&ccu CLK_BUS_MMC2>,
 567                                  <&ccu CLK_MMC2>,
 568                                  <&ccu CLK_MMC2_OUTPUT>,
 569                                  <&ccu CLK_MMC2_SAMPLE>;
 570                         clock-names = "ahb",
 571                                       "mmc",
 572                                       "output",
 573                                       "sample";
 574                         resets = <&ccu RST_BUS_MMC2>;
 575                         reset-names = "ahb";
 576                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 577                         status = "disabled";
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                 };
 581
 582                 sid: eeprom@1c14000 {
 583                         compatible = "allwinner,sun8i-a83t-sid";
 584                         reg = <0x1c14000 0x400>;
 585                         #address-cells = <1>;
 586                         #size-cells = <1>;
 587
 588                         ths_calibration: thermal-sensor-calibration@34 {
 589                                 reg = <0x34 8>;
 590                         };
 591                 };
 592
 593                 crypto: crypto@1c15000 {
 594                         compatible = "allwinner,sun8i-a83t-crypto";
 595                         reg = <0x01c15000 0x1000>;
 596                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 597                         resets = <&ccu RST_BUS_SS>;
 598                         clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
 599                         clock-names = "bus", "mod";
 600                 };
 601
 602                 usb_otg: usb@1c19000 {
 603                         compatible = "allwinner,sun8i-a83t-musb",
 604                                      "allwinner,sun8i-a33-musb";
 605                         reg = <0x01c19000 0x0400>;
 606                         clocks = <&ccu CLK_BUS_OTG>;
 607                         resets = <&ccu RST_BUS_OTG>;
 608                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 609                         interrupt-names = "mc";
 610                         phys = <&usbphy 0>;
 611                         phy-names = "usb";
 612                         extcon = <&usbphy 0>;
 613                         dr_mode = "otg";
 614                         status = "disabled";
 615                 };
 616
 617                 usbphy: phy@1c19400 {
 618                         compatible = "allwinner,sun8i-a83t-usb-phy";
 619                         reg = <0x01c19400 0x10>,
 620                               <0x01c1a800 0x14>,
 621                               <0x01c1b800 0x14>;
 622                         reg-names = "phy_ctrl",
 623                                     "pmu1",
 624                                     "pmu2";
 625                         clocks = <&ccu CLK_USB_PHY0>,
 626                                  <&ccu CLK_USB_PHY1>,
 627                                  <&ccu CLK_USB_HSIC>,
 628                                  <&ccu CLK_USB_HSIC_12M>;
 629                         clock-names = "usb0_phy",
 630                                       "usb1_phy",
 631                                       "usb2_phy",
 632                                       "usb2_hsic_12M";
 633                         resets = <&ccu RST_USB_PHY0>,
 634                                  <&ccu RST_USB_PHY1>,
 635                                  <&ccu RST_USB_HSIC>;
 636                         reset-names = "usb0_reset",
 637                                       "usb1_reset",
 638                                       "usb2_reset";
 639                         status = "disabled";
 640                         #phy-cells = <1>;
 641                 };
 642
 643                 ehci0: usb@1c1a000 {
 644                         compatible = "allwinner,sun8i-a83t-ehci",
 645                                      "generic-ehci";
 646                         reg = <0x01c1a000 0x100>;
 647                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 648                         clocks = <&ccu CLK_BUS_EHCI0>;
 649                         resets = <&ccu RST_BUS_EHCI0>;
 650                         phys = <&usbphy 1>;
 651                         phy-names = "usb";
 652                         status = "disabled";
 653                 };
 654
 655                 ohci0: usb@1c1a400 {
 656                         compatible = "allwinner,sun8i-a83t-ohci",
 657                                      "generic-ohci";
 658                         reg = <0x01c1a400 0x100>;
 659                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
 661                         resets = <&ccu RST_BUS_OHCI0>;
 662                         phys = <&usbphy 1>;
 663                         phy-names = "usb";
 664                         status = "disabled";
 665                 };
 666
 667                 ehci1: usb@1c1b000 {
 668                         compatible = "allwinner,sun8i-a83t-ehci",
 669                                      "generic-ehci";
 670                         reg = <0x01c1b000 0x100>;
 671                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 672                         clocks = <&ccu CLK_BUS_EHCI1>;
 673                         resets = <&ccu RST_BUS_EHCI1>;
 674                         phys = <&usbphy 2>;
 675                         phy-names = "usb";
 676                         status = "disabled";
 677                 };
 678
 679                 ccu: clock@1c20000 {
 680                         compatible = "allwinner,sun8i-a83t-ccu";
 681                         reg = <0x01c20000 0x400>;
 682                         clocks = <&osc24M>, <&osc16Md512>;
 683                         clock-names = "hosc", "losc";
 684                         #clock-cells = <1>;
 685                         #reset-cells = <1>;
 686                 };
 687
 688                 pio: pinctrl@1c20800 {
 689                         compatible = "allwinner,sun8i-a83t-pinctrl";
 690                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 693                         reg = <0x01c20800 0x400>;
 694                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
 695                         clock-names = "apb", "hosc", "losc";
 696                         gpio-controller;
 697                         interrupt-controller;
 698                         #interrupt-cells = <3>;
 699                         #gpio-cells = <3>;
 700
 701                         /omit-if-no-ref/
 702                         csi_8bit_parallel_pins: csi-8bit-parallel-pins {
 703                                 pins = "PE0", "PE2", "PE3", "PE6", "PE7",
 704                                        "PE8", "PE9", "PE10", "PE11",
 705                                        "PE12", "PE13";
 706                                 function = "csi";
 707                         };
 708
 709                         /omit-if-no-ref/
 710                         csi_mclk_pin: csi-mclk-pin {
 711                                 pins = "PE1";
 712                                 function = "csi";
 713                         };
 714
 715                         emac_rgmii_pins: emac-rgmii-pins {
 716                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 717                                        "PD11", "PD12", "PD13", "PD14", "PD18",
 718                                        "PD19", "PD21", "PD22", "PD23";
 719                                 function = "gmac";
 720                                 /*
 721                                  * data lines in RGMII mode use DDR mode
 722                                  * and need a higher signal drive strength
 723                                  */
 724                                 drive-strength = <40>;
 725                         };
 726
 727                         hdmi_pins: hdmi-pins {
 728                                 pins = "PH6", "PH7", "PH8";
 729                                 function = "hdmi";
 730                         };
 731
 732                         i2c0_pins: i2c0-pins {
 733                                 pins = "PH0", "PH1";
 734                                 function = "i2c0";
 735                         };
 736
 737                         i2c1_pins: i2c1-pins {
 738                                 pins = "PH2", "PH3";
 739                                 function = "i2c1";
 740                         };
 741
 742                         /omit-if-no-ref/
 743                         i2c2_pe_pins: i2c2-pe-pins {
 744                                 pins = "PE14", "PE15";
 745                                 function = "i2c2";
 746                         };
 747
 748                         i2c2_ph_pins: i2c2-ph-pins {
 749                                 pins = "PH4", "PH5";
 750                                 function = "i2c2";
 751                         };
 752
 753                         i2s1_pins: i2s1-pins {
 754                                 /* I2S1 does not have external MCLK pin */
 755                                 pins = "PG10", "PG11", "PG12", "PG13";
 756                                 function = "i2s1";
 757                         };
 758
 759                         lcd_lvds_pins: lcd-lvds-pins {
 760                                 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
 761                                        "PD23", "PD24", "PD25", "PD26", "PD27";
 762                                 function = "lvds0";
 763                         };
 764
 765                         mmc0_pins: mmc0-pins {
 766                                 pins = "PF0", "PF1", "PF2",
 767                                        "PF3", "PF4", "PF5";
 768                                 function = "mmc0";
 769                                 drive-strength = <30>;
 770                                 bias-pull-up;
 771                         };
 772
 773                         mmc1_pins: mmc1-pins {
 774                                 pins = "PG0", "PG1", "PG2",
 775                                        "PG3", "PG4", "PG5";
 776                                 function = "mmc1";
 777                                 drive-strength = <30>;
 778                                 bias-pull-up;
 779                         };
 780
 781                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 782                                 pins = "PC5", "PC6", "PC8", "PC9",
 783                                        "PC10", "PC11", "PC12", "PC13",
 784                                        "PC14", "PC15", "PC16";
 785                                 function = "mmc2";
 786                                 drive-strength = <30>;
 787                                 bias-pull-up;
 788                         };
 789
 790                         pwm_pin: pwm-pin {
 791                                 pins = "PD28";
 792                                 function = "pwm";
 793                         };
 794
 795                         spdif_tx_pin: spdif-tx-pin {
 796                                 pins = "PE18";
 797                                 function = "spdif";
 798                         };
 799
 800                         uart0_pb_pins: uart0-pb-pins {
 801                                 pins = "PB9", "PB10";
 802                                 function = "uart0";
 803                         };
 804
 805                         uart0_pf_pins: uart0-pf-pins {
 806                                 pins = "PF2", "PF4";
 807                                 function = "uart0";
 808                         };
 809
 810                         uart1_pins: uart1-pins {
 811                                 pins = "PG6", "PG7";
 812                                 function = "uart1";
 813                         };
 814
 815                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 816                                 pins = "PG8", "PG9";
 817                                 function = "uart1";
 818                         };
 819
 820                         /omit-if-no-ref/
 821                         uart2_pb_pins: uart2-pb-pins {
 822                                 pins = "PB0", "PB1";
 823                                 function = "uart2";
 824                         };
 825                 };
 826
 827                 timer@1c20c00 {
 828                         compatible = "allwinner,sun8i-a23-timer";
 829                         reg = <0x01c20c00 0xa0>;
 830                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 831                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 832                         clocks = <&osc24M>;
 833                 };
 834
 835                 watchdog@1c20ca0 {
 836                         compatible = "allwinner,sun6i-a31-wdt";
 837                         reg = <0x01c20ca0 0x20>;
 838                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 839                         clocks = <&osc24M>;
 840                 };
 841
 842                 spdif: spdif@1c21000 {
 843                         #sound-dai-cells = <0>;
 844                         compatible = "allwinner,sun8i-a83t-spdif",
 845                                      "allwinner,sun8i-h3-spdif";
 846                         reg = <0x01c21000 0x400>;
 847                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 848                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 849                         resets = <&ccu RST_BUS_SPDIF>;
 850                         clock-names = "apb", "spdif";
 851                         dmas = <&dma 2>;
 852                         dma-names = "tx";
 853                         pinctrl-names = "default";
 854                         pinctrl-0 = <&spdif_tx_pin>;
 855                         status = "disabled";
 856                 };
 857
 858                 i2s0: i2s@1c22000 {
 859                         #sound-dai-cells = <0>;
 860                         compatible = "allwinner,sun8i-a83t-i2s";
 861                         reg = <0x01c22000 0x400>;
 862                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 863                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 864                         clock-names = "apb", "mod";
 865                         dmas = <&dma 3>, <&dma 3>;
 866                         resets = <&ccu RST_BUS_I2S0>;
 867                         dma-names = "rx", "tx";
 868                         status = "disabled";
 869                 };
 870
 871                 i2s1: i2s@1c22400 {
 872                         #sound-dai-cells = <0>;
 873                         compatible = "allwinner,sun8i-a83t-i2s";
 874                         reg = <0x01c22400 0x400>;
 875                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 876                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 877                         clock-names = "apb", "mod";
 878                         dmas = <&dma 4>, <&dma 4>;
 879                         resets = <&ccu RST_BUS_I2S1>;
 880                         dma-names = "rx", "tx";
 881                         pinctrl-names = "default";
 882                         pinctrl-0 = <&i2s1_pins>;
 883                         status = "disabled";
 884                 };
 885
 886                 i2s2: i2s@1c22800 {
 887                         #sound-dai-cells = <0>;
 888                         compatible = "allwinner,sun8i-a83t-i2s";
 889                         reg = <0x01c22800 0x400>;
 890                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 891                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 892                         clock-names = "apb", "mod";
 893                         dmas = <&dma 27>;
 894                         resets = <&ccu RST_BUS_I2S2>;
 895                         dma-names = "tx";
 896                         status = "disabled";
 897                 };
 898
 899                 pwm: pwm@1c21400 {
 900                         compatible = "allwinner,sun8i-a83t-pwm",
 901                                      "allwinner,sun8i-h3-pwm";
 902                         reg = <0x01c21400 0x400>;
 903                         clocks = <&osc24M>;
 904                         #pwm-cells = <3>;
 905                         status = "disabled";
 906                 };
 907
 908                 uart0: serial@1c28000 {
 909                         compatible = "snps,dw-apb-uart";
 910                         reg = <0x01c28000 0x400>;
 911                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 912                         reg-shift = <2>;
 913                         reg-io-width = <4>;
 914                         clocks = <&ccu CLK_BUS_UART0>;
 915                         resets = <&ccu RST_BUS_UART0>;
 916                         status = "disabled";
 917                 };
 918
 919                 uart1: serial@1c28400 {
 920                         compatible = "snps,dw-apb-uart";
 921                         reg = <0x01c28400 0x400>;
 922                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 923                         reg-shift = <2>;
 924                         reg-io-width = <4>;
 925                         clocks = <&ccu CLK_BUS_UART1>;
 926                         resets = <&ccu RST_BUS_UART1>;
 927                         status = "disabled";
 928                 };
 929
 930                 uart2: serial@1c28800 {
 931                         compatible = "snps,dw-apb-uart";
 932                         reg = <0x01c28800 0x400>;
 933                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 934                         reg-shift = <2>;
 935                         reg-io-width = <4>;
 936                         clocks = <&ccu CLK_BUS_UART2>;
 937                         resets = <&ccu RST_BUS_UART2>;
 938                         status = "disabled";
 939                 };
 940
 941                 uart3: serial@1c28c00 {
 942                         compatible = "snps,dw-apb-uart";
 943                         reg = <0x01c28c00 0x400>;
 944                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 945                         reg-shift = <2>;
 946                         reg-io-width = <4>;
 947                         clocks = <&ccu CLK_BUS_UART3>;
 948                         resets = <&ccu RST_BUS_UART3>;
 949                         status = "disabled";
 950                 };
 951
 952                 uart4: serial@1c29000 {
 953                         compatible = "snps,dw-apb-uart";
 954                         reg = <0x01c29000 0x400>;
 955                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 956                         reg-shift = <2>;
 957                         reg-io-width = <4>;
 958                         clocks = <&ccu CLK_BUS_UART4>;
 959                         resets = <&ccu RST_BUS_UART4>;
 960                         status = "disabled";
 961                 };
 962
 963                 i2c0: i2c@1c2ac00 {
 964                         compatible = "allwinner,sun8i-a83t-i2c",
 965                                      "allwinner,sun6i-a31-i2c";
 966                         reg = <0x01c2ac00 0x400>;
 967                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 968                         clocks = <&ccu CLK_BUS_I2C0>;
 969                         resets = <&ccu RST_BUS_I2C0>;
 970                         pinctrl-names = "default";
 971                         pinctrl-0 = <&i2c0_pins>;
 972                         status = "disabled";
 973                         #address-cells = <1>;
 974                         #size-cells = <0>;
 975                 };
 976
 977                 i2c1: i2c@1c2b000 {
 978                         compatible = "allwinner,sun8i-a83t-i2c",
 979                                      "allwinner,sun6i-a31-i2c";
 980                         reg = <0x01c2b000 0x400>;
 981                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 982                         clocks = <&ccu CLK_BUS_I2C1>;
 983                         resets = <&ccu RST_BUS_I2C1>;
 984                         pinctrl-names = "default";
 985                         pinctrl-0 = <&i2c1_pins>;
 986                         status = "disabled";
 987                         #address-cells = <1>;
 988                         #size-cells = <0>;
 989                 };
 990
 991                 i2c2: i2c@1c2b400 {
 992                         compatible = "allwinner,sun8i-a83t-i2c",
 993                                      "allwinner,sun6i-a31-i2c";
 994                         reg = <0x01c2b400 0x400>;
 995                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 996                         clocks = <&ccu CLK_BUS_I2C2>;
 997                         resets = <&ccu RST_BUS_I2C2>;
 998                         status = "disabled";
 999                         #address-cells = <1>;
1000                         #size-cells = <0>;
1001                 };
1002
1003                 emac: ethernet@1c30000 {
1004                         compatible = "allwinner,sun8i-a83t-emac";
1005                         syscon = <&syscon>;
1006                         reg = <0x01c30000 0x104>;
1007                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1008                         interrupt-names = "macirq";
1009                         resets = <&ccu CLK_BUS_EMAC>;
1010                         reset-names = "stmmaceth";
1011                         clocks = <&ccu RST_BUS_EMAC>;
1012                         clock-names = "stmmaceth";
1013                         status = "disabled";
1014
1015                         mdio: mdio {
1016                                 compatible = "snps,dwmac-mdio";
1017                                 #address-cells = <1>;
1018                                 #size-cells = <0>;
1019                         };
1020                 };
1021
1022                 gic: interrupt-controller@1c81000 {
1023                         compatible = "arm,gic-400";
1024                         reg = <0x01c81000 0x1000>,
1025                               <0x01c82000 0x2000>,
1026                               <0x01c84000 0x2000>,
1027                               <0x01c86000 0x2000>;
1028                         interrupt-controller;
1029                         #interrupt-cells = <3>;
1030                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1031                 };
1032
1033                 csi: camera@1cb0000 {
1034                         compatible = "allwinner,sun8i-a83t-csi";
1035                         reg = <0x01cb0000 0x1000>;
1036                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1037                         clocks = <&ccu CLK_BUS_CSI>,
1038                                  <&ccu CLK_CSI_SCLK>,
1039                                  <&ccu CLK_DRAM_CSI>;
1040                         clock-names = "bus", "mod", "ram";
1041                         resets = <&ccu RST_BUS_CSI>;
1042                         status = "disabled";
1043
1044                         csi_in: port {
1045                         };
1046                 };
1047
1048                 hdmi: hdmi@1ee0000 {
1049                         compatible = "allwinner,sun8i-a83t-dw-hdmi";
1050                         reg = <0x01ee0000 0x10000>;
1051                         reg-io-width = <1>;
1052                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1053                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
1054                                  <&ccu CLK_HDMI>;
1055                         clock-names = "iahb", "isfr", "tmds";
1056                         resets = <&ccu RST_BUS_HDMI1>;
1057                         reset-names = "ctrl";
1058                         phys = <&hdmi_phy>;
1059                         phy-names = "phy";
1060                         pinctrl-names = "default";
1061                         pinctrl-0 = <&hdmi_pins>;
1062                         status = "disabled";
1063
1064                         ports {
1065                                 #address-cells = <1>;
1066                                 #size-cells = <0>;
1067
1068                                 hdmi_in: port@0 {
1069                                         reg = <0>;
1070
1071                                         hdmi_in_tcon1: endpoint {
1072                                                 remote-endpoint = <&tcon1_out_hdmi>;
1073                                         };
1074                                 };
1075
1076                                 hdmi_out: port@1 {
1077                                         reg = <1>;
1078                                 };
1079                         };
1080                 };
1081
1082                 hdmi_phy: hdmi-phy@1ef0000 {
1083                         compatible = "allwinner,sun8i-a83t-hdmi-phy";
1084                         reg = <0x01ef0000 0x10000>;
1085                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
1086                         clock-names = "bus", "mod";
1087                         resets = <&ccu RST_BUS_HDMI0>;
1088                         reset-names = "phy";
1089                         #phy-cells = <0>;
1090                 };
1091
1092                 r_intc: interrupt-controller@1f00c00 {
1093                         compatible = "allwinner,sun8i-a83t-r-intc",
1094                                      "allwinner,sun6i-a31-r-intc";
1095                         interrupt-controller;
1096                         #interrupt-cells = <2>;
1097                         reg = <0x01f00c00 0x400>;
1098                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1099                 };
1100
1101                 r_ccu: clock@1f01400 {
1102                         compatible = "allwinner,sun8i-a83t-r-ccu";
1103                         reg = <0x01f01400 0x400>;
1104                         clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
1105                                  <&ccu CLK_PLL_PERIPH>;
1106                         clock-names = "hosc", "losc", "iosc", "pll-periph";
1107                         #clock-cells = <1>;
1108                         #reset-cells = <1>;
1109                 };
1110
1111                 r_cpucfg@1f01c00 {
1112                         compatible = "allwinner,sun8i-a83t-r-cpucfg";
1113                         reg = <0x1f01c00 0x400>;
1114                 };
1115
1116                 r_cir: ir@1f02000 {
1117                         compatible = "allwinner,sun8i-a83t-ir",
1118                                 "allwinner,sun6i-a31-ir";
1119                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1120                         clock-names = "apb", "ir";
1121                         resets = <&r_ccu RST_APB0_IR>;
1122                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1123                         reg = <0x01f02000 0x400>;
1124                         pinctrl-names = "default";
1125                         pinctrl-0 = <&r_cir_pin>;
1126                         status = "disabled";
1127                 };
1128
1129                 r_lradc: lradc@1f03c00 {
1130                         compatible = "allwinner,sun8i-a83t-r-lradc";
1131                         reg = <0x01f03c00 0x100>;
1132                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1133                         status = "disabled";
1134                 };
1135
1136                 r_pio: pinctrl@1f02c00 {
1137                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
1138                         reg = <0x01f02c00 0x400>;
1139                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1140                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1141                                  <&osc16Md512>;
1142                         clock-names = "apb", "hosc", "losc";
1143                         gpio-controller;
1144                         #gpio-cells = <3>;
1145                         interrupt-controller;
1146                         #interrupt-cells = <3>;
1147
1148                         r_cir_pin: r-cir-pin {
1149                                 pins = "PL12";
1150                                 function = "s_cir_rx";
1151                         };
1152
1153                         r_rsb_pins: r-rsb-pins {
1154                                 pins = "PL0", "PL1";
1155                                 function = "s_rsb";
1156                                 drive-strength = <20>;
1157                                 bias-pull-up;
1158                         };
1159                 };
1160
1161                 r_rsb: rsb@1f03400 {
1162                         compatible = "allwinner,sun8i-a83t-rsb",
1163                                      "allwinner,sun8i-a23-rsb";
1164                         reg = <0x01f03400 0x400>;
1165                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1166                         clocks = <&r_ccu CLK_APB0_RSB>;
1167                         clock-frequency = <3000000>;
1168                         resets = <&r_ccu RST_APB0_RSB>;
1169                         pinctrl-names = "default";
1170                         pinctrl-0 = <&r_rsb_pins>;
1171                         status = "disabled";
1172                         #address-cells = <1>;
1173                         #size-cells = <0>;
1174                 };
1175
1176                 ths: thermal-sensor@1f04000 {
1177                         compatible = "allwinner,sun8i-a83t-ths";
1178                         reg = <0x01f04000 0x100>;
1179                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1180                         nvmem-cells = <&ths_calibration>;
1181                         nvmem-cell-names = "calibration";
1182                         #thermal-sensor-cells = <1>;
1183                 };
1184         };
1185
1186         thermal-zones {
1187                 cpu0_thermal: cpu0-thermal {
1188                         polling-delay-passive = <0>;
1189                         polling-delay = <0>;
1190                         thermal-sensors = <&ths 0>;
1191                 };
1192
1193                 cpu1_thermal: cpu1-thermal {
1194                         polling-delay-passive = <0>;
1195                         polling-delay = <0>;
1196                         thermal-sensors = <&ths 1>;
1197                 };
1198
1199                 gpu_thermal: gpu-thermal {
1200                         polling-delay-passive = <0>;
1201                         polling-delay = <0>;
1202                         thermal-sensors = <&ths 2>;
1203                 };
1204         };
1205 };