arch/arm/boot/dts/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
  48 #include <dt-bindings/clock/sun8i-de2.h>
  49 #include <dt-bindings/clock/sun8i-r-ccu.h>
  50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
  51 #include <dt-bindings/reset/sun8i-de2.h>
  52 #include <dt-bindings/reset/sun8i-r-ccu.h>
  53 #include <dt-bindings/thermal/thermal.h>
  54
  55 / {
  56         interrupt-parent = <&gic>;
  57         #address-cells = <1>;
  58         #size-cells = <1>;
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@0 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         clocks = <&ccu CLK_C0CPUX>;
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                         cci-control-port = <&cci_control0>;
  70                         enable-method = "allwinner,sun8i-a83t-smp";
  71                         reg = <0>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu1: cpu@1 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         clocks = <&ccu CLK_C0CPUX>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         cci-control-port = <&cci_control0>;
  81                         enable-method = "allwinner,sun8i-a83t-smp";
  82                         reg = <1>;
  83                         #cooling-cells = <2>;
  84                 };
  85
  86                 cpu2: cpu@2 {
  87                         compatible = "arm,cortex-a7";
  88                         device_type = "cpu";
  89                         clocks = <&ccu CLK_C0CPUX>;
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                         cci-control-port = <&cci_control0>;
  92                         enable-method = "allwinner,sun8i-a83t-smp";
  93                         reg = <2>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu3: cpu@3 {
  98                         compatible = "arm,cortex-a7";
  99                         device_type = "cpu";
 100                         clocks = <&ccu CLK_C0CPUX>;
 101                         operating-points-v2 = <&cpu0_opp_table>;
 102                         cci-control-port = <&cci_control0>;
 103                         enable-method = "allwinner,sun8i-a83t-smp";
 104                         reg = <3>;
 105                         #cooling-cells = <2>;
 106                 };
 107
 108                 cpu100: cpu@100 {
 109                         compatible = "arm,cortex-a7";
 110                         device_type = "cpu";
 111                         clocks = <&ccu CLK_C1CPUX>;
 112                         operating-points-v2 = <&cpu1_opp_table>;
 113                         cci-control-port = <&cci_control1>;
 114                         enable-method = "allwinner,sun8i-a83t-smp";
 115                         reg = <0x100>;
 116                         #cooling-cells = <2>;
 117                 };
 118
 119                 cpu101: cpu@101 {
 120                         compatible = "arm,cortex-a7";
 121                         device_type = "cpu";
 122                         clocks = <&ccu CLK_C1CPUX>;
 123                         operating-points-v2 = <&cpu1_opp_table>;
 124                         cci-control-port = <&cci_control1>;
 125                         enable-method = "allwinner,sun8i-a83t-smp";
 126                         reg = <0x101>;
 127                         #cooling-cells = <2>;
 128                 };
 129
 130                 cpu102: cpu@102 {
 131                         compatible = "arm,cortex-a7";
 132                         device_type = "cpu";
 133                         clocks = <&ccu CLK_C1CPUX>;
 134                         operating-points-v2 = <&cpu1_opp_table>;
 135                         cci-control-port = <&cci_control1>;
 136                         enable-method = "allwinner,sun8i-a83t-smp";
 137                         reg = <0x102>;
 138                         #cooling-cells = <2>;
 139                 };
 140
 141                 cpu103: cpu@103 {
 142                         compatible = "arm,cortex-a7";
 143                         device_type = "cpu";
 144                         clocks = <&ccu CLK_C1CPUX>;
 145                         operating-points-v2 = <&cpu1_opp_table>;
 146                         cci-control-port = <&cci_control1>;
 147                         enable-method = "allwinner,sun8i-a83t-smp";
 148                         reg = <0x103>;
 149                         #cooling-cells = <2>;
 150                 };
 151         };
 152
 153         timer {
 154                 compatible = "arm,armv7-timer";
 155                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 157                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 158                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 159         };
 160
 161         clocks {
 162                 #address-cells = <1>;
 163                 #size-cells = <1>;
 164                 ranges;
 165
 166                 /* TODO: PRCM block has a mux for this. */
 167                 osc24M: osc24M_clk {
 168                         #clock-cells = <0>;
 169                         compatible = "fixed-clock";
 170                         clock-frequency = <24000000>;
 171                         clock-accuracy = <50000>;
 172                         clock-output-names = "osc24M";
 173                 };
 174
 175                 /*
 176                  * This is called "internal OSC" in some places.
 177                  * It is an internal RC-based oscillator.
 178                  * TODO: Its controls are in the PRCM block.
 179                  */
 180                 osc16M: osc16M_clk {
 181                         #clock-cells = <0>;
 182                         compatible = "fixed-clock";
 183                         clock-frequency = <16000000>;
 184                         clock-output-names = "osc16M";
 185                 };
 186
 187                 osc16Md512: osc16Md512_clk {
 188                         #clock-cells = <0>;
 189                         compatible = "fixed-factor-clock";
 190                         clock-div = <512>;
 191                         clock-mult = <1>;
 192                         clocks = <&osc16M>;
 193                         clock-output-names = "osc16M-d512";
 194                 };
 195         };
 196
 197         de: display-engine {
 198                 compatible = "allwinner,sun8i-a83t-display-engine";
 199                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 200                 status = "disabled";
 201         };
 202
 203         cpu0_opp_table: opp_table0 {
 204                 compatible = "operating-points-v2";
 205                 opp-shared;
 206
 207                 opp-480000000 {
 208                         opp-hz = /bits/ 64 <480000000>;
 209                         opp-microvolt = <840000>;
 210                         clock-latency-ns = <244144>; /* 8 32k periods */
 211                 };
 212
 213                 opp-600000000 {
 214                         opp-hz = /bits/ 64 <600000000>;
 215                         opp-microvolt = <840000>;
 216                         clock-latency-ns = <244144>; /* 8 32k periods */
 217                 };
 218
 219                 opp-720000000 {
 220                         opp-hz = /bits/ 64 <720000000>;
 221                         opp-microvolt = <840000>;
 222                         clock-latency-ns = <244144>; /* 8 32k periods */
 223                 };
 224
 225                 opp-864000000 {
 226                         opp-hz = /bits/ 64 <864000000>;
 227                         opp-microvolt = <840000>;
 228                         clock-latency-ns = <244144>; /* 8 32k periods */
 229                 };
 230
 231                 opp-912000000 {
 232                         opp-hz = /bits/ 64 <912000000>;
 233                         opp-microvolt = <840000>;
 234                         clock-latency-ns = <244144>; /* 8 32k periods */
 235                 };
 236
 237                 opp-1008000000 {
 238                         opp-hz = /bits/ 64 <1008000000>;
 239                         opp-microvolt = <840000>;
 240                         clock-latency-ns = <244144>; /* 8 32k periods */
 241                 };
 242
 243                 opp-1128000000 {
 244                         opp-hz = /bits/ 64 <1128000000>;
 245                         opp-microvolt = <840000>;
 246                         clock-latency-ns = <244144>; /* 8 32k periods */
 247                 };
 248
 249                 opp-1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <840000>;
 252                         clock-latency-ns = <244144>; /* 8 32k periods */
 253                 };
 254         };
 255
 256         cpu1_opp_table: opp_table1 {
 257                 compatible = "operating-points-v2";
 258                 opp-shared;
 259
 260                 opp-480000000 {
 261                         opp-hz = /bits/ 64 <480000000>;
 262                         opp-microvolt = <840000>;
 263                         clock-latency-ns = <244144>; /* 8 32k periods */
 264                 };
 265
 266                 opp-600000000 {
 267                         opp-hz = /bits/ 64 <600000000>;
 268                         opp-microvolt = <840000>;
 269                         clock-latency-ns = <244144>; /* 8 32k periods */
 270                 };
 271
 272                 opp-720000000 {
 273                         opp-hz = /bits/ 64 <720000000>;
 274                         opp-microvolt = <840000>;
 275                         clock-latency-ns = <244144>; /* 8 32k periods */
 276                 };
 277
 278                 opp-864000000 {
 279                         opp-hz = /bits/ 64 <864000000>;
 280                         opp-microvolt = <840000>;
 281                         clock-latency-ns = <244144>; /* 8 32k periods */
 282                 };
 283
 284                 opp-912000000 {
 285                         opp-hz = /bits/ 64 <912000000>;
 286                         opp-microvolt = <840000>;
 287                         clock-latency-ns = <244144>; /* 8 32k periods */
 288                 };
 289
 290                 opp-1008000000 {
 291                         opp-hz = /bits/ 64 <1008000000>;
 292                         opp-microvolt = <840000>;
 293                         clock-latency-ns = <244144>; /* 8 32k periods */
 294                 };
 295
 296                 opp-1128000000 {
 297                         opp-hz = /bits/ 64 <1128000000>;
 298                         opp-microvolt = <840000>;
 299                         clock-latency-ns = <244144>; /* 8 32k periods */
 300                 };
 301
 302                 opp-1200000000 {
 303                         opp-hz = /bits/ 64 <1200000000>;
 304                         opp-microvolt = <840000>;
 305                         clock-latency-ns = <244144>; /* 8 32k periods */
 306                 };
 307         };
 308
 309         soc {
 310                 compatible = "simple-bus";
 311                 #address-cells = <1>;
 312                 #size-cells = <1>;
 313                 ranges;
 314
 315                 display_clocks: clock@1000000 {
 316                         compatible = "allwinner,sun8i-a83t-de2-clk";
 317                         reg = <0x01000000 0x10000>;
 318                         clocks = <&ccu CLK_BUS_DE>,
 319                                  <&ccu CLK_PLL_DE>;
 320                         clock-names = "bus",
 321                                       "mod";
 322                         resets = <&ccu RST_BUS_DE>;
 323                         #clock-cells = <1>;
 324                         #reset-cells = <1>;
 325                 };
 326
 327                 rotate: rotate@1020000 {
 328                         compatible = "allwinner,sun8i-a83t-de2-rotate";
 329                         reg = <0x1020000 0x10000>;
 330                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&display_clocks CLK_BUS_ROT>,
 332                                  <&display_clocks CLK_ROT>;
 333                         clock-names = "bus",
 334                                       "mod";
 335                         resets = <&display_clocks RST_ROT>;
 336                 };
 337
 338                 mixer0: mixer@1100000 {
 339                         compatible = "allwinner,sun8i-a83t-de2-mixer-0";
 340                         reg = <0x01100000 0x100000>;
 341                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 342                                  <&display_clocks CLK_MIXER0>;
 343                         clock-names = "bus",
 344                                       "mod";
 345                         resets = <&display_clocks RST_MIXER0>;
 346
 347                         ports {
 348                                 #address-cells = <1>;
 349                                 #size-cells = <0>;
 350
 351                                 mixer0_out: port@1 {
 352                                         #address-cells = <1>;
 353                                         #size-cells = <0>;
 354                                         reg = <1>;
 355
 356                                         mixer0_out_tcon0: endpoint@0 {
 357                                                 reg = <0>;
 358                                                 remote-endpoint = <&tcon0_in_mixer0>;
 359                                         };
 360
 361                                         mixer0_out_tcon1: endpoint@1 {
 362                                                 reg = <1>;
 363                                                 remote-endpoint = <&tcon1_in_mixer0>;
 364                                         };
 365                                 };
 366                         };
 367                 };
 368
 369                 mixer1: mixer@1200000 {
 370                         compatible = "allwinner,sun8i-a83t-de2-mixer-1";
 371                         reg = <0x01200000 0x100000>;
 372                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 373                                  <&display_clocks CLK_MIXER1>;
 374                         clock-names = "bus",
 375                                       "mod";
 376                         resets = <&display_clocks RST_WB>;
 377
 378                         ports {
 379                                 #address-cells = <1>;
 380                                 #size-cells = <0>;
 381
 382                                 mixer1_out: port@1 {
 383                                         #address-cells = <1>;
 384                                         #size-cells = <0>;
 385                                         reg = <1>;
 386
 387                                         mixer1_out_tcon0: endpoint@0 {
 388                                                 reg = <0>;
 389                                                 remote-endpoint = <&tcon0_in_mixer1>;
 390                                         };
 391
 392                                         mixer1_out_tcon1: endpoint@1 {
 393                                                 reg = <1>;
 394                                                 remote-endpoint = <&tcon1_in_mixer1>;
 395                                         };
 396                                 };
 397                         };
 398                 };
 399
 400                 cpucfg@1700000 {
 401                         compatible = "allwinner,sun8i-a83t-cpucfg";
 402                         reg = <0x01700000 0x400>;
 403                 };
 404
 405                 cci@1790000 {
 406                         compatible = "arm,cci-400";
 407                         #address-cells = <1>;
 408                         #size-cells = <1>;
 409                         reg = <0x01790000 0x10000>;
 410                         ranges = <0x0 0x01790000 0x10000>;
 411
 412                         cci_control0: slave-if@4000 {
 413                                 compatible = "arm,cci-400-ctrl-if";
 414                                 interface-type = "ace";
 415                                 reg = <0x4000 0x1000>;
 416                         };
 417
 418                         cci_control1: slave-if@5000 {
 419                                 compatible = "arm,cci-400-ctrl-if";
 420                                 interface-type = "ace";
 421                                 reg = <0x5000 0x1000>;
 422                         };
 423
 424                         pmu@9000 {
 425                                 compatible = "arm,cci-400-pmu,r1";
 426                                 reg = <0x9000 0x5000>;
 427                                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 428                                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 429                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 430                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 431                                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 433                                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 435                         };
 436                 };
 437
 438                 syscon: syscon@1c00000 {
 439                         compatible = "allwinner,sun8i-a83t-system-controller",
 440                                 "syscon";
 441                         reg = <0x01c00000 0x1000>;
 442                 };
 443
 444                 dma: dma-controller@1c02000 {
 445                         compatible = "allwinner,sun8i-a83t-dma";
 446                         reg = <0x01c02000 0x1000>;
 447                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 448                         clocks = <&ccu CLK_BUS_DMA>;
 449                         resets = <&ccu RST_BUS_DMA>;
 450                         #dma-cells = <1>;
 451                 };
 452
 453                 tcon0: lcd-controller@1c0c000 {
 454                         compatible = "allwinner,sun8i-a83t-tcon-lcd";
 455                         reg = <0x01c0c000 0x1000>;
 456                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 458                         clock-names = "ahb", "tcon-ch0";
 459                         clock-output-names = "tcon-pixel-clock";
 460                         #clock-cells = <0>;
 461                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 462                         reset-names = "lcd", "lvds";
 463
 464                         ports {
 465                                 #address-cells = <1>;
 466                                 #size-cells = <0>;
 467
 468                                 tcon0_in: port@0 {
 469                                         #address-cells = <1>;
 470                                         #size-cells = <0>;
 471                                         reg = <0>;
 472
 473                                         tcon0_in_mixer0: endpoint@0 {
 474                                                 reg = <0>;
 475                                                 remote-endpoint = <&mixer0_out_tcon0>;
 476                                         };
 477
 478                                         tcon0_in_mixer1: endpoint@1 {
 479                                                 reg = <1>;
 480                                                 remote-endpoint = <&mixer1_out_tcon0>;
 481                                         };
 482                                 };
 483
 484                                 tcon0_out: port@1 {
 485                                         reg = <1>;
 486                                 };
 487                         };
 488                 };
 489
 490                 tcon1: lcd-controller@1c0d000 {
 491                         compatible = "allwinner,sun8i-a83t-tcon-tv";
 492                         reg = <0x01c0d000 0x1000>;
 493                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 495                         clock-names = "ahb", "tcon-ch1";
 496                         resets = <&ccu RST_BUS_TCON1>;
 497                         reset-names = "lcd";
 498
 499                         ports {
 500                                 #address-cells = <1>;
 501                                 #size-cells = <0>;
 502
 503                                 tcon1_in: port@0 {
 504                                         #address-cells = <1>;
 505                                         #size-cells = <0>;
 506                                         reg = <0>;
 507
 508                                         tcon1_in_mixer0: endpoint@0 {
 509                                                 reg = <0>;
 510                                                 remote-endpoint = <&mixer0_out_tcon1>;
 511                                         };
 512
 513                                         tcon1_in_mixer1: endpoint@1 {
 514                                                 reg = <1>;
 515                                                 remote-endpoint = <&mixer1_out_tcon1>;
 516                                         };
 517                                 };
 518
 519                                 tcon1_out: port@1 {
 520                                         #address-cells = <1>;
 521                                         #size-cells = <0>;
 522                                         reg = <1>;
 523
 524                                         tcon1_out_hdmi: endpoint@1 {
 525                                                 reg = <1>;
 526                                                 remote-endpoint = <&hdmi_in_tcon1>;
 527                                         };
 528                                 };
 529                         };
 530                 };
 531
 532                 mmc0: mmc@1c0f000 {
 533                         compatible = "allwinner,sun8i-a83t-mmc",
 534                                      "allwinner,sun7i-a20-mmc";
 535                         reg = <0x01c0f000 0x1000>;
 536                         clocks = <&ccu CLK_BUS_MMC0>,
 537                                  <&ccu CLK_MMC0>,
 538                                  <&ccu CLK_MMC0_OUTPUT>,
 539                                  <&ccu CLK_MMC0_SAMPLE>;
 540                         clock-names = "ahb",
 541                                       "mmc",
 542                                       "output",
 543                                       "sample";
 544                         resets = <&ccu RST_BUS_MMC0>;
 545                         reset-names = "ahb";
 546                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 547                         status = "disabled";
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                 };
 551
 552                 mmc1: mmc@1c10000 {
 553                         compatible = "allwinner,sun8i-a83t-mmc",
 554                                      "allwinner,sun7i-a20-mmc";
 555                         reg = <0x01c10000 0x1000>;
 556                         clocks = <&ccu CLK_BUS_MMC1>,
 557                                  <&ccu CLK_MMC1>,
 558                                  <&ccu CLK_MMC1_OUTPUT>,
 559                                  <&ccu CLK_MMC1_SAMPLE>;
 560                         clock-names = "ahb",
 561                                       "mmc",
 562                                       "output",
 563                                       "sample";
 564                         resets = <&ccu RST_BUS_MMC1>;
 565                         reset-names = "ahb";
 566                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 567                         pinctrl-names = "default";
 568                         pinctrl-0 = <&mmc1_pins>;
 569                         status = "disabled";
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                 };
 573
 574                 mmc2: mmc@1c11000 {
 575                         compatible = "allwinner,sun8i-a83t-emmc";
 576                         reg = <0x01c11000 0x1000>;
 577                         clocks = <&ccu CLK_BUS_MMC2>,
 578                                  <&ccu CLK_MMC2>,
 579                                  <&ccu CLK_MMC2_OUTPUT>,
 580                                  <&ccu CLK_MMC2_SAMPLE>;
 581                         clock-names = "ahb",
 582                                       "mmc",
 583                                       "output",
 584                                       "sample";
 585                         resets = <&ccu RST_BUS_MMC2>;
 586                         reset-names = "ahb";
 587                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 588                         status = "disabled";
 589                         #address-cells = <1>;
 590                         #size-cells = <0>;
 591                 };
 592
 593                 sid: eeprom@1c14000 {
 594                         compatible = "allwinner,sun8i-a83t-sid";
 595                         reg = <0x1c14000 0x400>;
 596                         #address-cells = <1>;
 597                         #size-cells = <1>;
 598
 599                         ths_calibration: thermal-sensor-calibration@34 {
 600                                 reg = <0x34 8>;
 601                         };
 602                 };
 603
 604                 crypto: crypto@1c15000 {
 605                         compatible = "allwinner,sun8i-a83t-crypto";
 606                         reg = <0x01c15000 0x1000>;
 607                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 608                         resets = <&ccu RST_BUS_SS>;
 609                         clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
 610                         clock-names = "bus", "mod";
 611                 };
 612
 613                 usb_otg: usb@1c19000 {
 614                         compatible = "allwinner,sun8i-a83t-musb",
 615                                      "allwinner,sun8i-a33-musb";
 616                         reg = <0x01c19000 0x0400>;
 617                         clocks = <&ccu CLK_BUS_OTG>;
 618                         resets = <&ccu RST_BUS_OTG>;
 619                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 620                         interrupt-names = "mc";
 621                         phys = <&usbphy 0>;
 622                         phy-names = "usb";
 623                         extcon = <&usbphy 0>;
 624                         dr_mode = "otg";
 625                         status = "disabled";
 626                 };
 627
 628                 usbphy: phy@1c19400 {
 629                         compatible = "allwinner,sun8i-a83t-usb-phy";
 630                         reg = <0x01c19400 0x10>,
 631                               <0x01c1a800 0x14>,
 632                               <0x01c1b800 0x14>;
 633                         reg-names = "phy_ctrl",
 634                                     "pmu1",
 635                                     "pmu2";
 636                         clocks = <&ccu CLK_USB_PHY0>,
 637                                  <&ccu CLK_USB_PHY1>,
 638                                  <&ccu CLK_USB_HSIC>,
 639                                  <&ccu CLK_USB_HSIC_12M>;
 640                         clock-names = "usb0_phy",
 641                                       "usb1_phy",
 642                                       "usb2_phy",
 643                                       "usb2_hsic_12M";
 644                         resets = <&ccu RST_USB_PHY0>,
 645                                  <&ccu RST_USB_PHY1>,
 646                                  <&ccu RST_USB_HSIC>;
 647                         reset-names = "usb0_reset",
 648                                       "usb1_reset",
 649                                       "usb2_reset";
 650                         status = "disabled";
 651                         #phy-cells = <1>;
 652                 };
 653
 654                 ehci0: usb@1c1a000 {
 655                         compatible = "allwinner,sun8i-a83t-ehci",
 656                                      "generic-ehci";
 657                         reg = <0x01c1a000 0x100>;
 658                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 659                         clocks = <&ccu CLK_BUS_EHCI0>;
 660                         resets = <&ccu RST_BUS_EHCI0>;
 661                         phys = <&usbphy 1>;
 662                         phy-names = "usb";
 663                         status = "disabled";
 664                 };
 665
 666                 ohci0: usb@1c1a400 {
 667                         compatible = "allwinner,sun8i-a83t-ohci",
 668                                      "generic-ohci";
 669                         reg = <0x01c1a400 0x100>;
 670                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 671                         clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
 672                         resets = <&ccu RST_BUS_OHCI0>;
 673                         phys = <&usbphy 1>;
 674                         phy-names = "usb";
 675                         status = "disabled";
 676                 };
 677
 678                 ehci1: usb@1c1b000 {
 679                         compatible = "allwinner,sun8i-a83t-ehci",
 680                                      "generic-ehci";
 681                         reg = <0x01c1b000 0x100>;
 682                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&ccu CLK_BUS_EHCI1>;
 684                         resets = <&ccu RST_BUS_EHCI1>;
 685                         phys = <&usbphy 2>;
 686                         phy-names = "usb";
 687                         status = "disabled";
 688                 };
 689
 690                 ccu: clock@1c20000 {
 691                         compatible = "allwinner,sun8i-a83t-ccu";
 692                         reg = <0x01c20000 0x400>;
 693                         clocks = <&osc24M>, <&osc16Md512>;
 694                         clock-names = "hosc", "losc";
 695                         #clock-cells = <1>;
 696                         #reset-cells = <1>;
 697                 };
 698
 699                 pio: pinctrl@1c20800 {
 700                         compatible = "allwinner,sun8i-a83t-pinctrl";
 701                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 703                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 704                         reg = <0x01c20800 0x400>;
 705                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
 706                         clock-names = "apb", "hosc", "losc";
 707                         gpio-controller;
 708                         interrupt-controller;
 709                         #interrupt-cells = <3>;
 710                         #gpio-cells = <3>;
 711
 712                         /omit-if-no-ref/
 713                         csi_8bit_parallel_pins: csi-8bit-parallel-pins {
 714                                 pins = "PE0", "PE2", "PE3", "PE6", "PE7",
 715                                        "PE8", "PE9", "PE10", "PE11",
 716                                        "PE12", "PE13";
 717                                 function = "csi";
 718                         };
 719
 720                         /omit-if-no-ref/
 721                         csi_mclk_pin: csi-mclk-pin {
 722                                 pins = "PE1";
 723                                 function = "csi";
 724                         };
 725
 726                         emac_rgmii_pins: emac-rgmii-pins {
 727                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 728                                        "PD11", "PD12", "PD13", "PD14", "PD18",
 729                                        "PD19", "PD21", "PD22", "PD23";
 730                                 function = "gmac";
 731                                 /*
 732                                  * data lines in RGMII mode use DDR mode
 733                                  * and need a higher signal drive strength
 734                                  */
 735                                 drive-strength = <40>;
 736                         };
 737
 738                         hdmi_pins: hdmi-pins {
 739                                 pins = "PH6", "PH7", "PH8";
 740                                 function = "hdmi";
 741                         };
 742
 743                         i2c0_pins: i2c0-pins {
 744                                 pins = "PH0", "PH1";
 745                                 function = "i2c0";
 746                         };
 747
 748                         i2c1_pins: i2c1-pins {
 749                                 pins = "PH2", "PH3";
 750                                 function = "i2c1";
 751                         };
 752
 753                         /omit-if-no-ref/
 754                         i2c2_pe_pins: i2c2-pe-pins {
 755                                 pins = "PE14", "PE15";
 756                                 function = "i2c2";
 757                         };
 758
 759                         i2c2_ph_pins: i2c2-ph-pins {
 760                                 pins = "PH4", "PH5";
 761                                 function = "i2c2";
 762                         };
 763
 764                         i2s1_pins: i2s1-pins {
 765                                 /* I2S1 does not have external MCLK pin */
 766                                 pins = "PG10", "PG11", "PG12", "PG13";
 767                                 function = "i2s1";
 768                         };
 769
 770                         lcd_lvds_pins: lcd-lvds-pins {
 771                                 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
 772                                        "PD23", "PD24", "PD25", "PD26", "PD27";
 773                                 function = "lvds0";
 774                         };
 775
 776                         mmc0_pins: mmc0-pins {
 777                                 pins = "PF0", "PF1", "PF2",
 778                                        "PF3", "PF4", "PF5";
 779                                 function = "mmc0";
 780                                 drive-strength = <30>;
 781                                 bias-pull-up;
 782                         };
 783
 784                         mmc1_pins: mmc1-pins {
 785                                 pins = "PG0", "PG1", "PG2",
 786                                        "PG3", "PG4", "PG5";
 787                                 function = "mmc1";
 788                                 drive-strength = <30>;
 789                                 bias-pull-up;
 790                         };
 791
 792                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 793                                 pins = "PC5", "PC6", "PC8", "PC9",
 794                                        "PC10", "PC11", "PC12", "PC13",
 795                                        "PC14", "PC15", "PC16";
 796                                 function = "mmc2";
 797                                 drive-strength = <30>;
 798                                 bias-pull-up;
 799                         };
 800
 801                         pwm_pin: pwm-pin {
 802                                 pins = "PD28";
 803                                 function = "pwm";
 804                         };
 805
 806                         spdif_tx_pin: spdif-tx-pin {
 807                                 pins = "PE18";
 808                                 function = "spdif";
 809                         };
 810
 811                         uart0_pb_pins: uart0-pb-pins {
 812                                 pins = "PB9", "PB10";
 813                                 function = "uart0";
 814                         };
 815
 816                         uart0_pf_pins: uart0-pf-pins {
 817                                 pins = "PF2", "PF4";
 818                                 function = "uart0";
 819                         };
 820
 821                         uart1_pins: uart1-pins {
 822                                 pins = "PG6", "PG7";
 823                                 function = "uart1";
 824                         };
 825
 826                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 827                                 pins = "PG8", "PG9";
 828                                 function = "uart1";
 829                         };
 830
 831                         /omit-if-no-ref/
 832                         uart2_pb_pins: uart2-pb-pins {
 833                                 pins = "PB0", "PB1";
 834                                 function = "uart2";
 835                         };
 836                 };
 837
 838                 timer@1c20c00 {
 839                         compatible = "allwinner,sun8i-a23-timer";
 840                         reg = <0x01c20c00 0xa0>;
 841                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 842                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 843                         clocks = <&osc24M>;
 844                 };
 845
 846                 watchdog@1c20ca0 {
 847                         compatible = "allwinner,sun6i-a31-wdt";
 848                         reg = <0x01c20ca0 0x20>;
 849                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 850                         clocks = <&osc24M>;
 851                 };
 852
 853                 spdif: spdif@1c21000 {
 854                         #sound-dai-cells = <0>;
 855                         compatible = "allwinner,sun8i-a83t-spdif",
 856                                      "allwinner,sun8i-h3-spdif";
 857                         reg = <0x01c21000 0x400>;
 858                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 859                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 860                         resets = <&ccu RST_BUS_SPDIF>;
 861                         clock-names = "apb", "spdif";
 862                         dmas = <&dma 2>;
 863                         dma-names = "tx";
 864                         pinctrl-names = "default";
 865                         pinctrl-0 = <&spdif_tx_pin>;
 866                         status = "disabled";
 867                 };
 868
 869                 i2s0: i2s@1c22000 {
 870                         #sound-dai-cells = <0>;
 871                         compatible = "allwinner,sun8i-a83t-i2s";
 872                         reg = <0x01c22000 0x400>;
 873                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 874                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 875                         clock-names = "apb", "mod";
 876                         dmas = <&dma 3>, <&dma 3>;
 877                         resets = <&ccu RST_BUS_I2S0>;
 878                         dma-names = "rx", "tx";
 879                         status = "disabled";
 880                 };
 881
 882                 i2s1: i2s@1c22400 {
 883                         #sound-dai-cells = <0>;
 884                         compatible = "allwinner,sun8i-a83t-i2s";
 885                         reg = <0x01c22400 0x400>;
 886                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 887                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 888                         clock-names = "apb", "mod";
 889                         dmas = <&dma 4>, <&dma 4>;
 890                         resets = <&ccu RST_BUS_I2S1>;
 891                         dma-names = "rx", "tx";
 892                         pinctrl-names = "default";
 893                         pinctrl-0 = <&i2s1_pins>;
 894                         status = "disabled";
 895                 };
 896
 897                 i2s2: i2s@1c22800 {
 898                         #sound-dai-cells = <0>;
 899                         compatible = "allwinner,sun8i-a83t-i2s";
 900                         reg = <0x01c22800 0x400>;
 901                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 902                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 903                         clock-names = "apb", "mod";
 904                         dmas = <&dma 27>;
 905                         resets = <&ccu RST_BUS_I2S2>;
 906                         dma-names = "tx";
 907                         status = "disabled";
 908                 };
 909
 910                 pwm: pwm@1c21400 {
 911                         compatible = "allwinner,sun8i-a83t-pwm",
 912                                      "allwinner,sun8i-h3-pwm";
 913                         reg = <0x01c21400 0x400>;
 914                         clocks = <&osc24M>;
 915                         #pwm-cells = <3>;
 916                         status = "disabled";
 917                 };
 918
 919                 uart0: serial@1c28000 {
 920                         compatible = "snps,dw-apb-uart";
 921                         reg = <0x01c28000 0x400>;
 922                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 923                         reg-shift = <2>;
 924                         reg-io-width = <4>;
 925                         clocks = <&ccu CLK_BUS_UART0>;
 926                         resets = <&ccu RST_BUS_UART0>;
 927                         status = "disabled";
 928                 };
 929
 930                 uart1: serial@1c28400 {
 931                         compatible = "snps,dw-apb-uart";
 932                         reg = <0x01c28400 0x400>;
 933                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 934                         reg-shift = <2>;
 935                         reg-io-width = <4>;
 936                         clocks = <&ccu CLK_BUS_UART1>;
 937                         resets = <&ccu RST_BUS_UART1>;
 938                         status = "disabled";
 939                 };
 940
 941                 uart2: serial@1c28800 {
 942                         compatible = "snps,dw-apb-uart";
 943                         reg = <0x01c28800 0x400>;
 944                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 945                         reg-shift = <2>;
 946                         reg-io-width = <4>;
 947                         clocks = <&ccu CLK_BUS_UART2>;
 948                         resets = <&ccu RST_BUS_UART2>;
 949                         status = "disabled";
 950                 };
 951
 952                 uart3: serial@1c28c00 {
 953                         compatible = "snps,dw-apb-uart";
 954                         reg = <0x01c28c00 0x400>;
 955                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 956                         reg-shift = <2>;
 957                         reg-io-width = <4>;
 958                         clocks = <&ccu CLK_BUS_UART3>;
 959                         resets = <&ccu RST_BUS_UART3>;
 960                         status = "disabled";
 961                 };
 962
 963                 uart4: serial@1c29000 {
 964                         compatible = "snps,dw-apb-uart";
 965                         reg = <0x01c29000 0x400>;
 966                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 967                         reg-shift = <2>;
 968                         reg-io-width = <4>;
 969                         clocks = <&ccu CLK_BUS_UART4>;
 970                         resets = <&ccu RST_BUS_UART4>;
 971                         status = "disabled";
 972                 };
 973
 974                 i2c0: i2c@1c2ac00 {
 975                         compatible = "allwinner,sun8i-a83t-i2c",
 976                                      "allwinner,sun6i-a31-i2c";
 977                         reg = <0x01c2ac00 0x400>;
 978                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 979                         clocks = <&ccu CLK_BUS_I2C0>;
 980                         resets = <&ccu RST_BUS_I2C0>;
 981                         pinctrl-names = "default";
 982                         pinctrl-0 = <&i2c0_pins>;
 983                         status = "disabled";
 984                         #address-cells = <1>;
 985                         #size-cells = <0>;
 986                 };
 987
 988                 i2c1: i2c@1c2b000 {
 989                         compatible = "allwinner,sun8i-a83t-i2c",
 990                                      "allwinner,sun6i-a31-i2c";
 991                         reg = <0x01c2b000 0x400>;
 992                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 993                         clocks = <&ccu CLK_BUS_I2C1>;
 994                         resets = <&ccu RST_BUS_I2C1>;
 995                         pinctrl-names = "default";
 996                         pinctrl-0 = <&i2c1_pins>;
 997                         status = "disabled";
 998                         #address-cells = <1>;
 999                         #size-cells = <0>;
1000                 };
1001
1002                 i2c2: i2c@1c2b400 {
1003                         compatible = "allwinner,sun8i-a83t-i2c",
1004                                      "allwinner,sun6i-a31-i2c";
1005                         reg = <0x01c2b400 0x400>;
1006                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1007                         clocks = <&ccu CLK_BUS_I2C2>;
1008                         resets = <&ccu RST_BUS_I2C2>;
1009                         status = "disabled";
1010                         #address-cells = <1>;
1011                         #size-cells = <0>;
1012                 };
1013
1014                 emac: ethernet@1c30000 {
1015                         compatible = "allwinner,sun8i-a83t-emac";
1016                         syscon = <&syscon>;
1017                         reg = <0x01c30000 0x104>;
1018                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1019                         interrupt-names = "macirq";
1020                         clocks = <&ccu CLK_BUS_EMAC>;
1021                         clock-names = "stmmaceth";
1022                         resets = <&ccu RST_BUS_EMAC>;
1023                         reset-names = "stmmaceth";
1024                         status = "disabled";
1025
1026                         mdio: mdio {
1027                                 compatible = "snps,dwmac-mdio";
1028                                 #address-cells = <1>;
1029                                 #size-cells = <0>;
1030                         };
1031                 };
1032
1033                 gic: interrupt-controller@1c81000 {
1034                         compatible = "arm,gic-400";
1035                         reg = <0x01c81000 0x1000>,
1036                               <0x01c82000 0x2000>,
1037                               <0x01c84000 0x2000>,
1038                               <0x01c86000 0x2000>;
1039                         interrupt-controller;
1040                         #interrupt-cells = <3>;
1041                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1042                 };
1043
1044                 csi: camera@1cb0000 {
1045                         compatible = "allwinner,sun8i-a83t-csi";
1046                         reg = <0x01cb0000 0x1000>;
1047                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1048                         clocks = <&ccu CLK_BUS_CSI>,
1049                                  <&ccu CLK_CSI_SCLK>,
1050                                  <&ccu CLK_DRAM_CSI>;
1051                         clock-names = "bus", "mod", "ram";
1052                         resets = <&ccu RST_BUS_CSI>;
1053                         status = "disabled";
1054
1055                         csi_in: port {
1056                         };
1057                 };
1058
1059                 hdmi: hdmi@1ee0000 {
1060                         compatible = "allwinner,sun8i-a83t-dw-hdmi";
1061                         reg = <0x01ee0000 0x10000>;
1062                         reg-io-width = <1>;
1063                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1064                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
1065                                  <&ccu CLK_HDMI>;
1066                         clock-names = "iahb", "isfr", "tmds";
1067                         resets = <&ccu RST_BUS_HDMI1>;
1068                         reset-names = "ctrl";
1069                         phys = <&hdmi_phy>;
1070                         phy-names = "phy";
1071                         pinctrl-names = "default";
1072                         pinctrl-0 = <&hdmi_pins>;
1073                         status = "disabled";
1074
1075                         ports {
1076                                 #address-cells = <1>;
1077                                 #size-cells = <0>;
1078
1079                                 hdmi_in: port@0 {
1080                                         reg = <0>;
1081
1082                                         hdmi_in_tcon1: endpoint {
1083                                                 remote-endpoint = <&tcon1_out_hdmi>;
1084                                         };
1085                                 };
1086
1087                                 hdmi_out: port@1 {
1088                                         reg = <1>;
1089                                 };
1090                         };
1091                 };
1092
1093                 hdmi_phy: hdmi-phy@1ef0000 {
1094                         compatible = "allwinner,sun8i-a83t-hdmi-phy";
1095                         reg = <0x01ef0000 0x10000>;
1096                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
1097                         clock-names = "bus", "mod";
1098                         resets = <&ccu RST_BUS_HDMI0>;
1099                         reset-names = "phy";
1100                         #phy-cells = <0>;
1101                 };
1102
1103                 r_intc: interrupt-controller@1f00c00 {
1104                         compatible = "allwinner,sun8i-a83t-r-intc",
1105                                      "allwinner,sun6i-a31-r-intc";
1106                         interrupt-controller;
1107                         #interrupt-cells = <2>;
1108                         reg = <0x01f00c00 0x400>;
1109                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1110                 };
1111
1112                 r_ccu: clock@1f01400 {
1113                         compatible = "allwinner,sun8i-a83t-r-ccu";
1114                         reg = <0x01f01400 0x400>;
1115                         clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
1116                                  <&ccu CLK_PLL_PERIPH>;
1117                         clock-names = "hosc", "losc", "iosc", "pll-periph";
1118                         #clock-cells = <1>;
1119                         #reset-cells = <1>;
1120                 };
1121
1122                 r_cpucfg@1f01c00 {
1123                         compatible = "allwinner,sun8i-a83t-r-cpucfg";
1124                         reg = <0x1f01c00 0x400>;
1125                 };
1126
1127                 r_cir: ir@1f02000 {
1128                         compatible = "allwinner,sun8i-a83t-ir",
1129                                 "allwinner,sun6i-a31-ir";
1130                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1131                         clock-names = "apb", "ir";
1132                         resets = <&r_ccu RST_APB0_IR>;
1133                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1134                         reg = <0x01f02000 0x400>;
1135                         pinctrl-names = "default";
1136                         pinctrl-0 = <&r_cir_pin>;
1137                         status = "disabled";
1138                 };
1139
1140                 r_lradc: lradc@1f03c00 {
1141                         compatible = "allwinner,sun8i-a83t-r-lradc";
1142                         reg = <0x01f03c00 0x100>;
1143                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1144                         status = "disabled";
1145                 };
1146
1147                 r_pio: pinctrl@1f02c00 {
1148                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
1149                         reg = <0x01f02c00 0x400>;
1150                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1151                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1152                                  <&osc16Md512>;
1153                         clock-names = "apb", "hosc", "losc";
1154                         gpio-controller;
1155                         #gpio-cells = <3>;
1156                         interrupt-controller;
1157                         #interrupt-cells = <3>;
1158
1159                         r_cir_pin: r-cir-pin {
1160                                 pins = "PL12";
1161                                 function = "s_cir_rx";
1162                         };
1163
1164                         r_rsb_pins: r-rsb-pins {
1165                                 pins = "PL0", "PL1";
1166                                 function = "s_rsb";
1167                                 drive-strength = <20>;
1168                                 bias-pull-up;
1169                         };
1170                 };
1171
1172                 r_rsb: rsb@1f03400 {
1173                         compatible = "allwinner,sun8i-a83t-rsb",
1174                                      "allwinner,sun8i-a23-rsb";
1175                         reg = <0x01f03400 0x400>;
1176                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1177                         clocks = <&r_ccu CLK_APB0_RSB>;
1178                         clock-frequency = <3000000>;
1179                         resets = <&r_ccu RST_APB0_RSB>;
1180                         pinctrl-names = "default";
1181                         pinctrl-0 = <&r_rsb_pins>;
1182                         status = "disabled";
1183                         #address-cells = <1>;
1184                         #size-cells = <0>;
1185                 };
1186
1187                 ths: thermal-sensor@1f04000 {
1188                         compatible = "allwinner,sun8i-a83t-ths";
1189                         reg = <0x01f04000 0x100>;
1190                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1191                         nvmem-cells = <&ths_calibration>;
1192                         nvmem-cell-names = "calibration";
1193                         #thermal-sensor-cells = <1>;
1194                 };
1195         };
1196
1197         thermal-zones {
1198                 cpu0_thermal: cpu0-thermal {
1199                         polling-delay-passive = <0>;
1200                         polling-delay = <0>;
1201                         thermal-sensors = <&ths 0>;
1202
1203                         trips {
1204                                 cpu0_hot: cpu-hot {
1205                                         temperature = <80000>;
1206                                         hysteresis = <2000>;
1207                                         type = "passive";
1208                                 };
1209
1210                                 cpu0_very_hot: cpu-very-hot {
1211                                         temperature = <100000>;
1212                                         hysteresis = <0>;
1213                                         type = "critical";
1214                                 };
1215                         };
1216
1217                         cooling-maps {
1218                                 cpu-hot-limit {
1219                                         trip = <&cpu0_hot>;
1220                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1221                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1222                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1223                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1224                                 };
1225                         };
1226                 };
1227
1228                 cpu1_thermal: cpu1-thermal {
1229                         polling-delay-passive = <0>;
1230                         polling-delay = <0>;
1231                         thermal-sensors = <&ths 1>;
1232
1233                         trips {
1234                                 cpu1_hot: cpu-hot {
1235                                         temperature = <80000>;
1236                                         hysteresis = <2000>;
1237                                         type = "passive";
1238                                 };
1239
1240                                 cpu1_very_hot: cpu-very-hot {
1241                                         temperature = <100000>;
1242                                         hysteresis = <0>;
1243                                         type = "critical";
1244                                 };
1245                         };
1246
1247                         cooling-maps {
1248                                 cpu-hot-limit {
1249                                         trip = <&cpu1_hot>;
1250                                         cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1251                                                          <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1252                                                          <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1253                                                          <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1254                                 };
1255                         };
1256                 };
1257
1258                 gpu_thermal: gpu-thermal {
1259                         polling-delay-passive = <0>;
1260                         polling-delay = <0>;
1261                         thermal-sensors = <&ths 2>;
1262                 };
1263         };
1264 };