2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "sun8i-a23-a33.dtsi"
48 cpu0_opp_table: opp_table0 {
49 compatible = "operating-points-v2";
53 opp-hz = /bits/ 64 <648000000>;
54 opp-microvolt = <1040000>;
55 clock-latency-ns = <244144>; /* 8 32k periods */
59 opp-hz = /bits/ 64 <816000000>;
60 opp-microvolt = <1100000>;
61 clock-latency-ns = <244144>; /* 8 32k periods */
65 opp-hz = /bits/ 64 <1008000000>;
66 opp-microvolt = <1200000>;
67 clock-latency-ns = <244144>; /* 8 32k periods */
71 opp-hz = /bits/ 64 <1200000000>;
72 opp-microvolt = <1320000>;
73 clock-latency-ns = <244144>; /* 8 32k periods */
79 clocks = <&ccu CLK_CPUX>;
81 operating-points-v2 = <&cpu0_opp_table>;
85 compatible = "arm,cortex-a7";
91 compatible = "arm,cortex-a7";
98 compatible = "allwinner,sun8i-a33-display-engine";
99 allwinner,pipelines = <&fe0>;
104 reg = <0x40000000 0x80000000>;
108 compatible = "simple-audio-card";
109 simple-audio-card,name = "sun8i-a33-audio";
110 simple-audio-card,format = "i2s";
111 simple-audio-card,frame-master = <&link_codec>;
112 simple-audio-card,bitclock-master = <&link_codec>;
113 simple-audio-card,mclk-fs = <512>;
114 simple-audio-card,aux-devs = <&codec_analog>;
115 simple-audio-card,routing =
116 "Left DAC", "Digital Left DAC",
117 "Right DAC", "Digital Right DAC";
120 simple-audio-card,cpu {
124 link_codec: simple-audio-card,codec {
125 sound-dai = <&codec>;
130 tcon0: lcd-controller@01c0c000 {
131 compatible = "allwinner,sun8i-a33-tcon";
132 reg = <0x01c0c000 0x1000>;
133 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&ccu CLK_BUS_LCD>,
138 clock-output-names = "tcon-pixel-clock";
139 resets = <&ccu RST_BUS_LCD>;
144 #address-cells = <1>;
148 #address-cells = <1>;
152 tcon0_in_drc0: endpoint@0 {
154 remote-endpoint = <&drc0_out_tcon0>;
159 #address-cells = <1>;
166 crypto: crypto-engine@01c15000 {
167 compatible = "allwinner,sun4i-a10-crypto";
168 reg = <0x01c15000 0x1000>;
169 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
171 clock-names = "ahb", "mod";
172 resets = <&ccu RST_BUS_SS>;
177 #sound-dai-cells = <0>;
178 compatible = "allwinner,sun6i-a31-i2s";
179 reg = <0x01c22c00 0x200>;
180 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
182 clock-names = "apb", "mod";
183 resets = <&ccu RST_BUS_CODEC>;
184 dmas = <&dma 15>, <&dma 15>;
185 dma-names = "rx", "tx";
189 codec: codec@01c22e00 {
190 #sound-dai-cells = <0>;
191 compatible = "allwinner,sun8i-a33-codec";
192 reg = <0x01c22e00 0x400>;
193 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
195 clock-names = "bus", "mod";
199 fe0: display-frontend@01e00000 {
200 compatible = "allwinner,sun8i-a33-display-frontend";
201 reg = <0x01e00000 0x20000>;
202 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
204 <&ccu CLK_DRAM_DE_FE>;
205 clock-names = "ahb", "mod",
207 resets = <&ccu RST_BUS_DE_FE>;
211 #address-cells = <1>;
215 #address-cells = <1>;
219 fe0_out_be0: endpoint@0 {
221 remote-endpoint = <&be0_in_fe0>;
227 be0: display-backend@01e60000 {
228 compatible = "allwinner,sun8i-a33-display-backend";
229 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
230 reg-names = "be", "sat";
231 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
233 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
234 clock-names = "ahb", "mod",
236 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
237 reset-names = "be", "sat";
238 assigned-clocks = <&ccu CLK_DE_BE>;
239 assigned-clock-rates = <300000000>;
242 #address-cells = <1>;
246 #address-cells = <1>;
250 be0_in_fe0: endpoint@0 {
252 remote-endpoint = <&fe0_out_be0>;
257 #address-cells = <1>;
261 be0_out_drc0: endpoint@0 {
263 remote-endpoint = <&drc0_in_be0>;
270 compatible = "allwinner,sun8i-a33-drc";
271 reg = <0x01e70000 0x10000>;
272 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
275 clock-names = "ahb", "mod", "ram";
276 resets = <&ccu RST_BUS_DRC>;
278 assigned-clocks = <&ccu CLK_DRC>;
279 assigned-clock-rates = <300000000>;
282 #address-cells = <1>;
286 #address-cells = <1>;
290 drc0_in_be0: endpoint@0 {
292 remote-endpoint = <&be0_out_drc0>;
297 #address-cells = <1>;
301 drc0_out_tcon0: endpoint@0 {
303 remote-endpoint = <&tcon0_in_drc0>;
312 compatible = "allwinner,sun8i-a33-ccu";
316 compatible = "allwinner,sun8i-a33-pinctrl";
317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
320 uart0_pins_b: uart0@1 {
328 compatible = "allwinner,sun8i-a33-musb";
332 compatible = "allwinner,sun8i-a33-usb-phy";
333 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
334 reg-names = "phy_ctrl", "pmu1";