2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
54 opp-hz = /bits/ 64 <120000000>;
55 opp-microvolt = <1040000>;
56 clock-latency-ns = <244144>; /* 8 32k periods */
60 opp-hz = /bits/ 64 <240000000>;
61 opp-microvolt = <1040000>;
62 clock-latency-ns = <244144>; /* 8 32k periods */
66 opp-hz = /bits/ 64 <312000000>;
67 opp-microvolt = <1040000>;
68 clock-latency-ns = <244144>; /* 8 32k periods */
72 opp-hz = /bits/ 64 <408000000>;
73 opp-microvolt = <1040000>;
74 clock-latency-ns = <244144>; /* 8 32k periods */
78 opp-hz = /bits/ 64 <480000000>;
79 opp-microvolt = <1040000>;
80 clock-latency-ns = <244144>; /* 8 32k periods */
84 opp-hz = /bits/ 64 <504000000>;
85 opp-microvolt = <1040000>;
86 clock-latency-ns = <244144>; /* 8 32k periods */
90 opp-hz = /bits/ 64 <600000000>;
91 opp-microvolt = <1040000>;
92 clock-latency-ns = <244144>; /* 8 32k periods */
96 opp-hz = /bits/ 64 <648000000>;
97 opp-microvolt = <1040000>;
98 clock-latency-ns = <244144>; /* 8 32k periods */
102 opp-hz = /bits/ 64 <720000000>;
103 opp-microvolt = <1100000>;
104 clock-latency-ns = <244144>; /* 8 32k periods */
108 opp-hz = /bits/ 64 <816000000>;
109 opp-microvolt = <1100000>;
110 clock-latency-ns = <244144>; /* 8 32k periods */
114 opp-hz = /bits/ 64 <912000000>;
115 opp-microvolt = <1200000>;
116 clock-latency-ns = <244144>; /* 8 32k periods */
120 opp-hz = /bits/ 64 <1008000000>;
121 opp-microvolt = <1200000>;
122 clock-latency-ns = <244144>; /* 8 32k periods */
128 clocks = <&ccu CLK_CPUX>;
130 operating-points-v2 = <&cpu0_opp_table>;
131 #cooling-cells = <2>;
135 clocks = <&ccu CLK_CPUX>;
137 operating-points-v2 = <&cpu0_opp_table>;
138 #cooling-cells = <2>;
142 compatible = "arm,cortex-a7";
145 clocks = <&ccu CLK_CPUX>;
147 operating-points-v2 = <&cpu0_opp_table>;
148 #cooling-cells = <2>;
152 compatible = "arm,cortex-a7";
155 clocks = <&ccu CLK_CPUX>;
157 operating-points-v2 = <&cpu0_opp_table>;
158 #cooling-cells = <2>;
163 compatible = "iio-hwmon";
164 io-channels = <&ths>;
167 mali_opp_table: gpu-opp-table {
168 compatible = "operating-points-v2";
171 opp-hz = /bits/ 64 <144000000>;
175 opp-hz = /bits/ 64 <240000000>;
179 opp-hz = /bits/ 64 <384000000>;
184 compatible = "simple-audio-card";
185 simple-audio-card,name = "sun8i-a33-audio";
186 simple-audio-card,format = "i2s";
187 simple-audio-card,frame-master = <&link_codec>;
188 simple-audio-card,bitclock-master = <&link_codec>;
189 simple-audio-card,mclk-fs = <128>;
190 simple-audio-card,aux-devs = <&codec_analog>;
191 simple-audio-card,routing =
192 "Left DAC", "AIF1 Slot 0 Left",
193 "Right DAC", "AIF1 Slot 0 Right";
196 simple-audio-card,cpu {
200 link_codec: simple-audio-card,codec {
201 sound-dai = <&codec>;
206 video-codec@1c0e000 {
207 compatible = "allwinner,sun8i-a33-video-engine";
208 reg = <0x01c0e000 0x1000>;
209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
211 clock-names = "ahb", "mod", "ram";
212 resets = <&ccu RST_BUS_VE>;
213 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
214 allwinner,sram = <&ve_sram 1>;
217 crypto: crypto-engine@1c15000 {
218 compatible = "allwinner,sun4i-a10-crypto";
219 reg = <0x01c15000 0x1000>;
220 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
222 clock-names = "ahb", "mod";
223 resets = <&ccu RST_BUS_SS>;
228 #sound-dai-cells = <0>;
229 compatible = "allwinner,sun6i-a31-i2s";
230 reg = <0x01c22c00 0x200>;
231 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
233 clock-names = "apb", "mod";
234 resets = <&ccu RST_BUS_CODEC>;
235 dmas = <&dma 15>, <&dma 15>;
236 dma-names = "rx", "tx";
240 codec: codec@1c22e00 {
241 #sound-dai-cells = <0>;
242 compatible = "allwinner,sun8i-a33-codec";
243 reg = <0x01c22e00 0x400>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
246 clock-names = "bus", "mod";
251 compatible = "allwinner,sun8i-a33-ths";
252 reg = <0x01c25000 0x100>;
253 #thermal-sensor-cells = <0>;
254 #io-channel-cells = <0>;
258 compatible = "allwinner,sun6i-a31-mipi-dsi";
259 reg = <0x01ca0000 0x1000>;
260 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&ccu CLK_BUS_MIPI_DSI>,
263 clock-names = "bus", "mod";
264 resets = <&ccu RST_BUS_MIPI_DSI>;
268 #address-cells = <1>;
272 dsi_in_tcon0: endpoint {
273 remote-endpoint = <&tcon0_out_dsi>;
278 dphy: d-phy@1ca1000 {
279 compatible = "allwinner,sun6i-a31-mipi-dphy";
280 reg = <0x01ca1000 0x1000>;
281 clocks = <&ccu CLK_BUS_MIPI_DSI>,
283 clock-names = "bus", "mod";
284 resets = <&ccu RST_BUS_MIPI_DSI>;
293 polling-delay-passive = <250>;
294 polling-delay = <1000>;
295 thermal-sensors = <&ths>;
299 trip = <&cpu_alert0>;
300 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
301 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
302 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
303 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
306 trip = <&cpu_alert1>;
307 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
308 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
309 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
310 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
314 trip = <&gpu_alert0>;
315 cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
319 trip = <&gpu_alert1>;
320 cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
325 cpu_alert0: cpu_alert0 {
327 temperature = <75000>;
332 gpu_alert0: gpu_alert0 {
334 temperature = <85000>;
339 cpu_alert1: cpu_alert1 {
341 temperature = <90000>;
346 gpu_alert1: gpu_alert1 {
348 temperature = <95000>;
355 temperature = <110000>;
365 compatible = "allwinner,sun8i-a33-display-backend";
366 /* A33 has an extra "SAT" module packed inside the display backend */
367 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
368 reg-names = "be", "sat";
369 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
370 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
371 clock-names = "ahb", "mod",
373 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
374 reset-names = "be", "sat";
375 assigned-clocks = <&ccu CLK_DE_BE>;
376 assigned-clock-rates = <300000000>;
380 compatible = "allwinner,sun8i-a33-ccu";
384 compatible = "allwinner,sun8i-a33-display-engine";
388 compatible = "allwinner,sun8i-a33-drc";
392 compatible = "allwinner,sun8i-a33-display-frontend";
396 operating-points-v2 = <&mali_opp_table>;
400 compatible = "allwinner,sun8i-a33-pinctrl";
401 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
404 uart0_pb_pins: uart0-pb-pins {
412 compatible = "allwinner,sun8i-a33-tcon";
416 #address-cells = <1>;
419 tcon0_out_dsi: endpoint@1 {
421 remote-endpoint = <&dsi_in_tcon0>;
426 compatible = "allwinner,sun8i-a33-musb";
430 compatible = "allwinner,sun8i-a33-usb-phy";
431 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
432 reg-names = "phy_ctrl", "pmu1";