2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
51 interrupt-parent = <&gic>;
60 simplefb_lcd: framebuffer-lcd0 {
61 compatible = "allwinner,simple-framebuffer",
63 allwinner,pipeline = "de_be0-lcd0";
64 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
65 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
66 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
72 /* compatible gets set in SoC specific dtsi file */
73 allwinner,pipelines = <&fe0>;
78 compatible = "arm,armv7-timer";
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
83 clock-frequency = <24000000>;
84 arm,cpu-registers-not-fw-configured;
88 enable-method = "allwinner,sun8i-a23";
93 compatible = "arm,cortex-a7";
99 compatible = "arm,cortex-a7";
106 #address-cells = <1>;
112 compatible = "fixed-clock";
113 clock-frequency = <24000000>;
114 clock-accuracy = <50000>;
115 clock-output-names = "osc24M";
118 ext_osc32k: ext_osc32k_clk {
120 compatible = "fixed-clock";
121 clock-frequency = <32768>;
122 clock-accuracy = <50000>;
123 clock-output-names = "ext-osc32k";
128 compatible = "simple-bus";
129 #address-cells = <1>;
133 system-control@1c00000 {
134 compatible = "allwinner,sun8i-a23-system-control";
135 reg = <0x01c00000 0x30>;
136 #address-cells = <1>;
140 sram_c: sram@1d00000 {
141 compatible = "mmio-sram";
142 reg = <0x01d00000 0x80000>;
143 #address-cells = <1>;
145 ranges = <0 0x01d00000 0x80000>;
147 ve_sram: sram-section@0 {
148 compatible = "allwinner,sun8i-a23-sram-c1",
149 "allwinner,sun4i-a10-sram-c1";
150 reg = <0x000000 0x80000>;
155 dma: dma-controller@1c02000 {
156 compatible = "allwinner,sun8i-a23-dma";
157 reg = <0x01c02000 0x1000>;
158 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&ccu CLK_BUS_DMA>;
160 resets = <&ccu RST_BUS_DMA>;
164 nfc: nand-controller@1c03000 {
165 compatible = "allwinner,sun8i-a23-nand-controller";
166 reg = <0x01c03000 0x1000>;
167 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
169 clock-names = "ahb", "mod";
170 resets = <&ccu RST_BUS_NAND>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
177 #address-cells = <1>;
181 tcon0: lcd-controller@1c0c000 {
182 /* compatible gets set in SoC specific dtsi file */
183 reg = <0x01c0c000 0x1000>;
184 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&ccu CLK_BUS_LCD>,
192 clock-output-names = "tcon-pixel-clock";
194 resets = <&ccu RST_BUS_LCD>,
201 #address-cells = <1>;
207 tcon0_in_drc0: endpoint {
208 remote-endpoint = <&drc0_out_tcon0>;
219 compatible = "allwinner,sun7i-a20-mmc";
220 reg = <0x01c0f000 0x1000>;
221 clocks = <&ccu CLK_BUS_MMC0>,
223 <&ccu CLK_MMC0_OUTPUT>,
224 <&ccu CLK_MMC0_SAMPLE>;
229 resets = <&ccu RST_BUS_MMC0>;
231 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&mmc0_pins>;
235 #address-cells = <1>;
240 compatible = "allwinner,sun7i-a20-mmc";
241 reg = <0x01c10000 0x1000>;
242 clocks = <&ccu CLK_BUS_MMC1>,
244 <&ccu CLK_MMC1_OUTPUT>,
245 <&ccu CLK_MMC1_SAMPLE>;
250 resets = <&ccu RST_BUS_MMC1>;
252 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
259 compatible = "allwinner,sun7i-a20-mmc";
260 reg = <0x01c11000 0x1000>;
261 clocks = <&ccu CLK_BUS_MMC2>,
263 <&ccu CLK_MMC2_OUTPUT>,
264 <&ccu CLK_MMC2_SAMPLE>;
269 resets = <&ccu RST_BUS_MMC2>;
271 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
273 #address-cells = <1>;
277 usb_otg: usb@1c19000 {
278 /* compatible gets set in SoC specific dtsi file */
279 reg = <0x01c19000 0x0400>;
280 clocks = <&ccu CLK_BUS_OTG>;
281 resets = <&ccu RST_BUS_OTG>;
282 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "mc";
286 extcon = <&usbphy 0>;
291 usbphy: phy@1c19400 {
293 * compatible and address regions get set in
294 * SoC specific dtsi file
296 clocks = <&ccu CLK_USB_PHY0>,
298 clock-names = "usb0_phy",
300 resets = <&ccu RST_USB_PHY0>,
302 reset-names = "usb0_reset",
309 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
310 reg = <0x01c1a000 0x100>;
311 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&ccu CLK_BUS_EHCI>;
313 resets = <&ccu RST_BUS_EHCI>;
320 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
321 reg = <0x01c1a400 0x100>;
322 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
324 resets = <&ccu RST_BUS_OHCI>;
331 reg = <0x01c20000 0x400>;
332 clocks = <&osc24M>, <&rtc 0>;
333 clock-names = "hosc", "losc";
338 pio: pinctrl@1c20800 {
339 /* compatible gets set in SoC specific dtsi file */
340 reg = <0x01c20800 0x400>;
341 interrupt-parent = <&r_intc>;
342 /* interrupts get set in SoC specific dtsi file */
343 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
344 clock-names = "apb", "hosc", "losc";
346 interrupt-controller;
347 #interrupt-cells = <3>;
350 i2c0_pins: i2c0-pins {
355 i2c1_pins: i2c1-pins {
360 i2c2_pins: i2c2-pins {
361 pins = "PE12", "PE13";
365 lcd_rgb666_pins: lcd-rgb666-pins {
366 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
367 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
368 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
369 "PD24", "PD25", "PD26", "PD27";
373 mmc0_pins: mmc0-pins {
374 pins = "PF0", "PF1", "PF2",
377 drive-strength = <30>;
381 mmc1_pg_pins: mmc1-pg-pins {
382 pins = "PG0", "PG1", "PG2",
385 drive-strength = <30>;
389 mmc2_8bit_pins: mmc2-8bit-pins {
390 pins = "PC5", "PC6", "PC8",
391 "PC9", "PC10", "PC11",
392 "PC12", "PC13", "PC14",
395 drive-strength = <30>;
399 nand_pins: nand-pins {
400 pins = "PC0", "PC1", "PC2", "PC5",
401 "PC8", "PC9", "PC10", "PC11",
402 "PC12", "PC13", "PC14", "PC15";
406 nand_cs0_pin: nand-cs0-pin {
412 nand_cs1_pin: nand-cs1-pin {
418 nand_rb0_pin: nand-rb0-pin {
424 nand_rb1_pin: nand-rb1-pin {
435 uart0_pf_pins: uart0-pf-pins {
440 uart1_pg_pins: uart1-pg-pins {
445 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
452 compatible = "allwinner,sun8i-a23-timer";
453 reg = <0x01c20c00 0xa0>;
454 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
459 wdt0: watchdog@1c20ca0 {
460 compatible = "allwinner,sun6i-a31-wdt";
461 reg = <0x01c20ca0 0x20>;
462 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
467 compatible = "allwinner,sun7i-a20-pwm";
468 reg = <0x01c21400 0xc>;
474 lradc: lradc@1c22800 {
475 compatible = "allwinner,sun4i-a10-lradc-keys";
476 reg = <0x01c22800 0x100>;
477 interrupt-parent = <&r_intc>;
478 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
482 uart0: serial@1c28000 {
483 compatible = "snps,dw-apb-uart";
484 reg = <0x01c28000 0x400>;
485 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&ccu CLK_BUS_UART0>;
489 resets = <&ccu RST_BUS_UART0>;
490 dmas = <&dma 6>, <&dma 6>;
491 dma-names = "rx", "tx";
495 uart1: serial@1c28400 {
496 compatible = "snps,dw-apb-uart";
497 reg = <0x01c28400 0x400>;
498 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&ccu CLK_BUS_UART1>;
502 resets = <&ccu RST_BUS_UART1>;
503 dmas = <&dma 7>, <&dma 7>;
504 dma-names = "rx", "tx";
508 uart2: serial@1c28800 {
509 compatible = "snps,dw-apb-uart";
510 reg = <0x01c28800 0x400>;
511 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&ccu CLK_BUS_UART2>;
515 resets = <&ccu RST_BUS_UART2>;
516 dmas = <&dma 8>, <&dma 8>;
517 dma-names = "rx", "tx";
521 uart3: serial@1c28c00 {
522 compatible = "snps,dw-apb-uart";
523 reg = <0x01c28c00 0x400>;
524 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&ccu CLK_BUS_UART3>;
528 resets = <&ccu RST_BUS_UART3>;
529 dmas = <&dma 9>, <&dma 9>;
530 dma-names = "rx", "tx";
534 uart4: serial@1c29000 {
535 compatible = "snps,dw-apb-uart";
536 reg = <0x01c29000 0x400>;
537 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&ccu CLK_BUS_UART4>;
541 resets = <&ccu RST_BUS_UART4>;
542 dmas = <&dma 10>, <&dma 10>;
543 dma-names = "rx", "tx";
548 compatible = "allwinner,sun6i-a31-i2c";
549 reg = <0x01c2ac00 0x400>;
550 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&ccu CLK_BUS_I2C0>;
552 resets = <&ccu RST_BUS_I2C0>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c0_pins>;
556 #address-cells = <1>;
561 compatible = "allwinner,sun6i-a31-i2c";
562 reg = <0x01c2b000 0x400>;
563 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&ccu CLK_BUS_I2C1>;
565 resets = <&ccu RST_BUS_I2C1>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c1_pins>;
569 #address-cells = <1>;
574 compatible = "allwinner,sun6i-a31-i2c";
575 reg = <0x01c2b400 0x400>;
576 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&ccu CLK_BUS_I2C2>;
578 resets = <&ccu RST_BUS_I2C2>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c2_pins>;
582 #address-cells = <1>;
587 compatible = "allwinner,sun8i-a23-mali",
588 "allwinner,sun7i-a20-mali", "arm,mali-400";
589 reg = <0x01c40000 0x10000>;
590 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
597 interrupt-names = "gp",
604 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
605 clock-names = "bus", "core";
606 resets = <&ccu RST_BUS_GPU>;
607 #cooling-cells = <2>;
609 assigned-clocks = <&ccu CLK_GPU>;
610 assigned-clock-rates = <384000000>;
613 gic: interrupt-controller@1c81000 {
614 compatible = "arm,gic-400";
615 reg = <0x01c81000 0x1000>,
619 interrupt-controller;
620 #interrupt-cells = <3>;
621 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
624 fe0: display-frontend@1e00000 {
625 /* compatible gets set in SoC specific dtsi file */
626 reg = <0x01e00000 0x20000>;
627 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
629 <&ccu CLK_DRAM_DE_FE>;
630 clock-names = "ahb", "mod",
632 resets = <&ccu RST_BUS_DE_FE>;
635 #address-cells = <1>;
641 fe0_out_be0: endpoint {
642 remote-endpoint = <&be0_in_fe0>;
648 be0: display-backend@1e60000 {
649 /* compatible gets set in SoC specific dtsi file */
650 reg = <0x01e60000 0x10000>;
651 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
653 <&ccu CLK_DRAM_DE_BE>;
654 clock-names = "ahb", "mod",
656 resets = <&ccu RST_BUS_DE_BE>;
659 #address-cells = <1>;
665 be0_in_fe0: endpoint {
666 remote-endpoint = <&fe0_out_be0>;
673 be0_out_drc0: endpoint {
674 remote-endpoint = <&drc0_in_be0>;
681 /* compatible gets set in SoC specific dtsi file */
682 reg = <0x01e70000 0x10000>;
683 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
686 clock-names = "ahb", "mod", "ram";
687 resets = <&ccu RST_BUS_DRC>;
690 #address-cells = <1>;
696 drc0_in_be0: endpoint {
697 remote-endpoint = <&be0_out_drc0>;
704 drc0_out_tcon0: endpoint {
705 remote-endpoint = <&tcon0_in_drc0>;
712 compatible = "allwinner,sun8i-a23-rtc";
713 reg = <0x01f00000 0x400>;
714 interrupt-parent = <&r_intc>;
715 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
717 clock-output-names = "osc32k", "osc32k-out";
718 clocks = <&ext_osc32k>;
722 r_intc: interrupt-controller@1f00c00 {
723 compatible = "allwinner,sun6i-a31-r-intc";
724 interrupt-controller;
725 #interrupt-cells = <3>;
726 reg = <0x01f00c00 0x400>;
727 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
731 compatible = "allwinner,sun8i-a23-prcm";
732 reg = <0x01f01400 0x200>;
735 compatible = "fixed-factor-clock";
740 clock-output-names = "ar100";
744 compatible = "fixed-factor-clock";
749 clock-output-names = "ahb0";
753 compatible = "allwinner,sun8i-a23-apb0-clk";
756 clock-output-names = "apb0";
759 apb0_gates: apb0_gates_clk {
760 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
763 clock-output-names = "apb0_pio", "apb0_timer",
764 "apb0_rsb", "apb0_uart",
769 compatible = "allwinner,sun6i-a31-clock-reset";
773 codec_analog: codec-analog {
774 compatible = "allwinner,sun8i-a23-codec-analog";
779 compatible = "allwinner,sun8i-a23-cpuconfig";
780 reg = <0x01f01c00 0x300>;
783 r_uart: serial@1f02800 {
784 compatible = "snps,dw-apb-uart";
785 reg = <0x01f02800 0x400>;
786 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&apb0_gates 4>;
790 resets = <&apb0_rst 4>;
795 compatible = "allwinner,sun8i-a23-i2c",
796 "allwinner,sun6i-a31-i2c";
797 reg = <0x01f02400 0x400>;
798 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
799 pinctrl-names = "default";
800 pinctrl-0 = <&r_i2c_pins>;
801 clocks = <&apb0_gates 6>;
802 resets = <&apb0_rst 6>;
804 #address-cells = <1>;
808 r_pio: pinctrl@1f02c00 {
809 compatible = "allwinner,sun8i-a23-r-pinctrl";
810 reg = <0x01f02c00 0x400>;
811 interrupt-parent = <&r_intc>;
812 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
814 clock-names = "apb", "hosc", "losc";
815 resets = <&apb0_rst 0>;
817 interrupt-controller;
818 #interrupt-cells = <3>;
821 r_i2c_pins: r-i2c-pins {
827 r_rsb_pins: r-rsb-pins {
830 drive-strength = <20>;
834 r_uart_pins_a: r-uart-pins {
841 compatible = "allwinner,sun8i-a23-rsb";
842 reg = <0x01f03400 0x400>;
843 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&apb0_gates 3>;
845 clock-frequency = <3000000>;
846 resets = <&apb0_rst 3>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&r_rsb_pins>;
850 #address-cells = <1>;