arch/arm/boot/dts/sun8i-a23-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
  50 #include <dt-bindings/pinctrl/sun4i-a10.h>
  51 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
  52
  53 / {
  54         interrupt-parent = <&gic>;
  55
  56         chosen {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60
  61                 simplefb_lcd: framebuffer@0 {
  62                         compatible = "allwinner,simple-framebuffer",
  63                                      "simple-framebuffer";
  64                         allwinner,pipeline = "de_be0-lcd0";
  65                         clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
  66                                  <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
  67                                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
  68                         status = "disabled";
  69                 };
  70         };
  71
  72         timer {
  73                 compatible = "arm,armv7-timer";
  74                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  76                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  78                 clock-frequency = <24000000>;
  79                 arm,cpu-registers-not-fw-configured;
  80         };
  81
  82         cpus {
  83                 enable-method = "allwinner,sun8i-a23";
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86
  87                 cpu@0 {
  88                         compatible = "arm,cortex-a7";
  89                         device_type = "cpu";
  90                         reg = <0>;
  91                 };
  92
  93                 cpu@1 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <1>;
  97                 };
  98         };
  99
 100         clocks {
 101                 #address-cells = <1>;
 102                 #size-cells = <1>;
 103                 ranges;
 104
 105                 osc24M: osc24M_clk {
 106                         #clock-cells = <0>;
 107                         compatible = "fixed-clock";
 108                         clock-frequency = <24000000>;
 109                         clock-output-names = "osc24M";
 110                 };
 111
 112                 osc32k: osc32k_clk {
 113                         #clock-cells = <0>;
 114                         compatible = "fixed-clock";
 115                         clock-frequency = <32768>;
 116                         clock-output-names = "osc32k";
 117                 };
 118         };
 119
 120         soc@01c00000 {
 121                 compatible = "simple-bus";
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 ranges;
 125
 126                 dma: dma-controller@01c02000 {
 127                         compatible = "allwinner,sun8i-a23-dma";
 128                         reg = <0x01c02000 0x1000>;
 129                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 130                         clocks = <&ccu CLK_BUS_DMA>;
 131                         resets = <&ccu RST_BUS_DMA>;
 132                         #dma-cells = <1>;
 133                 };
 134
 135                 mmc0: mmc@01c0f000 {
 136                         compatible = "allwinner,sun7i-a20-mmc";
 137                         reg = <0x01c0f000 0x1000>;
 138                         clocks = <&ccu CLK_BUS_MMC0>,
 139                                  <&ccu CLK_MMC0>,
 140                                  <&ccu CLK_MMC0_OUTPUT>,
 141                                  <&ccu CLK_MMC0_SAMPLE>;
 142                         clock-names = "ahb",
 143                                       "mmc",
 144                                       "output",
 145                                       "sample";
 146                         resets = <&ccu RST_BUS_MMC0>;
 147                         reset-names = "ahb";
 148                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 149                         status = "disabled";
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152                 };
 153
 154                 mmc1: mmc@01c10000 {
 155                         compatible = "allwinner,sun7i-a20-mmc";
 156                         reg = <0x01c10000 0x1000>;
 157                         clocks = <&ccu CLK_BUS_MMC1>,
 158                                  <&ccu CLK_MMC1>,
 159                                  <&ccu CLK_MMC1_OUTPUT>,
 160                                  <&ccu CLK_MMC1_SAMPLE>;
 161                         clock-names = "ahb",
 162                                       "mmc",
 163                                       "output",
 164                                       "sample";
 165                         resets = <&ccu RST_BUS_MMC1>;
 166                         reset-names = "ahb";
 167                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 168                         status = "disabled";
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                 };
 172
 173                 mmc2: mmc@01c11000 {
 174                         compatible = "allwinner,sun7i-a20-mmc";
 175                         reg = <0x01c11000 0x1000>;
 176                         clocks = <&ccu CLK_BUS_MMC2>,
 177                                  <&ccu CLK_MMC2>,
 178                                  <&ccu CLK_MMC2_OUTPUT>,
 179                                  <&ccu CLK_MMC2_SAMPLE>;
 180                         clock-names = "ahb",
 181                                       "mmc",
 182                                       "output",
 183                                       "sample";
 184                         resets = <&ccu RST_BUS_MMC2>;
 185                         reset-names = "ahb";
 186                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 187                         status = "disabled";
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                 };
 191
 192                 nfc: nand@01c03000 {
 193                         compatible = "allwinner,sun4i-a10-nand";
 194                         reg = <0x01c03000 0x1000>;
 195                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 196                         clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
 197                         clock-names = "ahb", "mod";
 198                         resets = <&ccu RST_BUS_NAND>;
 199                         reset-names = "ahb";
 200                         status = "disabled";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                 };
 204
 205                 usb_otg: usb@01c19000 {
 206                         /* compatible gets set in SoC specific dtsi file */
 207                         reg = <0x01c19000 0x0400>;
 208                         clocks = <&ccu CLK_BUS_OTG>;
 209                         resets = <&ccu RST_BUS_OTG>;
 210                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 211                         interrupt-names = "mc";
 212                         phys = <&usbphy 0>;
 213                         phy-names = "usb";
 214                         extcon = <&usbphy 0>;
 215                         status = "disabled";
 216                 };
 217
 218                 usbphy: phy@01c19400 {
 219                         /*
 220                          * compatible and address regions get set in
 221                          * SoC specific dtsi file
 222                          */
 223                         clocks = <&ccu CLK_USB_PHY0>,
 224                                  <&ccu CLK_USB_PHY1>;
 225                         clock-names = "usb0_phy",
 226                                       "usb1_phy";
 227                         resets = <&ccu RST_USB_PHY0>,
 228                                  <&ccu RST_USB_PHY1>;
 229                         reset-names = "usb0_reset",
 230                                       "usb1_reset";
 231                         status = "disabled";
 232                         #phy-cells = <1>;
 233                 };
 234
 235                 ehci0: usb@01c1a000 {
 236                         compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
 237                         reg = <0x01c1a000 0x100>;
 238                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 239                         clocks = <&ccu CLK_BUS_EHCI>;
 240                         resets = <&ccu RST_BUS_EHCI>;
 241                         phys = <&usbphy 1>;
 242                         phy-names = "usb";
 243                         status = "disabled";
 244                 };
 245
 246                 ohci0: usb@01c1a400 {
 247                         compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
 248                         reg = <0x01c1a400 0x100>;
 249                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
 251                         resets = <&ccu RST_BUS_OHCI>;
 252                         phys = <&usbphy 1>;
 253                         phy-names = "usb";
 254                         status = "disabled";
 255                 };
 256
 257                 ccu: clock@01c20000 {
 258                         reg = <0x01c20000 0x400>;
 259                         clocks = <&osc24M>, <&osc32k>;
 260                         clock-names = "hosc", "losc";
 261                         #clock-cells = <1>;
 262                         #reset-cells = <1>;
 263                 };
 264
 265                 pio: pinctrl@01c20800 {
 266                         /* compatible gets set in SoC specific dtsi file */
 267                         reg = <0x01c20800 0x400>;
 268                         /* interrupts get set in SoC specific dtsi file */
 269                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 270                         clock-names = "apb", "hosc", "losc";
 271                         gpio-controller;
 272                         interrupt-controller;
 273                         #interrupt-cells = <3>;
 274                         #gpio-cells = <3>;
 275
 276                         uart0_pins_a: uart0@0 {
 277                                 allwinner,pins = "PF2", "PF4";
 278                                 allwinner,function = "uart0";
 279                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 280                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 281                         };
 282
 283                         uart1_pins_a: uart1@0 {
 284                                 allwinner,pins = "PG6", "PG7";
 285                                 allwinner,function = "uart1";
 286                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 287                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 288                         };
 289
 290                         uart1_pins_cts_rts_a: uart1-cts-rts@0 {
 291                                 allwinner,pins = "PG8", "PG9";
 292                                 allwinner,function = "uart1";
 293                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 294                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 295                         };
 296
 297                         mmc0_pins_a: mmc0@0 {
 298                                 allwinner,pins = "PF0", "PF1", "PF2",
 299                                                  "PF3", "PF4", "PF5";
 300                                 allwinner,function = "mmc0";
 301                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 302                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 303                         };
 304
 305                         mmc1_pins_a: mmc1@0 {
 306                                 allwinner,pins = "PG0", "PG1", "PG2",
 307                                                  "PG3", "PG4", "PG5";
 308                                 allwinner,function = "mmc1";
 309                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 310                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 311                         };
 312
 313                         mmc2_8bit_pins: mmc2_8bit {
 314                                 allwinner,pins = "PC5", "PC6", "PC8",
 315                                                  "PC9", "PC10", "PC11",
 316                                                  "PC12", "PC13", "PC14",
 317                                                  "PC15", "PC16";
 318                                 allwinner,function = "mmc2";
 319                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 320                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 321                         };
 322
 323                         pwm0_pins: pwm0 {
 324                                 allwinner,pins = "PH0";
 325                                 allwinner,function = "pwm0";
 326                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 327                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 328                         };
 329
 330                         i2c0_pins_a: i2c0@0 {
 331                                 allwinner,pins = "PH2", "PH3";
 332                                 allwinner,function = "i2c0";
 333                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 334                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 335                         };
 336
 337                         i2c1_pins_a: i2c1@0 {
 338                                 allwinner,pins = "PH4", "PH5";
 339                                 allwinner,function = "i2c1";
 340                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 341                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 342                         };
 343
 344                         i2c2_pins_a: i2c2@0 {
 345                                 allwinner,pins = "PE12", "PE13";
 346                                 allwinner,function = "i2c2";
 347                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 348                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 349                         };
 350
 351                         lcd_rgb666_pins: lcd-rgb666@0 {
 352                                 allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 353                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 354                                                  "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 355                                                  "PD24", "PD25", "PD26", "PD27";
 356                                 allwinner,function = "lcd0";
 357                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 358                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 359                         };
 360                 };
 361
 362                 timer@01c20c00 {
 363                         compatible = "allwinner,sun4i-a10-timer";
 364                         reg = <0x01c20c00 0xa0>;
 365                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&osc24M>;
 368                 };
 369
 370                 wdt0: watchdog@01c20ca0 {
 371                         compatible = "allwinner,sun6i-a31-wdt";
 372                         reg = <0x01c20ca0 0x20>;
 373                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 374                 };
 375
 376                 pwm: pwm@01c21400 {
 377                         compatible = "allwinner,sun7i-a20-pwm";
 378                         reg = <0x01c21400 0xc>;
 379                         clocks = <&osc24M>;
 380                         #pwm-cells = <3>;
 381                         status = "disabled";
 382                 };
 383
 384                 lradc: lradc@01c22800 {
 385                         compatible = "allwinner,sun4i-a10-lradc-keys";
 386                         reg = <0x01c22800 0x100>;
 387                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 388                         status = "disabled";
 389                 };
 390
 391                 uart0: serial@01c28000 {
 392                         compatible = "snps,dw-apb-uart";
 393                         reg = <0x01c28000 0x400>;
 394                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 395                         reg-shift = <2>;
 396                         reg-io-width = <4>;
 397                         clocks = <&ccu CLK_BUS_UART0>;
 398                         resets = <&ccu RST_BUS_UART0>;
 399                         dmas = <&dma 6>, <&dma 6>;
 400                         dma-names = "rx", "tx";
 401                         status = "disabled";
 402                 };
 403
 404                 uart1: serial@01c28400 {
 405                         compatible = "snps,dw-apb-uart";
 406                         reg = <0x01c28400 0x400>;
 407                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 408                         reg-shift = <2>;
 409                         reg-io-width = <4>;
 410                         clocks = <&ccu CLK_BUS_UART1>;
 411                         resets = <&ccu RST_BUS_UART1>;
 412                         dmas = <&dma 7>, <&dma 7>;
 413                         dma-names = "rx", "tx";
 414                         status = "disabled";
 415                 };
 416
 417                 uart2: serial@01c28800 {
 418                         compatible = "snps,dw-apb-uart";
 419                         reg = <0x01c28800 0x400>;
 420                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 421                         reg-shift = <2>;
 422                         reg-io-width = <4>;
 423                         clocks = <&ccu CLK_BUS_UART2>;
 424                         resets = <&ccu RST_BUS_UART2>;
 425                         dmas = <&dma 8>, <&dma 8>;
 426                         dma-names = "rx", "tx";
 427                         status = "disabled";
 428                 };
 429
 430                 uart3: serial@01c28c00 {
 431                         compatible = "snps,dw-apb-uart";
 432                         reg = <0x01c28c00 0x400>;
 433                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 434                         reg-shift = <2>;
 435                         reg-io-width = <4>;
 436                         clocks = <&ccu CLK_BUS_UART3>;
 437                         resets = <&ccu RST_BUS_UART3>;
 438                         dmas = <&dma 9>, <&dma 9>;
 439                         dma-names = "rx", "tx";
 440                         status = "disabled";
 441                 };
 442
 443                 uart4: serial@01c29000 {
 444                         compatible = "snps,dw-apb-uart";
 445                         reg = <0x01c29000 0x400>;
 446                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 447                         reg-shift = <2>;
 448                         reg-io-width = <4>;
 449                         clocks = <&ccu CLK_BUS_UART4>;
 450                         resets = <&ccu RST_BUS_UART4>;
 451                         dmas = <&dma 10>, <&dma 10>;
 452                         dma-names = "rx", "tx";
 453                         status = "disabled";
 454                 };
 455
 456                 i2c0: i2c@01c2ac00 {
 457                         compatible = "allwinner,sun6i-a31-i2c";
 458                         reg = <0x01c2ac00 0x400>;
 459                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&ccu CLK_BUS_I2C0>;
 461                         resets = <&ccu RST_BUS_I2C0>;
 462                         status = "disabled";
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                 };
 466
 467                 i2c1: i2c@01c2b000 {
 468                         compatible = "allwinner,sun6i-a31-i2c";
 469                         reg = <0x01c2b000 0x400>;
 470                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&ccu CLK_BUS_I2C1>;
 472                         resets = <&ccu RST_BUS_I2C1>;
 473                         status = "disabled";
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                 };
 477
 478                 i2c2: i2c@01c2b400 {
 479                         compatible = "allwinner,sun6i-a31-i2c";
 480                         reg = <0x01c2b400 0x400>;
 481                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&ccu CLK_BUS_I2C2>;
 483                         resets = <&ccu RST_BUS_I2C2>;
 484                         status = "disabled";
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                 };
 488
 489                 gic: interrupt-controller@01c81000 {
 490                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 491                         reg = <0x01c81000 0x1000>,
 492                               <0x01c82000 0x1000>,
 493                               <0x01c84000 0x2000>,
 494                               <0x01c86000 0x2000>;
 495                         interrupt-controller;
 496                         #interrupt-cells = <3>;
 497                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 498                 };
 499
 500                 rtc: rtc@01f00000 {
 501                         compatible = "allwinner,sun6i-a31-rtc";
 502                         reg = <0x01f00000 0x54>;
 503                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 504                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 505                 };
 506
 507                 nmi_intc: interrupt-controller@01f00c0c {
 508                         compatible = "allwinner,sun6i-a31-sc-nmi";
 509                         interrupt-controller;
 510                         #interrupt-cells = <2>;
 511                         reg = <0x01f00c0c 0x38>;
 512                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 513                 };
 514
 515                 prcm@01f01400 {
 516                         compatible = "allwinner,sun8i-a23-prcm";
 517                         reg = <0x01f01400 0x200>;
 518
 519                         ar100: ar100_clk {
 520                                 compatible = "fixed-factor-clock";
 521                                 #clock-cells = <0>;
 522                                 clock-div = <1>;
 523                                 clock-mult = <1>;
 524                                 clocks = <&osc24M>;
 525                                 clock-output-names = "ar100";
 526                         };
 527
 528                         ahb0: ahb0_clk {
 529                                 compatible = "fixed-factor-clock";
 530                                 #clock-cells = <0>;
 531                                 clock-div = <1>;
 532                                 clock-mult = <1>;
 533                                 clocks = <&ar100>;
 534                                 clock-output-names = "ahb0";
 535                         };
 536
 537                         apb0: apb0_clk {
 538                                 compatible = "allwinner,sun8i-a23-apb0-clk";
 539                                 #clock-cells = <0>;
 540                                 clocks = <&ahb0>;
 541                                 clock-output-names = "apb0";
 542                         };
 543
 544                         apb0_gates: apb0_gates_clk {
 545                                 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
 546                                 #clock-cells = <1>;
 547                                 clocks = <&apb0>;
 548                                 clock-output-names = "apb0_pio", "apb0_timer",
 549                                                 "apb0_rsb", "apb0_uart",
 550                                                 "apb0_i2c";
 551                         };
 552
 553                         apb0_rst: apb0_rst {
 554                                 compatible = "allwinner,sun6i-a31-clock-reset";
 555                                 #reset-cells = <1>;
 556                         };
 557                 };
 558
 559                 cpucfg@01f01c00 {
 560                         compatible = "allwinner,sun8i-a23-cpuconfig";
 561                         reg = <0x01f01c00 0x300>;
 562                 };
 563
 564                 r_uart: serial@01f02800 {
 565                         compatible = "snps,dw-apb-uart";
 566                         reg = <0x01f02800 0x400>;
 567                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 568                         reg-shift = <2>;
 569                         reg-io-width = <4>;
 570                         clocks = <&apb0_gates 4>;
 571                         resets = <&apb0_rst 4>;
 572                         status = "disabled";
 573                 };
 574
 575                 r_pio: pinctrl@01f02c00 {
 576                         compatible = "allwinner,sun8i-a23-r-pinctrl";
 577                         reg = <0x01f02c00 0x400>;
 578                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 579                         clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
 580                         clock-names = "apb", "hosc", "losc";
 581                         resets = <&apb0_rst 0>;
 582                         gpio-controller;
 583                         interrupt-controller;
 584                         #interrupt-cells = <3>;
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         #gpio-cells = <3>;
 588
 589                         r_rsb_pins: r_rsb {
 590                                 allwinner,pins = "PL0", "PL1";
 591                                 allwinner,function = "s_rsb";
 592                                 allwinner,drive = <SUN4I_PINCTRL_20_MA>;
 593                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 594                         };
 595
 596                         r_uart_pins_a: r_uart@0 {
 597                                 allwinner,pins = "PL2", "PL3";
 598                                 allwinner,function = "s_uart";
 599                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 600                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 601                         };
 602                 };
 603
 604                 r_rsb: rsb@01f03400 {
 605                         compatible = "allwinner,sun8i-a23-rsb";
 606                         reg = <0x01f03400 0x400>;
 607                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&apb0_gates 3>;
 609                         clock-frequency = <3000000>;
 610                         resets = <&apb0_rst 3>;
 611                         pinctrl-names = "default";
 612                         pinctrl-0 = <&r_rsb_pins>;
 613                         status = "disabled";
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                 };
 617         };
 618 };