arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/dma/sun4i-a10.h>
  48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
  49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  50 #include <dt-bindings/pinctrl/sun4i-a10.h>
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54         #address-cells = <1>;
  55         #size-cells = <1>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59         };
  60
  61         chosen {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 framebuffer-lcd0-hdmi {
  67                         compatible = "allwinner,simple-framebuffer",
  68                                      "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  71                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  72                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
  73                                  <&ccu CLK_HDMI>;
  74                         status = "disabled";
  75                 };
  76
  77                 framebuffer-lcd0 {
  78                         compatible = "allwinner,simple-framebuffer",
  79                                      "simple-framebuffer";
  80                         allwinner,pipeline = "de_be0-lcd0";
  81                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  82                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
  83                                  <&ccu CLK_DRAM_DE_BE0>;
  84                         status = "disabled";
  85                 };
  86
  87                 framebuffer-lcd0-tve0 {
  88                         compatible = "allwinner,simple-framebuffer",
  89                                      "simple-framebuffer";
  90                         allwinner,pipeline = "de_be0-lcd0-tve0";
  91                         clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
  92                                  <&ccu CLK_AHB_DE_BE0>,
  93                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
  94                                  <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
  95                         status = "disabled";
  96                 };
  97         };
  98
  99         cpus {
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102
 103                 cpu0: cpu@0 {
 104                         compatible = "arm,cortex-a7";
 105                         device_type = "cpu";
 106                         reg = <0>;
 107                         clocks = <&ccu CLK_CPU>;
 108                         clock-latency = <244144>; /* 8 32k periods */
 109                         operating-points =
 110                                 /* kHz    uV */
 111                                 <960000 1400000>,
 112                                 <912000 1400000>,
 113                                 <864000 1300000>,
 114                                 <720000 1200000>,
 115                                 <528000 1100000>,
 116                                 <312000 1000000>,
 117                                 <144000 1000000>;
 118                         #cooling-cells = <2>;
 119                 };
 120
 121                 cpu1: cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                         clocks = <&ccu CLK_CPU>;
 126                         clock-latency = <244144>; /* 8 32k periods */
 127                         operating-points =
 128                                 /* kHz    uV */
 129                                 <960000 1400000>,
 130                                 <912000 1400000>,
 131                                 <864000 1300000>,
 132                                 <720000 1200000>,
 133                                 <528000 1100000>,
 134                                 <312000 1000000>,
 135                                 <144000 1000000>;
 136                         #cooling-cells = <2>;
 137                 };
 138         };
 139
 140         thermal-zones {
 141                 cpu-thermal {
 142                         /* milliseconds */
 143                         polling-delay-passive = <250>;
 144                         polling-delay = <1000>;
 145                         thermal-sensors = <&rtp>;
 146
 147                         cooling-maps {
 148                                 map0 {
 149                                         trip = <&cpu_alert0>;
 150                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 151                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 152                                 };
 153                         };
 154
 155                         trips {
 156                                 cpu_alert0: cpu_alert0 {
 157                                         /* milliCelsius */
 158                                         temperature = <75000>;
 159                                         hysteresis = <2000>;
 160                                         type = "passive";
 161                                 };
 162
 163                                 cpu_crit: cpu_crit {
 164                                         /* milliCelsius */
 165                                         temperature = <100000>;
 166                                         hysteresis = <2000>;
 167                                         type = "critical";
 168                                 };
 169                         };
 170                 };
 171         };
 172
 173         reserved-memory {
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 ranges;
 177
 178                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 179                 default-pool {
 180                         compatible = "shared-dma-pool";
 181                         size = <0x6000000>;
 182                         alloc-ranges = <0x40000000 0x10000000>;
 183                         reusable;
 184                         linux,cma-default;
 185                 };
 186         };
 187
 188         timer {
 189                 compatible = "arm,armv7-timer";
 190                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 191                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 193                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 194         };
 195
 196         pmu {
 197                 compatible = "arm,cortex-a7-pmu";
 198                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 200         };
 201
 202         clocks {
 203                 #address-cells = <1>;
 204                 #size-cells = <1>;
 205                 ranges;
 206
 207                 osc24M: clk-24M {
 208                         #clock-cells = <0>;
 209                         compatible = "fixed-clock";
 210                         clock-frequency = <24000000>;
 211                         clock-output-names = "osc24M";
 212                 };
 213
 214                 osc32k: clk-32k {
 215                         #clock-cells = <0>;
 216                         compatible = "fixed-clock";
 217                         clock-frequency = <32768>;
 218                         clock-output-names = "osc32k";
 219                 };
 220
 221                 /*
 222                  * The following two are dummy clocks, placeholders
 223                  * used in the gmac_tx clock. The gmac driver will
 224                  * choose one parent depending on the PHY interface
 225                  * mode, using clk_set_rate auto-reparenting.
 226                  *
 227                  * The actual TX clock rate is not controlled by the
 228                  * gmac_tx clock.
 229                  */
 230                 mii_phy_tx_clk: clk-mii-phy-tx {
 231                         #clock-cells = <0>;
 232                         compatible = "fixed-clock";
 233                         clock-frequency = <25000000>;
 234                         clock-output-names = "mii_phy_tx";
 235                 };
 236
 237                 gmac_int_tx_clk: clk-gmac-int-tx {
 238                         #clock-cells = <0>;
 239                         compatible = "fixed-clock";
 240                         clock-frequency = <125000000>;
 241                         clock-output-names = "gmac_int_tx";
 242                 };
 243
 244                 gmac_tx_clk: clk@1c20164 {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun7i-a20-gmac-clk";
 247                         reg = <0x01c20164 0x4>;
 248                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 249                         clock-output-names = "gmac_tx";
 250                 };
 251         };
 252
 253
 254         de: display-engine {
 255                 compatible = "allwinner,sun7i-a20-display-engine";
 256                 allwinner,pipelines = <&fe0>, <&fe1>;
 257                 status = "disabled";
 258         };
 259
 260         soc {
 261                 compatible = "simple-bus";
 262                 #address-cells = <1>;
 263                 #size-cells = <1>;
 264                 ranges;
 265
 266                 system-control@1c00000 {
 267                         compatible = "allwinner,sun7i-a20-system-control",
 268                                      "allwinner,sun4i-a10-system-control";
 269                         reg = <0x01c00000 0x30>;
 270                         #address-cells = <1>;
 271                         #size-cells = <1>;
 272                         ranges;
 273
 274                         sram_a: sram@0 {
 275                                 compatible = "mmio-sram";
 276                                 reg = <0x00000000 0xc000>;
 277                                 #address-cells = <1>;
 278                                 #size-cells = <1>;
 279                                 ranges = <0 0x00000000 0xc000>;
 280
 281                                 emac_sram: sram-section@8000 {
 282                                         compatible = "allwinner,sun7i-a20-sram-a3-a4",
 283                                                      "allwinner,sun4i-a10-sram-a3-a4";
 284                                         reg = <0x8000 0x4000>;
 285                                         status = "disabled";
 286                                 };
 287                         };
 288
 289                         sram_d: sram@10000 {
 290                                 compatible = "mmio-sram";
 291                                 reg = <0x00010000 0x1000>;
 292                                 #address-cells = <1>;
 293                                 #size-cells = <1>;
 294                                 ranges = <0 0x00010000 0x1000>;
 295
 296                                 otg_sram: sram-section@0 {
 297                                         compatible = "allwinner,sun7i-a20-sram-d",
 298                                                      "allwinner,sun4i-a10-sram-d";
 299                                         reg = <0x0000 0x1000>;
 300                                         status = "disabled";
 301                                 };
 302                         };
 303
 304                         sram_c: sram@1d00000 {
 305                                 compatible = "mmio-sram";
 306                                 reg = <0x01d00000 0xd0000>;
 307                                 #address-cells = <1>;
 308                                 #size-cells = <1>;
 309                                 ranges = <0 0x01d00000 0xd0000>;
 310
 311                                 ve_sram: sram-section@0 {
 312                                         compatible = "allwinner,sun7i-a20-sram-c1",
 313                                                      "allwinner,sun4i-a10-sram-c1";
 314                                         reg = <0x000000 0x80000>;
 315                                 };
 316                         };
 317                 };
 318
 319                 nmi_intc: interrupt-controller@1c00030 {
 320                         compatible = "allwinner,sun7i-a20-sc-nmi";
 321                         interrupt-controller;
 322                         #interrupt-cells = <2>;
 323                         reg = <0x01c00030 0x0c>;
 324                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 325                 };
 326
 327                 dma: dma-controller@1c02000 {
 328                         compatible = "allwinner,sun4i-a10-dma";
 329                         reg = <0x01c02000 0x1000>;
 330                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&ccu CLK_AHB_DMA>;
 332                         #dma-cells = <2>;
 333                 };
 334
 335                 nfc: nand-controller@1c03000 {
 336                         compatible = "allwinner,sun4i-a10-nand";
 337                         reg = <0x01c03000 0x1000>;
 338                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 339                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 340                         clock-names = "ahb", "mod";
 341                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 342                         dma-names = "rxtx";
 343                         status = "disabled";
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                 };
 347
 348                 spi0: spi@1c05000 {
 349                         compatible = "allwinner,sun4i-a10-spi";
 350                         reg = <0x01c05000 0x1000>;
 351                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 352                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 353                         clock-names = "ahb", "mod";
 354                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 355                                <&dma SUN4I_DMA_DEDICATED 26>;
 356                         dma-names = "rx", "tx";
 357                         status = "disabled";
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         num-cs = <4>;
 361                 };
 362
 363                 spi1: spi@1c06000 {
 364                         compatible = "allwinner,sun4i-a10-spi";
 365                         reg = <0x01c06000 0x1000>;
 366                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 368                         clock-names = "ahb", "mod";
 369                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 370                                <&dma SUN4I_DMA_DEDICATED 8>;
 371                         dma-names = "rx", "tx";
 372                         status = "disabled";
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         num-cs = <1>;
 376                 };
 377
 378                 csi0: csi@1c09000 {
 379                         compatible = "allwinner,sun7i-a20-csi0";
 380                         reg = <0x01c09000 0x1000>;
 381                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
 383                         clock-names = "bus", "isp", "ram";
 384                         resets = <&ccu RST_CSI0>;
 385                         status = "disabled";
 386                 };
 387
 388                 emac: ethernet@1c0b000 {
 389                         compatible = "allwinner,sun4i-a10-emac";
 390                         reg = <0x01c0b000 0x1000>;
 391                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 392                         clocks = <&ccu CLK_AHB_EMAC>;
 393                         allwinner,sram = <&emac_sram 1>;
 394                         status = "disabled";
 395                 };
 396
 397                 mdio: mdio@1c0b080 {
 398                         compatible = "allwinner,sun4i-a10-mdio";
 399                         reg = <0x01c0b080 0x14>;
 400                         status = "disabled";
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                 };
 404
 405                 tcon0: lcd-controller@1c0c000 {
 406                         compatible = "allwinner,sun7i-a20-tcon0",
 407                                      "allwinner,sun7i-a20-tcon";
 408                         reg = <0x01c0c000 0x1000>;
 409                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 410                         resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
 411                         reset-names = "lcd", "lvds";
 412                         clocks = <&ccu CLK_AHB_LCD0>,
 413                                  <&ccu CLK_TCON0_CH0>,
 414                                  <&ccu CLK_TCON0_CH1>;
 415                         clock-names = "ahb",
 416                                       "tcon-ch0",
 417                                       "tcon-ch1";
 418                         clock-output-names = "tcon0-pixel-clock";
 419                         #clock-cells = <0>;
 420                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 421
 422                         ports {
 423                                 #address-cells = <1>;
 424                                 #size-cells = <0>;
 425
 426                                 tcon0_in: port@0 {
 427                                         #address-cells = <1>;
 428                                         #size-cells = <0>;
 429                                         reg = <0>;
 430
 431                                         tcon0_in_be0: endpoint@0 {
 432                                                 reg = <0>;
 433                                                 remote-endpoint = <&be0_out_tcon0>;
 434                                         };
 435
 436                                         tcon0_in_be1: endpoint@1 {
 437                                                 reg = <1>;
 438                                                 remote-endpoint = <&be1_out_tcon0>;
 439                                         };
 440                                 };
 441
 442                                 tcon0_out: port@1 {
 443                                         #address-cells = <1>;
 444                                         #size-cells = <0>;
 445                                         reg = <1>;
 446
 447                                         tcon0_out_hdmi: endpoint@1 {
 448                                                 reg = <1>;
 449                                                 remote-endpoint = <&hdmi_in_tcon0>;
 450                                                 allwinner,tcon-channel = <1>;
 451                                         };
 452                                 };
 453                         };
 454                 };
 455
 456                 tcon1: lcd-controller@1c0d000 {
 457                         compatible = "allwinner,sun7i-a20-tcon1",
 458                                      "allwinner,sun7i-a20-tcon";
 459                         reg = <0x01c0d000 0x1000>;
 460                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 461                         resets = <&ccu RST_TCON1>;
 462                         reset-names = "lcd";
 463                         clocks = <&ccu CLK_AHB_LCD1>,
 464                                  <&ccu CLK_TCON1_CH0>,
 465                                  <&ccu CLK_TCON1_CH1>;
 466                         clock-names = "ahb",
 467                                       "tcon-ch0",
 468                                       "tcon-ch1";
 469                         clock-output-names = "tcon1-pixel-clock";
 470                         #clock-cells = <0>;
 471                         dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 472
 473                         ports {
 474                                 #address-cells = <1>;
 475                                 #size-cells = <0>;
 476
 477                                 tcon1_in: port@0 {
 478                                         #address-cells = <1>;
 479                                         #size-cells = <0>;
 480                                         reg = <0>;
 481
 482                                         tcon1_in_be0: endpoint@0 {
 483                                                 reg = <0>;
 484                                                 remote-endpoint = <&be0_out_tcon1>;
 485                                         };
 486
 487                                         tcon1_in_be1: endpoint@1 {
 488                                                 reg = <1>;
 489                                                 remote-endpoint = <&be1_out_tcon1>;
 490                                         };
 491                                 };
 492
 493                                 tcon1_out: port@1 {
 494                                         #address-cells = <1>;
 495                                         #size-cells = <0>;
 496                                         reg = <1>;
 497
 498                                         tcon1_out_hdmi: endpoint@1 {
 499                                                 reg = <1>;
 500                                                 remote-endpoint = <&hdmi_in_tcon1>;
 501                                                 allwinner,tcon-channel = <1>;
 502                                         };
 503                                 };
 504                         };
 505                 };
 506
 507                 video-codec@1c0e000 {
 508                         compatible = "allwinner,sun7i-a20-video-engine";
 509                         reg = <0x01c0e000 0x1000>;
 510                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 511                                  <&ccu CLK_DRAM_VE>;
 512                         clock-names = "ahb", "mod", "ram";
 513                         resets = <&ccu RST_VE>;
 514                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 515                         allwinner,sram = <&ve_sram 1>;
 516                 };
 517
 518                 mmc0: mmc@1c0f000 {
 519                         compatible = "allwinner,sun7i-a20-mmc";
 520                         reg = <0x01c0f000 0x1000>;
 521                         clocks = <&ccu CLK_AHB_MMC0>,
 522                                  <&ccu CLK_MMC0>,
 523                                  <&ccu CLK_MMC0_OUTPUT>,
 524                                  <&ccu CLK_MMC0_SAMPLE>;
 525                         clock-names = "ahb",
 526                                       "mmc",
 527                                       "output",
 528                                       "sample";
 529                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 530                         pinctrl-names = "default";
 531                         pinctrl-0 = <&mmc0_pins>;
 532                         status = "disabled";
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                 };
 536
 537                 mmc1: mmc@1c10000 {
 538                         compatible = "allwinner,sun7i-a20-mmc";
 539                         reg = <0x01c10000 0x1000>;
 540                         clocks = <&ccu CLK_AHB_MMC1>,
 541                                  <&ccu CLK_MMC1>,
 542                                  <&ccu CLK_MMC1_OUTPUT>,
 543                                  <&ccu CLK_MMC1_SAMPLE>;
 544                         clock-names = "ahb",
 545                                       "mmc",
 546                                       "output",
 547                                       "sample";
 548                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 549                         status = "disabled";
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                 };
 553
 554                 mmc2: mmc@1c11000 {
 555                         compatible = "allwinner,sun7i-a20-mmc";
 556                         reg = <0x01c11000 0x1000>;
 557                         clocks = <&ccu CLK_AHB_MMC2>,
 558                                  <&ccu CLK_MMC2>,
 559                                  <&ccu CLK_MMC2_OUTPUT>,
 560                                  <&ccu CLK_MMC2_SAMPLE>;
 561                         clock-names = "ahb",
 562                                       "mmc",
 563                                       "output",
 564                                       "sample";
 565                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 566                         pinctrl-names = "default";
 567                         pinctrl-0 = <&mmc2_pins>;
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 mmc3: mmc@1c12000 {
 574                         compatible = "allwinner,sun7i-a20-mmc";
 575                         reg = <0x01c12000 0x1000>;
 576                         clocks = <&ccu CLK_AHB_MMC3>,
 577                                  <&ccu CLK_MMC3>,
 578                                  <&ccu CLK_MMC3_OUTPUT>,
 579                                  <&ccu CLK_MMC3_SAMPLE>;
 580                         clock-names = "ahb",
 581                                       "mmc",
 582                                       "output",
 583                                       "sample";
 584                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 585                         pinctrl-names = "default";
 586                         pinctrl-0 = <&mmc3_pins>;
 587                         status = "disabled";
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                 };
 591
 592                 usb_otg: usb@1c13000 {
 593                         compatible = "allwinner,sun4i-a10-musb";
 594                         reg = <0x01c13000 0x0400>;
 595                         clocks = <&ccu CLK_AHB_OTG>;
 596                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 597                         interrupt-names = "mc";
 598                         phys = <&usbphy 0>;
 599                         phy-names = "usb";
 600                         extcon = <&usbphy 0>;
 601                         allwinner,sram = <&otg_sram 1>;
 602                         dr_mode = "otg";
 603                         status = "disabled";
 604                 };
 605
 606                 usbphy: phy@1c13400 {
 607                         #phy-cells = <1>;
 608                         compatible = "allwinner,sun7i-a20-usb-phy";
 609                         reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 610                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 611                         clocks = <&ccu CLK_USB_PHY>;
 612                         clock-names = "usb_phy";
 613                         resets = <&ccu RST_USB_PHY0>,
 614                                  <&ccu RST_USB_PHY1>,
 615                                  <&ccu RST_USB_PHY2>;
 616                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 617                         status = "disabled";
 618                 };
 619
 620                 ehci0: usb@1c14000 {
 621                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 622                         reg = <0x01c14000 0x100>;
 623                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 624                         clocks = <&ccu CLK_AHB_EHCI0>;
 625                         phys = <&usbphy 1>;
 626                         phy-names = "usb";
 627                         status = "disabled";
 628                 };
 629
 630                 ohci0: usb@1c14400 {
 631                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 632                         reg = <0x01c14400 0x100>;
 633                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 634                         clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 635                         phys = <&usbphy 1>;
 636                         phy-names = "usb";
 637                         status = "disabled";
 638                 };
 639
 640                 crypto: crypto-engine@1c15000 {
 641                         compatible = "allwinner,sun7i-a20-crypto",
 642                                      "allwinner,sun4i-a10-crypto";
 643                         reg = <0x01c15000 0x1000>;
 644                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 646                         clock-names = "ahb", "mod";
 647                 };
 648
 649                 hdmi: hdmi@1c16000 {
 650                         compatible = "allwinner,sun7i-a20-hdmi",
 651                                      "allwinner,sun5i-a10s-hdmi";
 652                         reg = <0x01c16000 0x1000>;
 653                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 654                         clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 655                                  <&ccu CLK_PLL_VIDEO0_2X>,
 656                                  <&ccu CLK_PLL_VIDEO1_2X>;
 657                         clock-names = "ahb", "mod", "pll-0", "pll-1";
 658                         dmas = <&dma SUN4I_DMA_NORMAL 16>,
 659                                <&dma SUN4I_DMA_NORMAL 16>,
 660                                <&dma SUN4I_DMA_DEDICATED 24>;
 661                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 662                         status = "disabled";
 663
 664                         ports {
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667
 668                                 hdmi_in: port@0 {
 669                                         #address-cells = <1>;
 670                                         #size-cells = <0>;
 671                                         reg = <0>;
 672
 673                                         hdmi_in_tcon0: endpoint@0 {
 674                                                 reg = <0>;
 675                                                 remote-endpoint = <&tcon0_out_hdmi>;
 676                                         };
 677
 678                                         hdmi_in_tcon1: endpoint@1 {
 679                                                 reg = <1>;
 680                                                 remote-endpoint = <&tcon1_out_hdmi>;
 681                                         };
 682                                 };
 683
 684                                 hdmi_out: port@1 {
 685                                         reg = <1>;
 686                                 };
 687                         };
 688                 };
 689
 690                 spi2: spi@1c17000 {
 691                         compatible = "allwinner,sun4i-a10-spi";
 692                         reg = <0x01c17000 0x1000>;
 693                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 694                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 695                         clock-names = "ahb", "mod";
 696                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 697                                <&dma SUN4I_DMA_DEDICATED 28>;
 698                         dma-names = "rx", "tx";
 699                         status = "disabled";
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                         num-cs = <1>;
 703                 };
 704
 705                 ahci: sata@1c18000 {
 706                         compatible = "allwinner,sun4i-a10-ahci";
 707                         reg = <0x01c18000 0x1000>;
 708                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 710                         status = "disabled";
 711                 };
 712
 713                 ehci1: usb@1c1c000 {
 714                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 715                         reg = <0x01c1c000 0x100>;
 716                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 717                         clocks = <&ccu CLK_AHB_EHCI1>;
 718                         phys = <&usbphy 2>;
 719                         phy-names = "usb";
 720                         status = "disabled";
 721                 };
 722
 723                 ohci1: usb@1c1c400 {
 724                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 725                         reg = <0x01c1c400 0x100>;
 726                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 727                         clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 728                         phys = <&usbphy 2>;
 729                         phy-names = "usb";
 730                         status = "disabled";
 731                 };
 732
 733                 csi1: csi@1c1d000 {
 734                         compatible = "allwinner,sun7i-a20-csi1",
 735                                      "allwinner,sun4i-a10-csi1";
 736                         reg = <0x01c1d000 0x1000>;
 737                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 738                         clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
 739                         clock-names = "bus", "ram";
 740                         resets = <&ccu RST_CSI1>;
 741                         status = "disabled";
 742                 };
 743
 744                 spi3: spi@1c1f000 {
 745                         compatible = "allwinner,sun4i-a10-spi";
 746                         reg = <0x01c1f000 0x1000>;
 747                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 749                         clock-names = "ahb", "mod";
 750                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 751                                <&dma SUN4I_DMA_DEDICATED 30>;
 752                         dma-names = "rx", "tx";
 753                         status = "disabled";
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         num-cs = <1>;
 757                 };
 758
 759                 ccu: clock@1c20000 {
 760                         compatible = "allwinner,sun7i-a20-ccu";
 761                         reg = <0x01c20000 0x400>;
 762                         clocks = <&osc24M>, <&osc32k>;
 763                         clock-names = "hosc", "losc";
 764                         #clock-cells = <1>;
 765                         #reset-cells = <1>;
 766                 };
 767
 768                 pio: pinctrl@1c20800 {
 769                         compatible = "allwinner,sun7i-a20-pinctrl";
 770                         reg = <0x01c20800 0x400>;
 771                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 772                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 773                         clock-names = "apb", "hosc", "losc";
 774                         gpio-controller;
 775                         interrupt-controller;
 776                         #interrupt-cells = <3>;
 777                         #gpio-cells = <3>;
 778
 779                         /omit-if-no-ref/
 780                         can_pa_pins: can-pa-pins {
 781                                 pins = "PA16", "PA17";
 782                                 function = "can";
 783                         };
 784
 785                         /omit-if-no-ref/
 786                         can_ph_pins: can-ph-pins {
 787                                 pins = "PH20", "PH21";
 788                                 function = "can";
 789                         };
 790
 791                         /omit-if-no-ref/
 792                         clk_out_a_pin: clk-out-a-pin {
 793                                 pins = "PI12";
 794                                 function = "clk_out_a";
 795                         };
 796
 797                         /omit-if-no-ref/
 798                         clk_out_b_pin: clk-out-b-pin {
 799                                 pins = "PI13";
 800                                 function = "clk_out_b";
 801                         };
 802
 803                         /omit-if-no-ref/
 804                         csi0_8bits_pins: csi-8bits-pins {
 805                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 806                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 807                                        "PE11";
 808                                 function = "csi0";
 809                         };
 810
 811                         /omit-if-no-ref/
 812                         csi0_clk_pin: csi-clk-pin {
 813                                 pins = "PE1";
 814                                 function = "csi0";
 815                         };
 816
 817                         /omit-if-no-ref/
 818                         csi1_8bits_pg_pins: csi1-8bits-pg-pins {
 819                                 pins = "PG0", "PG2", "PG3", "PG4", "PG5",
 820                                        "PG6", "PG7", "PG8", "PG9", "PG10",
 821                                        "PG11";
 822                                 function = "csi1";
 823                         };
 824
 825                         /omit-if-no-ref/
 826                         csi1_24bits_ph_pins: csi1-24bits-ph-pins {
 827                                 pins = "PH0", "PH1", "PH2", "PH3", "PH4",
 828                                        "PH5", "PH6", "PH7", "PH8", "PH9",
 829                                        "PH10", "PH11", "PH12", "PH13", "PH14",
 830                                        "PH15", "PH16", "PH17", "PH18", "PH19",
 831                                        "PH20", "PH21", "PH22", "PH23", "PH24",
 832                                        "PH25", "PH26", "PH27";
 833                                 function = "csi1";
 834                         };
 835
 836                         /omit-if-no-ref/
 837                         csi1_clk_pg_pin: csi1-clk-pg-pin {
 838                                 pins = "PG1";
 839                                 function = "csi1";
 840                         };
 841
 842                         /omit-if-no-ref/
 843                         emac_pa_pins: emac-pa-pins {
 844                                 pins = "PA0", "PA1", "PA2",
 845                                        "PA3", "PA4", "PA5", "PA6",
 846                                        "PA7", "PA8", "PA9", "PA10",
 847                                        "PA11", "PA12", "PA13", "PA14",
 848                                        "PA15", "PA16";
 849                                 function = "emac";
 850                         };
 851
 852                         /omit-if-no-ref/
 853                         emac_ph_pins: emac-ph-pins {
 854                                 pins = "PH8", "PH9", "PH10", "PH11",
 855                                        "PH14", "PH15", "PH16", "PH17",
 856                                        "PH18", "PH19", "PH20", "PH21",
 857                                        "PH22", "PH23", "PH24", "PH25",
 858                                        "PH26";
 859                                 function = "emac";
 860                         };
 861
 862                         /omit-if-no-ref/
 863                         gmac_mii_pins: gmac-mii-pins {
 864                                 pins = "PA0", "PA1", "PA2",
 865                                        "PA3", "PA4", "PA5", "PA6",
 866                                        "PA7", "PA8", "PA9", "PA10",
 867                                        "PA11", "PA12", "PA13", "PA14",
 868                                        "PA15", "PA16";
 869                                 function = "gmac";
 870                         };
 871
 872                         /omit-if-no-ref/
 873                         gmac_rgmii_pins: gmac-rgmii-pins {
 874                                 pins = "PA0", "PA1", "PA2",
 875                                        "PA3", "PA4", "PA5", "PA6",
 876                                         "PA7", "PA8", "PA10",
 877                                        "PA11", "PA12", "PA13",
 878                                        "PA15", "PA16";
 879                                 function = "gmac";
 880                                 /*
 881                                  * data lines in RGMII mode use DDR mode
 882                                  * and need a higher signal drive strength
 883                                  */
 884                                 drive-strength = <40>;
 885                         };
 886
 887                         /omit-if-no-ref/
 888                         i2c0_pins: i2c0-pins {
 889                                 pins = "PB0", "PB1";
 890                                 function = "i2c0";
 891                         };
 892
 893                         /omit-if-no-ref/
 894                         i2c1_pins: i2c1-pins {
 895                                 pins = "PB18", "PB19";
 896                                 function = "i2c1";
 897                         };
 898
 899                         /omit-if-no-ref/
 900                         i2c2_pins: i2c2-pins {
 901                                 pins = "PB20", "PB21";
 902                                 function = "i2c2";
 903                         };
 904
 905                         /omit-if-no-ref/
 906                         i2c3_pins: i2c3-pins {
 907                                 pins = "PI0", "PI1";
 908                                 function = "i2c3";
 909                         };
 910
 911                         /omit-if-no-ref/
 912                         ir0_rx_pin: ir0-rx-pin {
 913                                 pins = "PB4";
 914                                 function = "ir0";
 915                         };
 916
 917                         /omit-if-no-ref/
 918                         ir0_tx_pin: ir0-tx-pin {
 919                                 pins = "PB3";
 920                                 function = "ir0";
 921                         };
 922
 923                         /omit-if-no-ref/
 924                         ir1_rx_pin: ir1-rx-pin {
 925                                 pins = "PB23";
 926                                 function = "ir1";
 927                         };
 928
 929                         /omit-if-no-ref/
 930                         ir1_tx_pin: ir1-tx-pin {
 931                                 pins = "PB22";
 932                                 function = "ir1";
 933                         };
 934
 935                         /omit-if-no-ref/
 936                         lcd_lvds0_pins: lcd-lvds0-pins {
 937                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 938                                        "PD5", "PD6", "PD7", "PD8", "PD9";
 939                                 function = "lvds0";
 940                         };
 941
 942                         /omit-if-no-ref/
 943                         lcd_lvds1_pins: lcd-lvds1-pins {
 944                                 pins = "PD10", "PD11", "PD12", "PD13", "PD14",
 945                                        "PD15", "PD16", "PD17", "PD18", "PD19";
 946                                 function = "lvds1";
 947                         };
 948
 949                         /omit-if-no-ref/
 950                         mmc0_pins: mmc0-pins {
 951                                 pins = "PF0", "PF1", "PF2",
 952                                        "PF3", "PF4", "PF5";
 953                                 function = "mmc0";
 954                                 drive-strength = <30>;
 955                                 bias-pull-up;
 956                         };
 957
 958                         /omit-if-no-ref/
 959                         mmc2_pins: mmc2-pins {
 960                                 pins = "PC6", "PC7", "PC8",
 961                                        "PC9", "PC10", "PC11";
 962                                 function = "mmc2";
 963                                 drive-strength = <30>;
 964                                 bias-pull-up;
 965                         };
 966
 967                         /omit-if-no-ref/
 968                         mmc3_pins: mmc3-pins {
 969                                 pins = "PI4", "PI5", "PI6",
 970                                        "PI7", "PI8", "PI9";
 971                                 function = "mmc3";
 972                                 drive-strength = <30>;
 973                                 bias-pull-up;
 974                         };
 975
 976                         /omit-if-no-ref/
 977                         ps2_0_pins: ps2-0-pins {
 978                                 pins = "PI20", "PI21";
 979                                 function = "ps2";
 980                         };
 981
 982                         /omit-if-no-ref/
 983                         ps2_1_ph_pins: ps2-1-ph-pins {
 984                                 pins = "PH12", "PH13";
 985                                 function = "ps2";
 986                         };
 987
 988                         /omit-if-no-ref/
 989                         pwm0_pin: pwm0-pin {
 990                                 pins = "PB2";
 991                                 function = "pwm";
 992                         };
 993
 994                         /omit-if-no-ref/
 995                         pwm1_pin: pwm1-pin {
 996                                 pins = "PI3";
 997                                 function = "pwm";
 998                         };
 999
1000                         /omit-if-no-ref/
1001                         spdif_tx_pin: spdif-tx-pin {
1002                                 pins = "PB13";
1003                                 function = "spdif";
1004                                 bias-pull-up;
1005                         };
1006
1007                         /omit-if-no-ref/
1008                         spi0_pi_pins: spi0-pi-pins {
1009                                 pins = "PI11", "PI12", "PI13";
1010                                 function = "spi0";
1011                         };
1012
1013                         /omit-if-no-ref/
1014                         spi0_cs0_pi_pin: spi0-cs0-pi-pin {
1015                                 pins = "PI10";
1016                                 function = "spi0";
1017                         };
1018
1019                         /omit-if-no-ref/
1020                         spi0_cs1_pi_pin: spi0-cs1-pi-pin {
1021                                 pins = "PI14";
1022                                 function = "spi0";
1023                         };
1024
1025                         /omit-if-no-ref/
1026                         spi1_pi_pins: spi1-pi-pins {
1027                                 pins = "PI17", "PI18", "PI19";
1028                                 function = "spi1";
1029                         };
1030
1031                         /omit-if-no-ref/
1032                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
1033                                 pins = "PI16";
1034                                 function = "spi1";
1035                         };
1036
1037                         /omit-if-no-ref/
1038                         spi2_pb_pins: spi2-pb-pins {
1039                                 pins = "PB15", "PB16", "PB17";
1040                                 function = "spi2";
1041                         };
1042
1043                         /omit-if-no-ref/
1044                         spi2_cs0_pb_pin: spi2-cs0-pb-pin {
1045                                 pins = "PB14";
1046                                 function = "spi2";
1047                         };
1048
1049                         /omit-if-no-ref/
1050                         spi2_pc_pins: spi2-pc-pins {
1051                                 pins = "PC20", "PC21", "PC22";
1052                                 function = "spi2";
1053                         };
1054
1055                         /omit-if-no-ref/
1056                         spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1057                                 pins = "PC19";
1058                                 function = "spi2";
1059                         };
1060
1061                         /omit-if-no-ref/
1062                         uart0_pb_pins: uart0-pb-pins {
1063                                 pins = "PB22", "PB23";
1064                                 function = "uart0";
1065                         };
1066
1067                         /omit-if-no-ref/
1068                         uart0_pf_pins: uart0-pf-pins {
1069                                 pins = "PF2", "PF4";
1070                                 function = "uart0";
1071                         };
1072
1073                         /omit-if-no-ref/
1074                         uart1_pa_pins: uart1-pa-pins {
1075                                 pins = "PA10", "PA11";
1076                                 function = "uart1";
1077                         };
1078
1079                         /omit-if-no-ref/
1080                         uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1081                                 pins = "PA12", "PA13";
1082                                 function = "uart1";
1083                         };
1084
1085                         /omit-if-no-ref/
1086                         uart2_pa_pins: uart2-pa-pins {
1087                                 pins = "PA2", "PA3";
1088                                 function = "uart2";
1089                         };
1090
1091                         /omit-if-no-ref/
1092                         uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1093                                 pins = "PA0", "PA1";
1094                                 function = "uart2";
1095                         };
1096
1097                         /omit-if-no-ref/
1098                         uart2_pi_pins: uart2-pi-pins {
1099                                 pins = "PI18", "PI19";
1100                                 function = "uart2";
1101                         };
1102
1103                         /omit-if-no-ref/
1104                         uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1105                                 pins = "PI16", "PI17";
1106                                 function = "uart2";
1107                         };
1108
1109                         /omit-if-no-ref/
1110                         uart3_pg_pins: uart3-pg-pins {
1111                                 pins = "PG6", "PG7";
1112                                 function = "uart3";
1113                         };
1114
1115                         /omit-if-no-ref/
1116                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1117                                 pins = "PG8", "PG9";
1118                                 function = "uart3";
1119                         };
1120
1121                         /omit-if-no-ref/
1122                         uart3_ph_pins: uart3-ph-pins {
1123                                 pins = "PH0", "PH1";
1124                                 function = "uart3";
1125                         };
1126
1127                         /omit-if-no-ref/
1128                         uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1129                                 pins = "PH2", "PH3";
1130                                 function = "uart3";
1131                         };
1132
1133                         /omit-if-no-ref/
1134                         uart4_pg_pins: uart4-pg-pins {
1135                                 pins = "PG10", "PG11";
1136                                 function = "uart4";
1137                         };
1138
1139                         /omit-if-no-ref/
1140                         uart4_ph_pins: uart4-ph-pins {
1141                                 pins = "PH4", "PH5";
1142                                 function = "uart4";
1143                         };
1144
1145                         /omit-if-no-ref/
1146                         uart5_ph_pins: uart5-ph-pins {
1147                                 pins = "PH6", "PH7";
1148                                 function = "uart5";
1149                         };
1150
1151                         /omit-if-no-ref/
1152                         uart5_pi_pins: uart5-pi-pins {
1153                                 pins = "PI10", "PI11";
1154                                 function = "uart5";
1155                         };
1156
1157                         /omit-if-no-ref/
1158                         uart6_pa_pins: uart6-pa-pins {
1159                                 pins = "PA12", "PA13";
1160                                 function = "uart6";
1161                         };
1162
1163                         /omit-if-no-ref/
1164                         uart6_pi_pins: uart6-pi-pins {
1165                                 pins = "PI12", "PI13";
1166                                 function = "uart6";
1167                         };
1168
1169                         /omit-if-no-ref/
1170                         uart7_pa_pins: uart7-pa-pins {
1171                                 pins = "PA14", "PA15";
1172                                 function = "uart7";
1173                         };
1174
1175                         /omit-if-no-ref/
1176                         uart7_pi_pins: uart7-pi-pins {
1177                                 pins = "PI20", "PI21";
1178                                 function = "uart7";
1179                         };
1180                 };
1181
1182                 timer@1c20c00 {
1183                         compatible = "allwinner,sun4i-a10-timer";
1184                         reg = <0x01c20c00 0x90>;
1185                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1186                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1187                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1188                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1189                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1190                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1191                         clocks = <&osc24M>;
1192                 };
1193
1194                 wdt: watchdog@1c20c90 {
1195                         compatible = "allwinner,sun4i-a10-wdt";
1196                         reg = <0x01c20c90 0x10>;
1197                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1198                         clocks = <&osc24M>;
1199                 };
1200
1201                 rtc: rtc@1c20d00 {
1202                         compatible = "allwinner,sun7i-a20-rtc";
1203                         reg = <0x01c20d00 0x20>;
1204                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1205                 };
1206
1207                 pwm: pwm@1c20e00 {
1208                         compatible = "allwinner,sun7i-a20-pwm";
1209                         reg = <0x01c20e00 0xc>;
1210                         clocks = <&osc24M>;
1211                         #pwm-cells = <3>;
1212                         status = "disabled";
1213                 };
1214
1215                 spdif: spdif@1c21000 {
1216                         #sound-dai-cells = <0>;
1217                         compatible = "allwinner,sun4i-a10-spdif";
1218                         reg = <0x01c21000 0x400>;
1219                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1220                         clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1221                         clock-names = "apb", "spdif";
1222                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1223                                <&dma SUN4I_DMA_NORMAL 2>;
1224                         dma-names = "rx", "tx";
1225                         status = "disabled";
1226                 };
1227
1228                 ir0: ir@1c21800 {
1229                         compatible = "allwinner,sun4i-a10-ir";
1230                         clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1231                         clock-names = "apb", "ir";
1232                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1233                         reg = <0x01c21800 0x40>;
1234                         status = "disabled";
1235                 };
1236
1237                 ir1: ir@1c21c00 {
1238                         compatible = "allwinner,sun4i-a10-ir";
1239                         clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1240                         clock-names = "apb", "ir";
1241                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1242                         reg = <0x01c21c00 0x40>;
1243                         status = "disabled";
1244                 };
1245
1246                 i2s1: i2s@1c22000 {
1247                         #sound-dai-cells = <0>;
1248                         compatible = "allwinner,sun4i-a10-i2s";
1249                         reg = <0x01c22000 0x400>;
1250                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1251                         clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1252                         clock-names = "apb", "mod";
1253                         dmas = <&dma SUN4I_DMA_NORMAL 4>,
1254                                <&dma SUN4I_DMA_NORMAL 4>;
1255                         dma-names = "rx", "tx";
1256                         status = "disabled";
1257                 };
1258
1259                 i2s0: i2s@1c22400 {
1260                         #sound-dai-cells = <0>;
1261                         compatible = "allwinner,sun4i-a10-i2s";
1262                         reg = <0x01c22400 0x400>;
1263                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1264                         clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1265                         clock-names = "apb", "mod";
1266                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
1267                                <&dma SUN4I_DMA_NORMAL 3>;
1268                         dma-names = "rx", "tx";
1269                         status = "disabled";
1270                 };
1271
1272                 lradc: lradc@1c22800 {
1273                         compatible = "allwinner,sun4i-a10-lradc-keys";
1274                         reg = <0x01c22800 0x100>;
1275                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1276                         status = "disabled";
1277                 };
1278
1279                 codec: codec@1c22c00 {
1280                         #sound-dai-cells = <0>;
1281                         compatible = "allwinner,sun7i-a20-codec";
1282                         reg = <0x01c22c00 0x40>;
1283                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1284                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1285                         clock-names = "apb", "codec";
1286                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1287                                <&dma SUN4I_DMA_NORMAL 19>;
1288                         dma-names = "rx", "tx";
1289                         status = "disabled";
1290                 };
1291
1292                 sid: eeprom@1c23800 {
1293                         compatible = "allwinner,sun7i-a20-sid";
1294                         reg = <0x01c23800 0x200>;
1295                 };
1296
1297                 i2s2: i2s@1c24400 {
1298                         #sound-dai-cells = <0>;
1299                         compatible = "allwinner,sun4i-a10-i2s";
1300                         reg = <0x01c24400 0x400>;
1301                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1302                         clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1303                         clock-names = "apb", "mod";
1304                         dmas = <&dma SUN4I_DMA_NORMAL 6>,
1305                                <&dma SUN4I_DMA_NORMAL 6>;
1306                         dma-names = "rx", "tx";
1307                         status = "disabled";
1308                 };
1309
1310                 rtp: rtp@1c25000 {
1311                         compatible = "allwinner,sun5i-a13-ts";
1312                         reg = <0x01c25000 0x100>;
1313                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1314                         #thermal-sensor-cells = <0>;
1315                 };
1316
1317                 uart0: serial@1c28000 {
1318                         compatible = "snps,dw-apb-uart";
1319                         reg = <0x01c28000 0x400>;
1320                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1321                         reg-shift = <2>;
1322                         reg-io-width = <4>;
1323                         clocks = <&ccu CLK_APB1_UART0>;
1324                         status = "disabled";
1325                 };
1326
1327                 uart1: serial@1c28400 {
1328                         compatible = "snps,dw-apb-uart";
1329                         reg = <0x01c28400 0x400>;
1330                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1331                         reg-shift = <2>;
1332                         reg-io-width = <4>;
1333                         clocks = <&ccu CLK_APB1_UART1>;
1334                         status = "disabled";
1335                 };
1336
1337                 uart2: serial@1c28800 {
1338                         compatible = "snps,dw-apb-uart";
1339                         reg = <0x01c28800 0x400>;
1340                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1341                         reg-shift = <2>;
1342                         reg-io-width = <4>;
1343                         clocks = <&ccu CLK_APB1_UART2>;
1344                         status = "disabled";
1345                 };
1346
1347                 uart3: serial@1c28c00 {
1348                         compatible = "snps,dw-apb-uart";
1349                         reg = <0x01c28c00 0x400>;
1350                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1351                         reg-shift = <2>;
1352                         reg-io-width = <4>;
1353                         clocks = <&ccu CLK_APB1_UART3>;
1354                         status = "disabled";
1355                 };
1356
1357                 uart4: serial@1c29000 {
1358                         compatible = "snps,dw-apb-uart";
1359                         reg = <0x01c29000 0x400>;
1360                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1361                         reg-shift = <2>;
1362                         reg-io-width = <4>;
1363                         clocks = <&ccu CLK_APB1_UART4>;
1364                         status = "disabled";
1365                 };
1366
1367                 uart5: serial@1c29400 {
1368                         compatible = "snps,dw-apb-uart";
1369                         reg = <0x01c29400 0x400>;
1370                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1371                         reg-shift = <2>;
1372                         reg-io-width = <4>;
1373                         clocks = <&ccu CLK_APB1_UART5>;
1374                         status = "disabled";
1375                 };
1376
1377                 uart6: serial@1c29800 {
1378                         compatible = "snps,dw-apb-uart";
1379                         reg = <0x01c29800 0x400>;
1380                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1381                         reg-shift = <2>;
1382                         reg-io-width = <4>;
1383                         clocks = <&ccu CLK_APB1_UART6>;
1384                         status = "disabled";
1385                 };
1386
1387                 uart7: serial@1c29c00 {
1388                         compatible = "snps,dw-apb-uart";
1389                         reg = <0x01c29c00 0x400>;
1390                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1391                         reg-shift = <2>;
1392                         reg-io-width = <4>;
1393                         clocks = <&ccu CLK_APB1_UART7>;
1394                         status = "disabled";
1395                 };
1396
1397                 ps20: ps2@1c2a000 {
1398                         compatible = "allwinner,sun4i-a10-ps2";
1399                         reg = <0x01c2a000 0x400>;
1400                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1401                         clocks = <&ccu CLK_APB1_PS20>;
1402                         status = "disabled";
1403                 };
1404
1405                 ps21: ps2@1c2a400 {
1406                         compatible = "allwinner,sun4i-a10-ps2";
1407                         reg = <0x01c2a400 0x400>;
1408                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1409                         clocks = <&ccu CLK_APB1_PS21>;
1410                         status = "disabled";
1411                 };
1412
1413                 i2c0: i2c@1c2ac00 {
1414                         compatible = "allwinner,sun7i-a20-i2c",
1415                                      "allwinner,sun4i-a10-i2c";
1416                         reg = <0x01c2ac00 0x400>;
1417                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1418                         clocks = <&ccu CLK_APB1_I2C0>;
1419                         pinctrl-names = "default";
1420                         pinctrl-0 = <&i2c0_pins>;
1421                         status = "disabled";
1422                         #address-cells = <1>;
1423                         #size-cells = <0>;
1424                 };
1425
1426                 i2c1: i2c@1c2b000 {
1427                         compatible = "allwinner,sun7i-a20-i2c",
1428                                      "allwinner,sun4i-a10-i2c";
1429                         reg = <0x01c2b000 0x400>;
1430                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1431                         clocks = <&ccu CLK_APB1_I2C1>;
1432                         pinctrl-names = "default";
1433                         pinctrl-0 = <&i2c1_pins>;
1434                         status = "disabled";
1435                         #address-cells = <1>;
1436                         #size-cells = <0>;
1437                 };
1438
1439                 i2c2: i2c@1c2b400 {
1440                         compatible = "allwinner,sun7i-a20-i2c",
1441                                      "allwinner,sun4i-a10-i2c";
1442                         reg = <0x01c2b400 0x400>;
1443                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1444                         clocks = <&ccu CLK_APB1_I2C2>;
1445                         pinctrl-names = "default";
1446                         pinctrl-0 = <&i2c2_pins>;
1447                         status = "disabled";
1448                         #address-cells = <1>;
1449                         #size-cells = <0>;
1450                 };
1451
1452                 i2c3: i2c@1c2b800 {
1453                         compatible = "allwinner,sun7i-a20-i2c",
1454                                      "allwinner,sun4i-a10-i2c";
1455                         reg = <0x01c2b800 0x400>;
1456                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1457                         clocks = <&ccu CLK_APB1_I2C3>;
1458                         pinctrl-names = "default";
1459                         pinctrl-0 = <&i2c3_pins>;
1460                         status = "disabled";
1461                         #address-cells = <1>;
1462                         #size-cells = <0>;
1463                 };
1464
1465                 can0: can@1c2bc00 {
1466                         compatible = "allwinner,sun7i-a20-can",
1467                                      "allwinner,sun4i-a10-can";
1468                         reg = <0x01c2bc00 0x400>;
1469                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1470                         clocks = <&ccu CLK_APB1_CAN>;
1471                         status = "disabled";
1472                 };
1473
1474                 i2c4: i2c@1c2c000 {
1475                         compatible = "allwinner,sun7i-a20-i2c",
1476                                      "allwinner,sun4i-a10-i2c";
1477                         reg = <0x01c2c000 0x400>;
1478                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1479                         clocks = <&ccu CLK_APB1_I2C4>;
1480                         status = "disabled";
1481                         #address-cells = <1>;
1482                         #size-cells = <0>;
1483                 };
1484
1485                 mali: gpu@1c40000 {
1486                         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1487                         reg = <0x01c40000 0x10000>;
1488                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1489                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1490                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1491                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1492                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1493                                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1494                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1495                         interrupt-names = "gp",
1496                                           "gpmmu",
1497                                           "pp0",
1498                                           "ppmmu0",
1499                                           "pp1",
1500                                           "ppmmu1",
1501                                           "pmu";
1502                         clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1503                         clock-names = "bus", "core";
1504                         resets = <&ccu RST_GPU>;
1505
1506                         assigned-clocks = <&ccu CLK_GPU>;
1507                         assigned-clock-rates = <384000000>;
1508                 };
1509
1510                 gmac: ethernet@1c50000 {
1511                         compatible = "allwinner,sun7i-a20-gmac";
1512                         reg = <0x01c50000 0x10000>;
1513                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1514                         interrupt-names = "macirq";
1515                         clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1516                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1517                         snps,pbl = <2>;
1518                         snps,fixed-burst;
1519                         snps,force_sf_dma_mode;
1520                         status = "disabled";
1521
1522                         gmac_mdio: mdio {
1523                                 compatible = "snps,dwmac-mdio";
1524                                 #address-cells = <1>;
1525                                 #size-cells = <0>;
1526                         };
1527                 };
1528
1529                 hstimer@1c60000 {
1530                         compatible = "allwinner,sun7i-a20-hstimer";
1531                         reg = <0x01c60000 0x1000>;
1532                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1533                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1534                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1535                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1536                         clocks = <&ccu CLK_AHB_HSTIMER>;
1537                 };
1538
1539                 gic: interrupt-controller@1c81000 {
1540                         compatible = "arm,gic-400";
1541                         reg = <0x01c81000 0x1000>,
1542                               <0x01c82000 0x2000>,
1543                               <0x01c84000 0x2000>,
1544                               <0x01c86000 0x2000>;
1545                         interrupt-controller;
1546                         #interrupt-cells = <3>;
1547                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1548                 };
1549
1550                 fe0: display-frontend@1e00000 {
1551                         compatible = "allwinner,sun7i-a20-display-frontend";
1552                         reg = <0x01e00000 0x20000>;
1553                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1554                         clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1555                                  <&ccu CLK_DRAM_DE_FE0>;
1556                         clock-names = "ahb", "mod",
1557                                       "ram";
1558                         resets = <&ccu RST_DE_FE0>;
1559
1560                         ports {
1561                                 #address-cells = <1>;
1562                                 #size-cells = <0>;
1563
1564                                 fe0_out: port@1 {
1565                                         #address-cells = <1>;
1566                                         #size-cells = <0>;
1567                                         reg = <1>;
1568
1569                                         fe0_out_be0: endpoint@0 {
1570                                                 reg = <0>;
1571                                                 remote-endpoint = <&be0_in_fe0>;
1572                                         };
1573
1574                                         fe0_out_be1: endpoint@1 {
1575                                                 reg = <1>;
1576                                                 remote-endpoint = <&be1_in_fe0>;
1577                                         };
1578                                 };
1579                         };
1580                 };
1581
1582                 fe1: display-frontend@1e20000 {
1583                         compatible = "allwinner,sun7i-a20-display-frontend";
1584                         reg = <0x01e20000 0x20000>;
1585                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1586                         clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1587                                  <&ccu CLK_DRAM_DE_FE1>;
1588                         clock-names = "ahb", "mod",
1589                                       "ram";
1590                         resets = <&ccu RST_DE_FE1>;
1591
1592                         ports {
1593                                 #address-cells = <1>;
1594                                 #size-cells = <0>;
1595
1596                                 fe1_out: port@1 {
1597                                         #address-cells = <1>;
1598                                         #size-cells = <0>;
1599                                         reg = <1>;
1600
1601                                         fe1_out_be0: endpoint@0 {
1602                                                 reg = <0>;
1603                                                 remote-endpoint = <&be0_in_fe1>;
1604                                         };
1605
1606                                         fe1_out_be1: endpoint@1 {
1607                                                 reg = <1>;
1608                                                 remote-endpoint = <&be1_in_fe1>;
1609                                         };
1610                                 };
1611                         };
1612                 };
1613
1614                 be1: display-backend@1e40000 {
1615                         compatible = "allwinner,sun7i-a20-display-backend";
1616                         reg = <0x01e40000 0x10000>;
1617                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1618                         clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1619                                  <&ccu CLK_DRAM_DE_BE1>;
1620                         clock-names = "ahb", "mod",
1621                                       "ram";
1622                         resets = <&ccu RST_DE_BE1>;
1623
1624                         ports {
1625                                 #address-cells = <1>;
1626                                 #size-cells = <0>;
1627
1628                                 be1_in: port@0 {
1629                                         #address-cells = <1>;
1630                                         #size-cells = <0>;
1631                                         reg = <0>;
1632
1633                                         be1_in_fe0: endpoint@0 {
1634                                                 reg = <0>;
1635                                                 remote-endpoint = <&fe0_out_be1>;
1636                                         };
1637
1638                                         be1_in_fe1: endpoint@1 {
1639                                                 reg = <1>;
1640                                                 remote-endpoint = <&fe1_out_be1>;
1641                                         };
1642                                 };
1643
1644                                 be1_out: port@1 {
1645                                         #address-cells = <1>;
1646                                         #size-cells = <0>;
1647                                         reg = <1>;
1648
1649                                         be1_out_tcon0: endpoint@0 {
1650                                                 reg = <0>;
1651                                                 remote-endpoint = <&tcon0_in_be1>;
1652                                         };
1653
1654                                         be1_out_tcon1: endpoint@1 {
1655                                                 reg = <1>;
1656                                                 remote-endpoint = <&tcon1_in_be1>;
1657                                         };
1658                                 };
1659                         };
1660                 };
1661
1662                 be0: display-backend@1e60000 {
1663                         compatible = "allwinner,sun7i-a20-display-backend";
1664                         reg = <0x01e60000 0x10000>;
1665                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1666                         clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1667                                  <&ccu CLK_DRAM_DE_BE0>;
1668                         clock-names = "ahb", "mod",
1669                                       "ram";
1670                         resets = <&ccu RST_DE_BE0>;
1671
1672                         ports {
1673                                 #address-cells = <1>;
1674                                 #size-cells = <0>;
1675
1676                                 be0_in: port@0 {
1677                                         #address-cells = <1>;
1678                                         #size-cells = <0>;
1679                                         reg = <0>;
1680
1681                                         be0_in_fe0: endpoint@0 {
1682                                                 reg = <0>;
1683                                                 remote-endpoint = <&fe0_out_be0>;
1684                                         };
1685
1686                                         be0_in_fe1: endpoint@1 {
1687                                                 reg = <1>;
1688                                                 remote-endpoint = <&fe1_out_be0>;
1689                                         };
1690                                 };
1691
1692                                 be0_out: port@1 {
1693                                         #address-cells = <1>;
1694                                         #size-cells = <0>;
1695                                         reg = <1>;
1696
1697                                         be0_out_tcon0: endpoint@0 {
1698                                                 reg = <0>;
1699                                                 remote-endpoint = <&tcon0_in_be0>;
1700                                         };
1701
1702                                         be0_out_tcon1: endpoint@1 {
1703                                                 reg = <1>;
1704                                                 remote-endpoint = <&tcon1_in_be0>;
1705                                         };
1706                                 };
1707                         };
1708                 };
1709         };
1710 };