2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
66 framebuffer-lcd0-hdmi {
67 compatible = "allwinner,simple-framebuffer",
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
71 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
72 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
78 compatible = "allwinner,simple-framebuffer",
80 allwinner,pipeline = "de_be0-lcd0";
81 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
82 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
83 <&ccu CLK_DRAM_DE_BE0>;
87 framebuffer-lcd0-tve0 {
88 compatible = "allwinner,simple-framebuffer",
90 allwinner,pipeline = "de_be0-lcd0-tve0";
91 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
92 <&ccu CLK_AHB_DE_BE0>,
93 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
94 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
100 #address-cells = <1>;
104 compatible = "arm,cortex-a7";
107 clocks = <&ccu CLK_CPU>;
108 clock-latency = <244144>; /* 8 32k periods */
118 #cooling-cells = <2>;
122 compatible = "arm,cortex-a7";
125 clocks = <&ccu CLK_CPU>;
126 clock-latency = <244144>; /* 8 32k periods */
136 #cooling-cells = <2>;
143 polling-delay-passive = <250>;
144 polling-delay = <1000>;
145 thermal-sensors = <&rtp>;
149 trip = <&cpu_alert0>;
150 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
151 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
156 cpu_alert0: cpu_alert0 {
158 temperature = <75000>;
165 temperature = <100000>;
174 #address-cells = <1>;
178 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
180 compatible = "shared-dma-pool";
182 alloc-ranges = <0x40000000 0x10000000>;
189 compatible = "arm,armv7-timer";
190 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
191 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
192 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
193 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
197 compatible = "arm,cortex-a7-pmu";
198 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
203 #address-cells = <1>;
209 compatible = "fixed-clock";
210 clock-frequency = <24000000>;
211 clock-output-names = "osc24M";
216 compatible = "fixed-clock";
217 clock-frequency = <32768>;
218 clock-output-names = "osc32k";
222 * The following two are dummy clocks, placeholders
223 * used in the gmac_tx clock. The gmac driver will
224 * choose one parent depending on the PHY interface
225 * mode, using clk_set_rate auto-reparenting.
227 * The actual TX clock rate is not controlled by the
230 mii_phy_tx_clk: clk-mii-phy-tx {
232 compatible = "fixed-clock";
233 clock-frequency = <25000000>;
234 clock-output-names = "mii_phy_tx";
237 gmac_int_tx_clk: clk-gmac-int-tx {
239 compatible = "fixed-clock";
240 clock-frequency = <125000000>;
241 clock-output-names = "gmac_int_tx";
244 gmac_tx_clk: clk@1c20164 {
246 compatible = "allwinner,sun7i-a20-gmac-clk";
247 reg = <0x01c20164 0x4>;
248 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
249 clock-output-names = "gmac_tx";
255 compatible = "allwinner,sun7i-a20-display-engine";
256 allwinner,pipelines = <&fe0>, <&fe1>;
261 compatible = "simple-bus";
262 #address-cells = <1>;
266 system-control@1c00000 {
267 compatible = "allwinner,sun7i-a20-system-control",
268 "allwinner,sun4i-a10-system-control";
269 reg = <0x01c00000 0x30>;
270 #address-cells = <1>;
275 compatible = "mmio-sram";
276 reg = <0x00000000 0xc000>;
277 #address-cells = <1>;
279 ranges = <0 0x00000000 0xc000>;
281 emac_sram: sram-section@8000 {
282 compatible = "allwinner,sun7i-a20-sram-a3-a4",
283 "allwinner,sun4i-a10-sram-a3-a4";
284 reg = <0x8000 0x4000>;
290 compatible = "mmio-sram";
291 reg = <0x00010000 0x1000>;
292 #address-cells = <1>;
294 ranges = <0 0x00010000 0x1000>;
296 otg_sram: sram-section@0 {
297 compatible = "allwinner,sun7i-a20-sram-d",
298 "allwinner,sun4i-a10-sram-d";
299 reg = <0x0000 0x1000>;
304 sram_c: sram@1d00000 {
305 compatible = "mmio-sram";
306 reg = <0x01d00000 0xd0000>;
307 #address-cells = <1>;
309 ranges = <0 0x01d00000 0xd0000>;
311 ve_sram: sram-section@0 {
312 compatible = "allwinner,sun7i-a20-sram-c1",
313 "allwinner,sun4i-a10-sram-c1";
314 reg = <0x000000 0x80000>;
319 nmi_intc: interrupt-controller@1c00030 {
320 compatible = "allwinner,sun7i-a20-sc-nmi";
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 reg = <0x01c00030 0x0c>;
324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
327 dma: dma-controller@1c02000 {
328 compatible = "allwinner,sun4i-a10-dma";
329 reg = <0x01c02000 0x1000>;
330 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&ccu CLK_AHB_DMA>;
335 nfc: nand-controller@1c03000 {
336 compatible = "allwinner,sun4i-a10-nand";
337 reg = <0x01c03000 0x1000>;
338 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
340 clock-names = "ahb", "mod";
341 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
344 #address-cells = <1>;
349 compatible = "allwinner,sun4i-a10-spi";
350 reg = <0x01c05000 0x1000>;
351 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
353 clock-names = "ahb", "mod";
354 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
355 <&dma SUN4I_DMA_DEDICATED 26>;
356 dma-names = "rx", "tx";
358 #address-cells = <1>;
364 compatible = "allwinner,sun4i-a10-spi";
365 reg = <0x01c06000 0x1000>;
366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
368 clock-names = "ahb", "mod";
369 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
370 <&dma SUN4I_DMA_DEDICATED 8>;
371 dma-names = "rx", "tx";
373 #address-cells = <1>;
379 compatible = "allwinner,sun7i-a20-csi0";
380 reg = <0x01c09000 0x1000>;
381 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
383 clock-names = "bus", "isp", "ram";
384 resets = <&ccu RST_CSI0>;
388 emac: ethernet@1c0b000 {
389 compatible = "allwinner,sun4i-a10-emac";
390 reg = <0x01c0b000 0x1000>;
391 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&ccu CLK_AHB_EMAC>;
393 allwinner,sram = <&emac_sram 1>;
398 compatible = "allwinner,sun4i-a10-mdio";
399 reg = <0x01c0b080 0x14>;
401 #address-cells = <1>;
405 tcon0: lcd-controller@1c0c000 {
406 compatible = "allwinner,sun7i-a20-tcon0",
407 "allwinner,sun7i-a20-tcon";
408 reg = <0x01c0c000 0x1000>;
409 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
410 resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
411 reset-names = "lcd", "lvds";
412 clocks = <&ccu CLK_AHB_LCD0>,
413 <&ccu CLK_TCON0_CH0>,
414 <&ccu CLK_TCON0_CH1>;
418 clock-output-names = "tcon0-pixel-clock";
420 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
423 #address-cells = <1>;
427 #address-cells = <1>;
431 tcon0_in_be0: endpoint@0 {
433 remote-endpoint = <&be0_out_tcon0>;
436 tcon0_in_be1: endpoint@1 {
438 remote-endpoint = <&be1_out_tcon0>;
443 #address-cells = <1>;
447 tcon0_out_hdmi: endpoint@1 {
449 remote-endpoint = <&hdmi_in_tcon0>;
450 allwinner,tcon-channel = <1>;
456 tcon1: lcd-controller@1c0d000 {
457 compatible = "allwinner,sun7i-a20-tcon1",
458 "allwinner,sun7i-a20-tcon";
459 reg = <0x01c0d000 0x1000>;
460 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
461 resets = <&ccu RST_TCON1>;
463 clocks = <&ccu CLK_AHB_LCD1>,
464 <&ccu CLK_TCON1_CH0>,
465 <&ccu CLK_TCON1_CH1>;
469 clock-output-names = "tcon1-pixel-clock";
471 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
474 #address-cells = <1>;
478 #address-cells = <1>;
482 tcon1_in_be0: endpoint@0 {
484 remote-endpoint = <&be0_out_tcon1>;
487 tcon1_in_be1: endpoint@1 {
489 remote-endpoint = <&be1_out_tcon1>;
494 #address-cells = <1>;
498 tcon1_out_hdmi: endpoint@1 {
500 remote-endpoint = <&hdmi_in_tcon1>;
501 allwinner,tcon-channel = <1>;
507 video-codec@1c0e000 {
508 compatible = "allwinner,sun7i-a20-video-engine";
509 reg = <0x01c0e000 0x1000>;
510 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
512 clock-names = "ahb", "mod", "ram";
513 resets = <&ccu RST_VE>;
514 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
515 allwinner,sram = <&ve_sram 1>;
519 compatible = "allwinner,sun7i-a20-mmc";
520 reg = <0x01c0f000 0x1000>;
521 clocks = <&ccu CLK_AHB_MMC0>,
523 <&ccu CLK_MMC0_OUTPUT>,
524 <&ccu CLK_MMC0_SAMPLE>;
529 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&mmc0_pins>;
533 #address-cells = <1>;
538 compatible = "allwinner,sun7i-a20-mmc";
539 reg = <0x01c10000 0x1000>;
540 clocks = <&ccu CLK_AHB_MMC1>,
542 <&ccu CLK_MMC1_OUTPUT>,
543 <&ccu CLK_MMC1_SAMPLE>;
548 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
550 #address-cells = <1>;
555 compatible = "allwinner,sun7i-a20-mmc";
556 reg = <0x01c11000 0x1000>;
557 clocks = <&ccu CLK_AHB_MMC2>,
559 <&ccu CLK_MMC2_OUTPUT>,
560 <&ccu CLK_MMC2_SAMPLE>;
565 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&mmc2_pins>;
569 #address-cells = <1>;
574 compatible = "allwinner,sun7i-a20-mmc";
575 reg = <0x01c12000 0x1000>;
576 clocks = <&ccu CLK_AHB_MMC3>,
578 <&ccu CLK_MMC3_OUTPUT>,
579 <&ccu CLK_MMC3_SAMPLE>;
584 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&mmc3_pins>;
588 #address-cells = <1>;
592 usb_otg: usb@1c13000 {
593 compatible = "allwinner,sun4i-a10-musb";
594 reg = <0x01c13000 0x0400>;
595 clocks = <&ccu CLK_AHB_OTG>;
596 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
597 interrupt-names = "mc";
600 extcon = <&usbphy 0>;
601 allwinner,sram = <&otg_sram 1>;
606 usbphy: phy@1c13400 {
608 compatible = "allwinner,sun7i-a20-usb-phy";
609 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
610 reg-names = "phy_ctrl", "pmu1", "pmu2";
611 clocks = <&ccu CLK_USB_PHY>;
612 clock-names = "usb_phy";
613 resets = <&ccu RST_USB_PHY0>,
616 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
621 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
622 reg = <0x01c14000 0x100>;
623 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&ccu CLK_AHB_EHCI0>;
631 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
632 reg = <0x01c14400 0x100>;
633 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
640 crypto: crypto-engine@1c15000 {
641 compatible = "allwinner,sun7i-a20-crypto",
642 "allwinner,sun4i-a10-crypto";
643 reg = <0x01c15000 0x1000>;
644 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
646 clock-names = "ahb", "mod";
650 compatible = "allwinner,sun7i-a20-hdmi",
651 "allwinner,sun5i-a10s-hdmi";
652 reg = <0x01c16000 0x1000>;
653 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
655 <&ccu CLK_PLL_VIDEO0_2X>,
656 <&ccu CLK_PLL_VIDEO1_2X>;
657 clock-names = "ahb", "mod", "pll-0", "pll-1";
658 dmas = <&dma SUN4I_DMA_NORMAL 16>,
659 <&dma SUN4I_DMA_NORMAL 16>,
660 <&dma SUN4I_DMA_DEDICATED 24>;
661 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
665 #address-cells = <1>;
669 #address-cells = <1>;
673 hdmi_in_tcon0: endpoint@0 {
675 remote-endpoint = <&tcon0_out_hdmi>;
678 hdmi_in_tcon1: endpoint@1 {
680 remote-endpoint = <&tcon1_out_hdmi>;
691 compatible = "allwinner,sun4i-a10-spi";
692 reg = <0x01c17000 0x1000>;
693 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
695 clock-names = "ahb", "mod";
696 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
697 <&dma SUN4I_DMA_DEDICATED 28>;
698 dma-names = "rx", "tx";
700 #address-cells = <1>;
706 compatible = "allwinner,sun4i-a10-ahci";
707 reg = <0x01c18000 0x1000>;
708 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
714 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
715 reg = <0x01c1c000 0x100>;
716 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&ccu CLK_AHB_EHCI1>;
724 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
725 reg = <0x01c1c400 0x100>;
726 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
734 compatible = "allwinner,sun7i-a20-csi1",
735 "allwinner,sun4i-a10-csi1";
736 reg = <0x01c1d000 0x1000>;
737 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
739 clock-names = "bus", "ram";
740 resets = <&ccu RST_CSI1>;
745 compatible = "allwinner,sun4i-a10-spi";
746 reg = <0x01c1f000 0x1000>;
747 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
749 clock-names = "ahb", "mod";
750 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
751 <&dma SUN4I_DMA_DEDICATED 30>;
752 dma-names = "rx", "tx";
754 #address-cells = <1>;
760 compatible = "allwinner,sun7i-a20-ccu";
761 reg = <0x01c20000 0x400>;
762 clocks = <&osc24M>, <&osc32k>;
763 clock-names = "hosc", "losc";
768 pio: pinctrl@1c20800 {
769 compatible = "allwinner,sun7i-a20-pinctrl";
770 reg = <0x01c20800 0x400>;
771 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
773 clock-names = "apb", "hosc", "losc";
775 interrupt-controller;
776 #interrupt-cells = <3>;
780 can_pa_pins: can-pa-pins {
781 pins = "PA16", "PA17";
786 can_ph_pins: can-ph-pins {
787 pins = "PH20", "PH21";
792 clk_out_a_pin: clk-out-a-pin {
794 function = "clk_out_a";
798 clk_out_b_pin: clk-out-b-pin {
800 function = "clk_out_b";
804 csi0_8bits_pins: csi-8bits-pins {
805 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
806 "PE6", "PE7", "PE8", "PE9", "PE10",
812 csi0_clk_pin: csi-clk-pin {
818 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
819 pins = "PG0", "PG2", "PG3", "PG4", "PG5",
820 "PG6", "PG7", "PG8", "PG9", "PG10",
826 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
827 pins = "PH0", "PH1", "PH2", "PH3", "PH4",
828 "PH5", "PH6", "PH7", "PH8", "PH9",
829 "PH10", "PH11", "PH12", "PH13", "PH14",
830 "PH15", "PH16", "PH17", "PH18", "PH19",
831 "PH20", "PH21", "PH22", "PH23", "PH24",
832 "PH25", "PH26", "PH27";
837 csi1_clk_pg_pin: csi1-clk-pg-pin {
843 emac_pa_pins: emac-pa-pins {
844 pins = "PA0", "PA1", "PA2",
845 "PA3", "PA4", "PA5", "PA6",
846 "PA7", "PA8", "PA9", "PA10",
847 "PA11", "PA12", "PA13", "PA14",
853 emac_ph_pins: emac-ph-pins {
854 pins = "PH8", "PH9", "PH10", "PH11",
855 "PH14", "PH15", "PH16", "PH17",
856 "PH18", "PH19", "PH20", "PH21",
857 "PH22", "PH23", "PH24", "PH25",
863 gmac_mii_pins: gmac-mii-pins {
864 pins = "PA0", "PA1", "PA2",
865 "PA3", "PA4", "PA5", "PA6",
866 "PA7", "PA8", "PA9", "PA10",
867 "PA11", "PA12", "PA13", "PA14",
873 gmac_rgmii_pins: gmac-rgmii-pins {
874 pins = "PA0", "PA1", "PA2",
875 "PA3", "PA4", "PA5", "PA6",
876 "PA7", "PA8", "PA10",
877 "PA11", "PA12", "PA13",
881 * data lines in RGMII mode use DDR mode
882 * and need a higher signal drive strength
884 drive-strength = <40>;
888 i2c0_pins: i2c0-pins {
894 i2c1_pins: i2c1-pins {
895 pins = "PB18", "PB19";
900 i2c2_pins: i2c2-pins {
901 pins = "PB20", "PB21";
906 i2c3_pins: i2c3-pins {
912 ir0_rx_pin: ir0-rx-pin {
918 ir0_tx_pin: ir0-tx-pin {
924 ir1_rx_pin: ir1-rx-pin {
930 ir1_tx_pin: ir1-tx-pin {
936 lcd_lvds0_pins: lcd-lvds0-pins {
937 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
938 "PD5", "PD6", "PD7", "PD8", "PD9";
943 lcd_lvds1_pins: lcd-lvds1-pins {
944 pins = "PD10", "PD11", "PD12", "PD13", "PD14",
945 "PD15", "PD16", "PD17", "PD18", "PD19";
950 mmc0_pins: mmc0-pins {
951 pins = "PF0", "PF1", "PF2",
954 drive-strength = <30>;
959 mmc2_pins: mmc2-pins {
960 pins = "PC6", "PC7", "PC8",
961 "PC9", "PC10", "PC11";
963 drive-strength = <30>;
968 mmc3_pins: mmc3-pins {
969 pins = "PI4", "PI5", "PI6",
972 drive-strength = <30>;
977 ps2_0_pins: ps2-0-pins {
978 pins = "PI20", "PI21";
983 ps2_1_ph_pins: ps2-1-ph-pins {
984 pins = "PH12", "PH13";
1001 spdif_tx_pin: spdif-tx-pin {
1008 spi0_pi_pins: spi0-pi-pins {
1009 pins = "PI11", "PI12", "PI13";
1014 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
1020 spi0_cs1_pi_pin: spi0-cs1-pi-pin {
1026 spi1_pi_pins: spi1-pi-pins {
1027 pins = "PI17", "PI18", "PI19";
1032 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
1038 spi2_pb_pins: spi2-pb-pins {
1039 pins = "PB15", "PB16", "PB17";
1044 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
1050 spi2_pc_pins: spi2-pc-pins {
1051 pins = "PC20", "PC21", "PC22";
1056 spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1062 uart0_pb_pins: uart0-pb-pins {
1063 pins = "PB22", "PB23";
1068 uart0_pf_pins: uart0-pf-pins {
1069 pins = "PF2", "PF4";
1074 uart1_pa_pins: uart1-pa-pins {
1075 pins = "PA10", "PA11";
1080 uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1081 pins = "PA12", "PA13";
1086 uart2_pa_pins: uart2-pa-pins {
1087 pins = "PA2", "PA3";
1092 uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1093 pins = "PA0", "PA1";
1098 uart2_pi_pins: uart2-pi-pins {
1099 pins = "PI18", "PI19";
1104 uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1105 pins = "PI16", "PI17";
1110 uart3_pg_pins: uart3-pg-pins {
1111 pins = "PG6", "PG7";
1116 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1117 pins = "PG8", "PG9";
1122 uart3_ph_pins: uart3-ph-pins {
1123 pins = "PH0", "PH1";
1128 uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1129 pins = "PH2", "PH3";
1134 uart4_pg_pins: uart4-pg-pins {
1135 pins = "PG10", "PG11";
1140 uart4_ph_pins: uart4-ph-pins {
1141 pins = "PH4", "PH5";
1146 uart5_ph_pins: uart5-ph-pins {
1147 pins = "PH6", "PH7";
1152 uart5_pi_pins: uart5-pi-pins {
1153 pins = "PI10", "PI11";
1158 uart6_pa_pins: uart6-pa-pins {
1159 pins = "PA12", "PA13";
1164 uart6_pi_pins: uart6-pi-pins {
1165 pins = "PI12", "PI13";
1170 uart7_pa_pins: uart7-pa-pins {
1171 pins = "PA14", "PA15";
1176 uart7_pi_pins: uart7-pi-pins {
1177 pins = "PI20", "PI21";
1183 compatible = "allwinner,sun4i-a10-timer";
1184 reg = <0x01c20c00 0x90>;
1185 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1194 wdt: watchdog@1c20c90 {
1195 compatible = "allwinner,sun4i-a10-wdt";
1196 reg = <0x01c20c90 0x10>;
1197 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1202 compatible = "allwinner,sun7i-a20-rtc";
1203 reg = <0x01c20d00 0x20>;
1204 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1208 compatible = "allwinner,sun7i-a20-pwm";
1209 reg = <0x01c20e00 0xc>;
1212 status = "disabled";
1215 spdif: spdif@1c21000 {
1216 #sound-dai-cells = <0>;
1217 compatible = "allwinner,sun4i-a10-spdif";
1218 reg = <0x01c21000 0x400>;
1219 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1221 clock-names = "apb", "spdif";
1222 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1223 <&dma SUN4I_DMA_NORMAL 2>;
1224 dma-names = "rx", "tx";
1225 status = "disabled";
1229 compatible = "allwinner,sun4i-a10-ir";
1230 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1231 clock-names = "apb", "ir";
1232 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1233 reg = <0x01c21800 0x40>;
1234 status = "disabled";
1238 compatible = "allwinner,sun4i-a10-ir";
1239 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1240 clock-names = "apb", "ir";
1241 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1242 reg = <0x01c21c00 0x40>;
1243 status = "disabled";
1247 #sound-dai-cells = <0>;
1248 compatible = "allwinner,sun4i-a10-i2s";
1249 reg = <0x01c22000 0x400>;
1250 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1252 clock-names = "apb", "mod";
1253 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1254 <&dma SUN4I_DMA_NORMAL 4>;
1255 dma-names = "rx", "tx";
1256 status = "disabled";
1260 #sound-dai-cells = <0>;
1261 compatible = "allwinner,sun4i-a10-i2s";
1262 reg = <0x01c22400 0x400>;
1263 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1265 clock-names = "apb", "mod";
1266 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1267 <&dma SUN4I_DMA_NORMAL 3>;
1268 dma-names = "rx", "tx";
1269 status = "disabled";
1272 lradc: lradc@1c22800 {
1273 compatible = "allwinner,sun4i-a10-lradc-keys";
1274 reg = <0x01c22800 0x100>;
1275 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1276 status = "disabled";
1279 codec: codec@1c22c00 {
1280 #sound-dai-cells = <0>;
1281 compatible = "allwinner,sun7i-a20-codec";
1282 reg = <0x01c22c00 0x40>;
1283 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1284 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1285 clock-names = "apb", "codec";
1286 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1287 <&dma SUN4I_DMA_NORMAL 19>;
1288 dma-names = "rx", "tx";
1289 status = "disabled";
1292 sid: eeprom@1c23800 {
1293 compatible = "allwinner,sun7i-a20-sid";
1294 reg = <0x01c23800 0x200>;
1298 #sound-dai-cells = <0>;
1299 compatible = "allwinner,sun4i-a10-i2s";
1300 reg = <0x01c24400 0x400>;
1301 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1303 clock-names = "apb", "mod";
1304 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1305 <&dma SUN4I_DMA_NORMAL 6>;
1306 dma-names = "rx", "tx";
1307 status = "disabled";
1311 compatible = "allwinner,sun5i-a13-ts";
1312 reg = <0x01c25000 0x100>;
1313 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1314 #thermal-sensor-cells = <0>;
1317 uart0: serial@1c28000 {
1318 compatible = "snps,dw-apb-uart";
1319 reg = <0x01c28000 0x400>;
1320 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&ccu CLK_APB1_UART0>;
1324 status = "disabled";
1327 uart1: serial@1c28400 {
1328 compatible = "snps,dw-apb-uart";
1329 reg = <0x01c28400 0x400>;
1330 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1333 clocks = <&ccu CLK_APB1_UART1>;
1334 status = "disabled";
1337 uart2: serial@1c28800 {
1338 compatible = "snps,dw-apb-uart";
1339 reg = <0x01c28800 0x400>;
1340 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1343 clocks = <&ccu CLK_APB1_UART2>;
1344 status = "disabled";
1347 uart3: serial@1c28c00 {
1348 compatible = "snps,dw-apb-uart";
1349 reg = <0x01c28c00 0x400>;
1350 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1353 clocks = <&ccu CLK_APB1_UART3>;
1354 status = "disabled";
1357 uart4: serial@1c29000 {
1358 compatible = "snps,dw-apb-uart";
1359 reg = <0x01c29000 0x400>;
1360 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1363 clocks = <&ccu CLK_APB1_UART4>;
1364 status = "disabled";
1367 uart5: serial@1c29400 {
1368 compatible = "snps,dw-apb-uart";
1369 reg = <0x01c29400 0x400>;
1370 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1373 clocks = <&ccu CLK_APB1_UART5>;
1374 status = "disabled";
1377 uart6: serial@1c29800 {
1378 compatible = "snps,dw-apb-uart";
1379 reg = <0x01c29800 0x400>;
1380 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&ccu CLK_APB1_UART6>;
1384 status = "disabled";
1387 uart7: serial@1c29c00 {
1388 compatible = "snps,dw-apb-uart";
1389 reg = <0x01c29c00 0x400>;
1390 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1393 clocks = <&ccu CLK_APB1_UART7>;
1394 status = "disabled";
1398 compatible = "allwinner,sun4i-a10-ps2";
1399 reg = <0x01c2a000 0x400>;
1400 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1401 clocks = <&ccu CLK_APB1_PS20>;
1402 status = "disabled";
1406 compatible = "allwinner,sun4i-a10-ps2";
1407 reg = <0x01c2a400 0x400>;
1408 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&ccu CLK_APB1_PS21>;
1410 status = "disabled";
1414 compatible = "allwinner,sun7i-a20-i2c",
1415 "allwinner,sun4i-a10-i2c";
1416 reg = <0x01c2ac00 0x400>;
1417 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1418 clocks = <&ccu CLK_APB1_I2C0>;
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&i2c0_pins>;
1421 status = "disabled";
1422 #address-cells = <1>;
1427 compatible = "allwinner,sun7i-a20-i2c",
1428 "allwinner,sun4i-a10-i2c";
1429 reg = <0x01c2b000 0x400>;
1430 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&ccu CLK_APB1_I2C1>;
1432 pinctrl-names = "default";
1433 pinctrl-0 = <&i2c1_pins>;
1434 status = "disabled";
1435 #address-cells = <1>;
1440 compatible = "allwinner,sun7i-a20-i2c",
1441 "allwinner,sun4i-a10-i2c";
1442 reg = <0x01c2b400 0x400>;
1443 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&ccu CLK_APB1_I2C2>;
1445 pinctrl-names = "default";
1446 pinctrl-0 = <&i2c2_pins>;
1447 status = "disabled";
1448 #address-cells = <1>;
1453 compatible = "allwinner,sun7i-a20-i2c",
1454 "allwinner,sun4i-a10-i2c";
1455 reg = <0x01c2b800 0x400>;
1456 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&ccu CLK_APB1_I2C3>;
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&i2c3_pins>;
1460 status = "disabled";
1461 #address-cells = <1>;
1466 compatible = "allwinner,sun7i-a20-can",
1467 "allwinner,sun4i-a10-can";
1468 reg = <0x01c2bc00 0x400>;
1469 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&ccu CLK_APB1_CAN>;
1471 status = "disabled";
1475 compatible = "allwinner,sun7i-a20-i2c",
1476 "allwinner,sun4i-a10-i2c";
1477 reg = <0x01c2c000 0x400>;
1478 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&ccu CLK_APB1_I2C4>;
1480 status = "disabled";
1481 #address-cells = <1>;
1486 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1487 reg = <0x01c40000 0x10000>;
1488 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1495 interrupt-names = "gp",
1502 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1503 clock-names = "bus", "core";
1504 resets = <&ccu RST_GPU>;
1506 assigned-clocks = <&ccu CLK_GPU>;
1507 assigned-clock-rates = <384000000>;
1510 gmac: ethernet@1c50000 {
1511 compatible = "allwinner,sun7i-a20-gmac";
1512 reg = <0x01c50000 0x10000>;
1513 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1514 interrupt-names = "macirq";
1515 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1516 clock-names = "stmmaceth", "allwinner_gmac_tx";
1519 snps,force_sf_dma_mode;
1520 status = "disabled";
1523 compatible = "snps,dwmac-mdio";
1524 #address-cells = <1>;
1530 compatible = "allwinner,sun7i-a20-hstimer";
1531 reg = <0x01c60000 0x1000>;
1532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1536 clocks = <&ccu CLK_AHB_HSTIMER>;
1539 gic: interrupt-controller@1c81000 {
1540 compatible = "arm,gic-400";
1541 reg = <0x01c81000 0x1000>,
1542 <0x01c82000 0x2000>,
1543 <0x01c84000 0x2000>,
1544 <0x01c86000 0x2000>;
1545 interrupt-controller;
1546 #interrupt-cells = <3>;
1547 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1550 fe0: display-frontend@1e00000 {
1551 compatible = "allwinner,sun7i-a20-display-frontend";
1552 reg = <0x01e00000 0x20000>;
1553 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1554 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1555 <&ccu CLK_DRAM_DE_FE0>;
1556 clock-names = "ahb", "mod",
1558 resets = <&ccu RST_DE_FE0>;
1561 #address-cells = <1>;
1565 #address-cells = <1>;
1569 fe0_out_be0: endpoint@0 {
1571 remote-endpoint = <&be0_in_fe0>;
1574 fe0_out_be1: endpoint@1 {
1576 remote-endpoint = <&be1_in_fe0>;
1582 fe1: display-frontend@1e20000 {
1583 compatible = "allwinner,sun7i-a20-display-frontend";
1584 reg = <0x01e20000 0x20000>;
1585 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1586 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1587 <&ccu CLK_DRAM_DE_FE1>;
1588 clock-names = "ahb", "mod",
1590 resets = <&ccu RST_DE_FE1>;
1593 #address-cells = <1>;
1597 #address-cells = <1>;
1601 fe1_out_be0: endpoint@0 {
1603 remote-endpoint = <&be0_in_fe1>;
1606 fe1_out_be1: endpoint@1 {
1608 remote-endpoint = <&be1_in_fe1>;
1614 be1: display-backend@1e40000 {
1615 compatible = "allwinner,sun7i-a20-display-backend";
1616 reg = <0x01e40000 0x10000>;
1617 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1619 <&ccu CLK_DRAM_DE_BE1>;
1620 clock-names = "ahb", "mod",
1622 resets = <&ccu RST_DE_BE1>;
1625 #address-cells = <1>;
1629 #address-cells = <1>;
1633 be1_in_fe0: endpoint@0 {
1635 remote-endpoint = <&fe0_out_be1>;
1638 be1_in_fe1: endpoint@1 {
1640 remote-endpoint = <&fe1_out_be1>;
1645 #address-cells = <1>;
1649 be1_out_tcon0: endpoint@0 {
1651 remote-endpoint = <&tcon0_in_be1>;
1654 be1_out_tcon1: endpoint@1 {
1656 remote-endpoint = <&tcon1_in_be1>;
1662 be0: display-backend@1e60000 {
1663 compatible = "allwinner,sun7i-a20-display-backend";
1664 reg = <0x01e60000 0x10000>;
1665 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1666 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1667 <&ccu CLK_DRAM_DE_BE0>;
1668 clock-names = "ahb", "mod",
1670 resets = <&ccu RST_DE_BE0>;
1673 #address-cells = <1>;
1677 #address-cells = <1>;
1681 be0_in_fe0: endpoint@0 {
1683 remote-endpoint = <&fe0_out_be0>;
1686 be0_in_fe1: endpoint@1 {
1688 remote-endpoint = <&fe1_out_be0>;
1693 #address-cells = <1>;
1697 be0_out_tcon0: endpoint@0 {
1699 remote-endpoint = <&tcon0_in_be0>;
1702 be0_out_tcon1: endpoint@1 {
1704 remote-endpoint = <&tcon1_in_be0>;