arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/dma/sun4i-a10.h>
  48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
  49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 framebuffer-lcd0-hdmi {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  70                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  71                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
  72                                  <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 framebuffer-lcd0 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  81                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
  82                                  <&ccu CLK_DRAM_DE_BE0>;
  83                         status = "disabled";
  84                 };
  85
  86                 framebuffer-lcd0-tve0 {
  87                         compatible = "allwinner,simple-framebuffer",
  88                                      "simple-framebuffer";
  89                         allwinner,pipeline = "de_be0-lcd0-tve0";
  90                         clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
  91                                  <&ccu CLK_AHB_DE_BE0>,
  92                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
  93                                  <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
  94                         status = "disabled";
  95                 };
  96         };
  97
  98         cpus {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 960000  1400000
 111                                 912000  1400000
 112                                 864000  1300000
 113                                 720000  1200000
 114                                 528000  1100000
 115                                 312000  1000000
 116                                 144000  1000000
 117                                 >;
 118                         #cooling-cells = <2>;
 119                 };
 120
 121                 cpu1: cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                         clocks = <&ccu CLK_CPU>;
 126                         clock-latency = <244144>; /* 8 32k periods */
 127                         operating-points = <
 128                                 /* kHz    uV */
 129                                 960000  1400000
 130                                 912000  1400000
 131                                 864000  1300000
 132                                 720000  1200000
 133                                 528000  1100000
 134                                 312000  1000000
 135                                 144000  1000000
 136                                 >;
 137                         #cooling-cells = <2>;
 138                 };
 139         };
 140
 141         thermal-zones {
 142                 cpu_thermal {
 143                         /* milliseconds */
 144                         polling-delay-passive = <250>;
 145                         polling-delay = <1000>;
 146                         thermal-sensors = <&rtp>;
 147
 148                         cooling-maps {
 149                                 map0 {
 150                                         trip = <&cpu_alert0>;
 151                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 152                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 153                                 };
 154                         };
 155
 156                         trips {
 157                                 cpu_alert0: cpu_alert0 {
 158                                         /* milliCelsius */
 159                                         temperature = <75000>;
 160                                         hysteresis = <2000>;
 161                                         type = "passive";
 162                                 };
 163
 164                                 cpu_crit: cpu_crit {
 165                                         /* milliCelsius */
 166                                         temperature = <100000>;
 167                                         hysteresis = <2000>;
 168                                         type = "critical";
 169                                 };
 170                         };
 171                 };
 172         };
 173
 174         reserved-memory {
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 ranges;
 178
 179                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 180                 default-pool {
 181                         compatible = "shared-dma-pool";
 182                         size = <0x6000000>;
 183                         alloc-ranges = <0x4a000000 0x6000000>;
 184                         reusable;
 185                         linux,cma-default;
 186                 };
 187         };
 188
 189         timer {
 190                 compatible = "arm,armv7-timer";
 191                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 193                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 194                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 195         };
 196
 197         pmu {
 198                 compatible = "arm,cortex-a7-pmu";
 199                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 201         };
 202
 203         clocks {
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges;
 207
 208                 osc24M: clk-24M {
 209                         #clock-cells = <0>;
 210                         compatible = "fixed-clock";
 211                         clock-frequency = <24000000>;
 212                         clock-output-names = "osc24M";
 213                 };
 214
 215                 osc32k: clk-32k {
 216                         #clock-cells = <0>;
 217                         compatible = "fixed-clock";
 218                         clock-frequency = <32768>;
 219                         clock-output-names = "osc32k";
 220                 };
 221
 222                 /*
 223                  * The following two are dummy clocks, placeholders
 224                  * used in the gmac_tx clock. The gmac driver will
 225                  * choose one parent depending on the PHY interface
 226                  * mode, using clk_set_rate auto-reparenting.
 227                  *
 228                  * The actual TX clock rate is not controlled by the
 229                  * gmac_tx clock.
 230                  */
 231                 mii_phy_tx_clk: clk-mii-phy-tx {
 232                         #clock-cells = <0>;
 233                         compatible = "fixed-clock";
 234                         clock-frequency = <25000000>;
 235                         clock-output-names = "mii_phy_tx";
 236                 };
 237
 238                 gmac_int_tx_clk: clk-gmac-int-tx {
 239                         #clock-cells = <0>;
 240                         compatible = "fixed-clock";
 241                         clock-frequency = <125000000>;
 242                         clock-output-names = "gmac_int_tx";
 243                 };
 244
 245                 gmac_tx_clk: clk@1c20164 {
 246                         #clock-cells = <0>;
 247                         compatible = "allwinner,sun7i-a20-gmac-clk";
 248                         reg = <0x01c20164 0x4>;
 249                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 250                         clock-output-names = "gmac_tx";
 251                 };
 252         };
 253
 254
 255         de: display-engine {
 256                 compatible = "allwinner,sun7i-a20-display-engine";
 257                 allwinner,pipelines = <&fe0>, <&fe1>;
 258                 status = "disabled";
 259         };
 260
 261         soc {
 262                 compatible = "simple-bus";
 263                 #address-cells = <1>;
 264                 #size-cells = <1>;
 265                 ranges;
 266
 267                 system-control@1c00000 {
 268                         compatible = "allwinner,sun7i-a20-system-control",
 269                                      "allwinner,sun4i-a10-system-control";
 270                         reg = <0x01c00000 0x30>;
 271                         #address-cells = <1>;
 272                         #size-cells = <1>;
 273                         ranges;
 274
 275                         sram_a: sram@0 {
 276                                 compatible = "mmio-sram";
 277                                 reg = <0x00000000 0xc000>;
 278                                 #address-cells = <1>;
 279                                 #size-cells = <1>;
 280                                 ranges = <0 0x00000000 0xc000>;
 281
 282                                 emac_sram: sram-section@8000 {
 283                                         compatible = "allwinner,sun7i-a20-sram-a3-a4",
 284                                                      "allwinner,sun4i-a10-sram-a3-a4";
 285                                         reg = <0x8000 0x4000>;
 286                                         status = "disabled";
 287                                 };
 288                         };
 289
 290                         sram_d: sram@10000 {
 291                                 compatible = "mmio-sram";
 292                                 reg = <0x00010000 0x1000>;
 293                                 #address-cells = <1>;
 294                                 #size-cells = <1>;
 295                                 ranges = <0 0x00010000 0x1000>;
 296
 297                                 otg_sram: sram-section@0 {
 298                                         compatible = "allwinner,sun7i-a20-sram-d",
 299                                                      "allwinner,sun4i-a10-sram-d";
 300                                         reg = <0x0000 0x1000>;
 301                                         status = "disabled";
 302                                 };
 303                         };
 304
 305                         sram_c: sram@1d00000 {
 306                                 compatible = "mmio-sram";
 307                                 reg = <0x01d00000 0xd0000>;
 308                                 #address-cells = <1>;
 309                                 #size-cells = <1>;
 310                                 ranges = <0 0x01d00000 0xd0000>;
 311
 312                                 ve_sram: sram-section@0 {
 313                                         compatible = "allwinner,sun7i-a20-sram-c1",
 314                                                      "allwinner,sun4i-a10-sram-c1";
 315                                         reg = <0x000000 0x80000>;
 316                                 };
 317                         };
 318                 };
 319
 320                 nmi_intc: interrupt-controller@1c00030 {
 321                         compatible = "allwinner,sun7i-a20-sc-nmi";
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                         reg = <0x01c00030 0x0c>;
 325                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 326                 };
 327
 328                 dma: dma-controller@1c02000 {
 329                         compatible = "allwinner,sun4i-a10-dma";
 330                         reg = <0x01c02000 0x1000>;
 331                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&ccu CLK_AHB_DMA>;
 333                         #dma-cells = <2>;
 334                 };
 335
 336                 nfc: nand-controller@1c03000 {
 337                         compatible = "allwinner,sun4i-a10-nand";
 338                         reg = <0x01c03000 0x1000>;
 339                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 341                         clock-names = "ahb", "mod";
 342                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 343                         dma-names = "rxtx";
 344                         status = "disabled";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                 };
 348
 349                 spi0: spi@1c05000 {
 350                         compatible = "allwinner,sun4i-a10-spi";
 351                         reg = <0x01c05000 0x1000>;
 352                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 353                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 354                         clock-names = "ahb", "mod";
 355                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 356                                <&dma SUN4I_DMA_DEDICATED 26>;
 357                         dma-names = "rx", "tx";
 358                         status = "disabled";
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         num-cs = <4>;
 362                 };
 363
 364                 spi1: spi@1c06000 {
 365                         compatible = "allwinner,sun4i-a10-spi";
 366                         reg = <0x01c06000 0x1000>;
 367                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 369                         clock-names = "ahb", "mod";
 370                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 371                                <&dma SUN4I_DMA_DEDICATED 8>;
 372                         dma-names = "rx", "tx";
 373                         status = "disabled";
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         num-cs = <1>;
 377                 };
 378
 379                 csi0: csi@1c09000 {
 380                         compatible = "allwinner,sun7i-a20-csi0";
 381                         reg = <0x01c09000 0x1000>;
 382                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
 384                                  <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
 385                         clock-names = "bus", "mod", "isp", "ram";
 386                         resets = <&ccu RST_CSI0>;
 387                         status = "disabled";
 388                 };
 389
 390                 emac: ethernet@1c0b000 {
 391                         compatible = "allwinner,sun4i-a10-emac";
 392                         reg = <0x01c0b000 0x1000>;
 393                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&ccu CLK_AHB_EMAC>;
 395                         allwinner,sram = <&emac_sram 1>;
 396                         status = "disabled";
 397                 };
 398
 399                 mdio: mdio@1c0b080 {
 400                         compatible = "allwinner,sun4i-a10-mdio";
 401                         reg = <0x01c0b080 0x14>;
 402                         status = "disabled";
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                 };
 406
 407                 tcon0: lcd-controller@1c0c000 {
 408                         compatible = "allwinner,sun7i-a20-tcon";
 409                         reg = <0x01c0c000 0x1000>;
 410                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 411                         resets = <&ccu RST_TCON0>;
 412                         reset-names = "lcd";
 413                         clocks = <&ccu CLK_AHB_LCD0>,
 414                                  <&ccu CLK_TCON0_CH0>,
 415                                  <&ccu CLK_TCON0_CH1>;
 416                         clock-names = "ahb",
 417                                       "tcon-ch0",
 418                                       "tcon-ch1";
 419                         clock-output-names = "tcon0-pixel-clock";
 420                         #clock-cells = <0>;
 421                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 422
 423                         ports {
 424                                 #address-cells = <1>;
 425                                 #size-cells = <0>;
 426
 427                                 tcon0_in: port@0 {
 428                                         #address-cells = <1>;
 429                                         #size-cells = <0>;
 430                                         reg = <0>;
 431
 432                                         tcon0_in_be0: endpoint@0 {
 433                                                 reg = <0>;
 434                                                 remote-endpoint = <&be0_out_tcon0>;
 435                                         };
 436
 437                                         tcon0_in_be1: endpoint@1 {
 438                                                 reg = <1>;
 439                                                 remote-endpoint = <&be1_out_tcon0>;
 440                                         };
 441                                 };
 442
 443                                 tcon0_out: port@1 {
 444                                         #address-cells = <1>;
 445                                         #size-cells = <0>;
 446                                         reg = <1>;
 447
 448                                         tcon0_out_hdmi: endpoint@1 {
 449                                                 reg = <1>;
 450                                                 remote-endpoint = <&hdmi_in_tcon0>;
 451                                                 allwinner,tcon-channel = <1>;
 452                                         };
 453                                 };
 454                         };
 455                 };
 456
 457                 tcon1: lcd-controller@1c0d000 {
 458                         compatible = "allwinner,sun7i-a20-tcon";
 459                         reg = <0x01c0d000 0x1000>;
 460                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 461                         resets = <&ccu RST_TCON1>;
 462                         reset-names = "lcd";
 463                         clocks = <&ccu CLK_AHB_LCD1>,
 464                                  <&ccu CLK_TCON1_CH0>,
 465                                  <&ccu CLK_TCON1_CH1>;
 466                         clock-names = "ahb",
 467                                       "tcon-ch0",
 468                                       "tcon-ch1";
 469                         clock-output-names = "tcon1-pixel-clock";
 470                         #clock-cells = <0>;
 471                         dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 472
 473                         ports {
 474                                 #address-cells = <1>;
 475                                 #size-cells = <0>;
 476
 477                                 tcon1_in: port@0 {
 478                                         #address-cells = <1>;
 479                                         #size-cells = <0>;
 480                                         reg = <0>;
 481
 482                                         tcon1_in_be0: endpoint@0 {
 483                                                 reg = <0>;
 484                                                 remote-endpoint = <&be0_out_tcon1>;
 485                                         };
 486
 487                                         tcon1_in_be1: endpoint@1 {
 488                                                 reg = <1>;
 489                                                 remote-endpoint = <&be1_out_tcon1>;
 490                                         };
 491                                 };
 492
 493                                 tcon1_out: port@1 {
 494                                         #address-cells = <1>;
 495                                         #size-cells = <0>;
 496                                         reg = <1>;
 497
 498                                         tcon1_out_hdmi: endpoint@1 {
 499                                                 reg = <1>;
 500                                                 remote-endpoint = <&hdmi_in_tcon1>;
 501                                                 allwinner,tcon-channel = <1>;
 502                                         };
 503                                 };
 504                         };
 505                 };
 506
 507                 video-codec@1c0e000 {
 508                         compatible = "allwinner,sun7i-a20-video-engine";
 509                         reg = <0x01c0e000 0x1000>;
 510                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 511                                  <&ccu CLK_DRAM_VE>;
 512                         clock-names = "ahb", "mod", "ram";
 513                         resets = <&ccu RST_VE>;
 514                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 515                         allwinner,sram = <&ve_sram 1>;
 516                 };
 517
 518                 mmc0: mmc@1c0f000 {
 519                         compatible = "allwinner,sun7i-a20-mmc";
 520                         reg = <0x01c0f000 0x1000>;
 521                         clocks = <&ccu CLK_AHB_MMC0>,
 522                                  <&ccu CLK_MMC0>,
 523                                  <&ccu CLK_MMC0_OUTPUT>,
 524                                  <&ccu CLK_MMC0_SAMPLE>;
 525                         clock-names = "ahb",
 526                                       "mmc",
 527                                       "output",
 528                                       "sample";
 529                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 530                         pinctrl-names = "default";
 531                         pinctrl-0 = <&mmc0_pins>;
 532                         status = "disabled";
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                 };
 536
 537                 mmc1: mmc@1c10000 {
 538                         compatible = "allwinner,sun7i-a20-mmc";
 539                         reg = <0x01c10000 0x1000>;
 540                         clocks = <&ccu CLK_AHB_MMC1>,
 541                                  <&ccu CLK_MMC1>,
 542                                  <&ccu CLK_MMC1_OUTPUT>,
 543                                  <&ccu CLK_MMC1_SAMPLE>;
 544                         clock-names = "ahb",
 545                                       "mmc",
 546                                       "output",
 547                                       "sample";
 548                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 549                         status = "disabled";
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                 };
 553
 554                 mmc2: mmc@1c11000 {
 555                         compatible = "allwinner,sun7i-a20-mmc";
 556                         reg = <0x01c11000 0x1000>;
 557                         clocks = <&ccu CLK_AHB_MMC2>,
 558                                  <&ccu CLK_MMC2>,
 559                                  <&ccu CLK_MMC2_OUTPUT>,
 560                                  <&ccu CLK_MMC2_SAMPLE>;
 561                         clock-names = "ahb",
 562                                       "mmc",
 563                                       "output",
 564                                       "sample";
 565                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 566                         pinctrl-names = "default";
 567                         pinctrl-0 = <&mmc2_pins>;
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 mmc3: mmc@1c12000 {
 574                         compatible = "allwinner,sun7i-a20-mmc";
 575                         reg = <0x01c12000 0x1000>;
 576                         clocks = <&ccu CLK_AHB_MMC3>,
 577                                  <&ccu CLK_MMC3>,
 578                                  <&ccu CLK_MMC3_OUTPUT>,
 579                                  <&ccu CLK_MMC3_SAMPLE>;
 580                         clock-names = "ahb",
 581                                       "mmc",
 582                                       "output",
 583                                       "sample";
 584                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 585                         pinctrl-names = "default";
 586                         pinctrl-0 = <&mmc3_pins>;
 587                         status = "disabled";
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                 };
 591
 592                 usb_otg: usb@1c13000 {
 593                         compatible = "allwinner,sun4i-a10-musb";
 594                         reg = <0x01c13000 0x0400>;
 595                         clocks = <&ccu CLK_AHB_OTG>;
 596                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 597                         interrupt-names = "mc";
 598                         phys = <&usbphy 0>;
 599                         phy-names = "usb";
 600                         extcon = <&usbphy 0>;
 601                         allwinner,sram = <&otg_sram 1>;
 602                         dr_mode = "otg";
 603                         status = "disabled";
 604                 };
 605
 606                 usbphy: phy@1c13400 {
 607                         #phy-cells = <1>;
 608                         compatible = "allwinner,sun7i-a20-usb-phy";
 609                         reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 610                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 611                         clocks = <&ccu CLK_USB_PHY>;
 612                         clock-names = "usb_phy";
 613                         resets = <&ccu RST_USB_PHY0>,
 614                                  <&ccu RST_USB_PHY1>,
 615                                  <&ccu RST_USB_PHY2>;
 616                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 617                         status = "disabled";
 618                 };
 619
 620                 ehci0: usb@1c14000 {
 621                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 622                         reg = <0x01c14000 0x100>;
 623                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 624                         clocks = <&ccu CLK_AHB_EHCI0>;
 625                         phys = <&usbphy 1>;
 626                         phy-names = "usb";
 627                         status = "disabled";
 628                 };
 629
 630                 ohci0: usb@1c14400 {
 631                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 632                         reg = <0x01c14400 0x100>;
 633                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 634                         clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 635                         phys = <&usbphy 1>;
 636                         phy-names = "usb";
 637                         status = "disabled";
 638                 };
 639
 640                 crypto: crypto-engine@1c15000 {
 641                         compatible = "allwinner,sun7i-a20-crypto",
 642                                      "allwinner,sun4i-a10-crypto";
 643                         reg = <0x01c15000 0x1000>;
 644                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 646                         clock-names = "ahb", "mod";
 647                 };
 648
 649                 hdmi: hdmi@1c16000 {
 650                         compatible = "allwinner,sun7i-a20-hdmi",
 651                                      "allwinner,sun5i-a10s-hdmi";
 652                         reg = <0x01c16000 0x1000>;
 653                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 654                         clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 655                                  <&ccu CLK_PLL_VIDEO0_2X>,
 656                                  <&ccu CLK_PLL_VIDEO1_2X>;
 657                         clock-names = "ahb", "mod", "pll-0", "pll-1";
 658                         dmas = <&dma SUN4I_DMA_NORMAL 16>,
 659                                <&dma SUN4I_DMA_NORMAL 16>,
 660                                <&dma SUN4I_DMA_DEDICATED 24>;
 661                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 662                         status = "disabled";
 663
 664                         ports {
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667
 668                                 hdmi_in: port@0 {
 669                                         #address-cells = <1>;
 670                                         #size-cells = <0>;
 671                                         reg = <0>;
 672
 673                                         hdmi_in_tcon0: endpoint@0 {
 674                                                 reg = <0>;
 675                                                 remote-endpoint = <&tcon0_out_hdmi>;
 676                                         };
 677
 678                                         hdmi_in_tcon1: endpoint@1 {
 679                                                 reg = <1>;
 680                                                 remote-endpoint = <&tcon1_out_hdmi>;
 681                                         };
 682                                 };
 683
 684                                 hdmi_out: port@1 {
 685                                         reg = <1>;
 686                                 };
 687                         };
 688                 };
 689
 690                 spi2: spi@1c17000 {
 691                         compatible = "allwinner,sun4i-a10-spi";
 692                         reg = <0x01c17000 0x1000>;
 693                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 694                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 695                         clock-names = "ahb", "mod";
 696                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 697                                <&dma SUN4I_DMA_DEDICATED 28>;
 698                         dma-names = "rx", "tx";
 699                         status = "disabled";
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                         num-cs = <1>;
 703                 };
 704
 705                 ahci: sata@1c18000 {
 706                         compatible = "allwinner,sun4i-a10-ahci";
 707                         reg = <0x01c18000 0x1000>;
 708                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 710                         status = "disabled";
 711                 };
 712
 713                 ehci1: usb@1c1c000 {
 714                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 715                         reg = <0x01c1c000 0x100>;
 716                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 717                         clocks = <&ccu CLK_AHB_EHCI1>;
 718                         phys = <&usbphy 2>;
 719                         phy-names = "usb";
 720                         status = "disabled";
 721                 };
 722
 723                 ohci1: usb@1c1c400 {
 724                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 725                         reg = <0x01c1c400 0x100>;
 726                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 727                         clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 728                         phys = <&usbphy 2>;
 729                         phy-names = "usb";
 730                         status = "disabled";
 731                 };
 732
 733                 spi3: spi@1c1f000 {
 734                         compatible = "allwinner,sun4i-a10-spi";
 735                         reg = <0x01c1f000 0x1000>;
 736                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 737                         clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 738                         clock-names = "ahb", "mod";
 739                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 740                                <&dma SUN4I_DMA_DEDICATED 30>;
 741                         dma-names = "rx", "tx";
 742                         status = "disabled";
 743                         #address-cells = <1>;
 744                         #size-cells = <0>;
 745                         num-cs = <1>;
 746                 };
 747
 748                 ccu: clock@1c20000 {
 749                         compatible = "allwinner,sun7i-a20-ccu";
 750                         reg = <0x01c20000 0x400>;
 751                         clocks = <&osc24M>, <&osc32k>;
 752                         clock-names = "hosc", "losc";
 753                         #clock-cells = <1>;
 754                         #reset-cells = <1>;
 755                 };
 756
 757                 pio: pinctrl@1c20800 {
 758                         compatible = "allwinner,sun7i-a20-pinctrl";
 759                         reg = <0x01c20800 0x400>;
 760                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 762                         clock-names = "apb", "hosc", "losc";
 763                         gpio-controller;
 764                         interrupt-controller;
 765                         #interrupt-cells = <3>;
 766                         #gpio-cells = <3>;
 767
 768                         /omit-if-no-ref/
 769                         can_pa_pins: can-pa-pins {
 770                                 pins = "PA16", "PA17";
 771                                 function = "can";
 772                         };
 773
 774                         /omit-if-no-ref/
 775                         can_ph_pins: can-ph-pins {
 776                                 pins = "PH20", "PH21";
 777                                 function = "can";
 778                         };
 779
 780                         /omit-if-no-ref/
 781                         clk_out_a_pin: clk-out-a-pin {
 782                                 pins = "PI12";
 783                                 function = "clk_out_a";
 784                         };
 785
 786                         /omit-if-no-ref/
 787                         clk_out_b_pin: clk-out-b-pin {
 788                                 pins = "PI13";
 789                                 function = "clk_out_b";
 790                         };
 791
 792                         /omit-if-no-ref/
 793                         csi0_8bits_pins: csi-8bits-pins {
 794                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 795                                        "PE6", "PE7", "PE8", "PE9", "PE10",
 796                                        "PE11";
 797                                 function = "csi0";
 798                         };
 799
 800                         /omit-if-no-ref/
 801                         csi0_clk_pin: csi-clk-pin {
 802                                 pins = "PE1";
 803                                 function = "csi0";
 804                         };
 805
 806                         /omit-if-no-ref/
 807                         emac_pa_pins: emac-pa-pins {
 808                                 pins = "PA0", "PA1", "PA2",
 809                                        "PA3", "PA4", "PA5", "PA6",
 810                                        "PA7", "PA8", "PA9", "PA10",
 811                                        "PA11", "PA12", "PA13", "PA14",
 812                                        "PA15", "PA16";
 813                                 function = "emac";
 814                         };
 815
 816                         /omit-if-no-ref/
 817                         emac_ph_pins: emac-ph-pins {
 818                                 pins = "PH8", "PH9", "PH10", "PH11",
 819                                        "PH14", "PH15", "PH16", "PH17",
 820                                        "PH18", "PH19", "PH20", "PH21",
 821                                        "PH22", "PH23", "PH24", "PH25",
 822                                        "PH26";
 823                                 function = "emac";
 824                         };
 825
 826                         /omit-if-no-ref/
 827                         gmac_mii_pins: gmac-mii-pins {
 828                                 pins = "PA0", "PA1", "PA2",
 829                                        "PA3", "PA4", "PA5", "PA6",
 830                                        "PA7", "PA8", "PA9", "PA10",
 831                                        "PA11", "PA12", "PA13", "PA14",
 832                                        "PA15", "PA16";
 833                                 function = "gmac";
 834                         };
 835
 836                         /omit-if-no-ref/
 837                         gmac_rgmii_pins: gmac-rgmii-pins {
 838                                 pins = "PA0", "PA1", "PA2",
 839                                        "PA3", "PA4", "PA5", "PA6",
 840                                         "PA7", "PA8", "PA10",
 841                                        "PA11", "PA12", "PA13",
 842                                        "PA15", "PA16";
 843                                 function = "gmac";
 844                                 /*
 845                                  * data lines in RGMII mode use DDR mode
 846                                  * and need a higher signal drive strength
 847                                  */
 848                                 drive-strength = <40>;
 849                         };
 850
 851                         /omit-if-no-ref/
 852                         i2c0_pins: i2c0-pins {
 853                                 pins = "PB0", "PB1";
 854                                 function = "i2c0";
 855                         };
 856
 857                         /omit-if-no-ref/
 858                         i2c1_pins: i2c1-pins {
 859                                 pins = "PB18", "PB19";
 860                                 function = "i2c1";
 861                         };
 862
 863                         /omit-if-no-ref/
 864                         i2c2_pins: i2c2-pins {
 865                                 pins = "PB20", "PB21";
 866                                 function = "i2c2";
 867                         };
 868
 869                         /omit-if-no-ref/
 870                         i2c3_pins: i2c3-pins {
 871                                 pins = "PI0", "PI1";
 872                                 function = "i2c3";
 873                         };
 874
 875                         /omit-if-no-ref/
 876                         ir0_rx_pin: ir0-rx-pin {
 877                                 pins = "PB4";
 878                                 function = "ir0";
 879                         };
 880
 881                         /omit-if-no-ref/
 882                         ir0_tx_pin: ir0-tx-pin {
 883                                 pins = "PB3";
 884                                 function = "ir0";
 885                         };
 886
 887                         /omit-if-no-ref/
 888                         ir1_rx_pin: ir1-rx-pin {
 889                                 pins = "PB23";
 890                                 function = "ir1";
 891                         };
 892
 893                         /omit-if-no-ref/
 894                         ir1_tx_pin: ir1-tx-pin {
 895                                 pins = "PB22";
 896                                 function = "ir1";
 897                         };
 898
 899                         /omit-if-no-ref/
 900                         mmc0_pins: mmc0-pins {
 901                                 pins = "PF0", "PF1", "PF2",
 902                                        "PF3", "PF4", "PF5";
 903                                 function = "mmc0";
 904                                 drive-strength = <30>;
 905                                 bias-pull-up;
 906                         };
 907
 908                         /omit-if-no-ref/
 909                         mmc2_pins: mmc2-pins {
 910                                 pins = "PC6", "PC7", "PC8",
 911                                        "PC9", "PC10", "PC11";
 912                                 function = "mmc2";
 913                                 drive-strength = <30>;
 914                                 bias-pull-up;
 915                         };
 916
 917                         /omit-if-no-ref/
 918                         mmc3_pins: mmc3-pins {
 919                                 pins = "PI4", "PI5", "PI6",
 920                                        "PI7", "PI8", "PI9";
 921                                 function = "mmc3";
 922                                 drive-strength = <30>;
 923                                 bias-pull-up;
 924                         };
 925
 926                         /omit-if-no-ref/
 927                         ps2_0_pins: ps2-0-pins {
 928                                 pins = "PI20", "PI21";
 929                                 function = "ps2";
 930                         };
 931
 932                         /omit-if-no-ref/
 933                         ps2_1_ph_pins: ps2-1-ph-pins {
 934                                 pins = "PH12", "PH13";
 935                                 function = "ps2";
 936                         };
 937
 938                         /omit-if-no-ref/
 939                         pwm0_pin: pwm0-pin {
 940                                 pins = "PB2";
 941                                 function = "pwm";
 942                         };
 943
 944                         /omit-if-no-ref/
 945                         pwm1_pin: pwm1-pin {
 946                                 pins = "PI3";
 947                                 function = "pwm";
 948                         };
 949
 950                         /omit-if-no-ref/
 951                         spdif_tx_pin: spdif-tx-pin {
 952                                 pins = "PB13";
 953                                 function = "spdif";
 954                                 bias-pull-up;
 955                         };
 956
 957                         /omit-if-no-ref/
 958                         spi0_pi_pins: spi0-pi-pins {
 959                                 pins = "PI11", "PI12", "PI13";
 960                                 function = "spi0";
 961                         };
 962
 963                         /omit-if-no-ref/
 964                         spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 965                                 pins = "PI10";
 966                                 function = "spi0";
 967                         };
 968
 969                         /omit-if-no-ref/
 970                         spi0_cs1_pi_pin: spi0-cs1-pi-pin {
 971                                 pins = "PI14";
 972                                 function = "spi0";
 973                         };
 974
 975                         /omit-if-no-ref/
 976                         spi1_pi_pins: spi1-pi-pins {
 977                                 pins = "PI17", "PI18", "PI19";
 978                                 function = "spi1";
 979                         };
 980
 981                         /omit-if-no-ref/
 982                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 983                                 pins = "PI16";
 984                                 function = "spi1";
 985                         };
 986
 987                         /omit-if-no-ref/
 988                         spi2_pb_pins: spi2-pb-pins {
 989                                 pins = "PB15", "PB16", "PB17";
 990                                 function = "spi2";
 991                         };
 992
 993                         /omit-if-no-ref/
 994                         spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 995                                 pins = "PB14";
 996                                 function = "spi2";
 997                         };
 998
 999                         /omit-if-no-ref/
1000                         spi2_pc_pins: spi2-pc-pins {
1001                                 pins = "PC20", "PC21", "PC22";
1002                                 function = "spi2";
1003                         };
1004
1005                         /omit-if-no-ref/
1006                         spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1007                                 pins = "PC19";
1008                                 function = "spi2";
1009                         };
1010
1011                         /omit-if-no-ref/
1012                         uart0_pb_pins: uart0-pb-pins {
1013                                 pins = "PB22", "PB23";
1014                                 function = "uart0";
1015                         };
1016
1017                         /omit-if-no-ref/
1018                         uart0_pf_pins: uart0-pf-pins {
1019                                 pins = "PF2", "PF4";
1020                                 function = "uart0";
1021                         };
1022
1023                         /omit-if-no-ref/
1024                         uart1_pa_pins: uart1-pa-pins {
1025                                 pins = "PA10", "PA11";
1026                                 function = "uart1";
1027                         };
1028
1029                         /omit-if-no-ref/
1030                         uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1031                                 pins = "PA12", "PA13";
1032                                 function = "uart1";
1033                         };
1034
1035                         /omit-if-no-ref/
1036                         uart2_pa_pins: uart2-pa-pins {
1037                                 pins = "PA2", "PA3";
1038                                 function = "uart2";
1039                         };
1040
1041                         /omit-if-no-ref/
1042                         uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1043                                 pins = "PA0", "PA1";
1044                                 function = "uart2";
1045                         };
1046
1047                         /omit-if-no-ref/
1048                         uart2_pi_pins: uart2-pi-pins {
1049                                 pins = "PI18", "PI19";
1050                                 function = "uart2";
1051                         };
1052
1053                         /omit-if-no-ref/
1054                         uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1055                                 pins = "PI16", "PI17";
1056                                 function = "uart2";
1057                         };
1058
1059                         /omit-if-no-ref/
1060                         uart3_pg_pins: uart3-pg-pins {
1061                                 pins = "PG6", "PG7";
1062                                 function = "uart3";
1063                         };
1064
1065                         /omit-if-no-ref/
1066                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1067                                 pins = "PG8", "PG9";
1068                                 function = "uart3";
1069                         };
1070
1071                         /omit-if-no-ref/
1072                         uart3_ph_pins: uart3-ph-pins {
1073                                 pins = "PH0", "PH1";
1074                                 function = "uart3";
1075                         };
1076
1077                         /omit-if-no-ref/
1078                         uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1079                                 pins = "PH2", "PH3";
1080                                 function = "uart3";
1081                         };
1082
1083                         /omit-if-no-ref/
1084                         uart4_pg_pins: uart4-pg-pins {
1085                                 pins = "PG10", "PG11";
1086                                 function = "uart4";
1087                         };
1088
1089                         /omit-if-no-ref/
1090                         uart4_ph_pins: uart4-ph-pins {
1091                                 pins = "PH4", "PH5";
1092                                 function = "uart4";
1093                         };
1094
1095                         /omit-if-no-ref/
1096                         uart5_ph_pins: uart5-ph-pins {
1097                                 pins = "PH6", "PH7";
1098                                 function = "uart5";
1099                         };
1100
1101                         /omit-if-no-ref/
1102                         uart5_pi_pins: uart5-pi-pins {
1103                                 pins = "PI10", "PI11";
1104                                 function = "uart5";
1105                         };
1106
1107                         /omit-if-no-ref/
1108                         uart6_pa_pins: uart6-pa-pins {
1109                                 pins = "PA12", "PA13";
1110                                 function = "uart6";
1111                         };
1112
1113                         /omit-if-no-ref/
1114                         uart6_pi_pins: uart6-pi-pins {
1115                                 pins = "PI12", "PI13";
1116                                 function = "uart6";
1117                         };
1118
1119                         /omit-if-no-ref/
1120                         uart7_pa_pins: uart7-pa-pins {
1121                                 pins = "PA14", "PA15";
1122                                 function = "uart7";
1123                         };
1124
1125                         /omit-if-no-ref/
1126                         uart7_pi_pins: uart7-pi-pins {
1127                                 pins = "PI20", "PI21";
1128                                 function = "uart7";
1129                         };
1130                 };
1131
1132                 timer@1c20c00 {
1133                         compatible = "allwinner,sun4i-a10-timer";
1134                         reg = <0x01c20c00 0x90>;
1135                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1136                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1137                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1138                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1139                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1140                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1141                         clocks = <&osc24M>;
1142                 };
1143
1144                 wdt: watchdog@1c20c90 {
1145                         compatible = "allwinner,sun4i-a10-wdt";
1146                         reg = <0x01c20c90 0x10>;
1147                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1148                         clocks = <&osc24M>;
1149                 };
1150
1151                 rtc: rtc@1c20d00 {
1152                         compatible = "allwinner,sun7i-a20-rtc";
1153                         reg = <0x01c20d00 0x20>;
1154                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1155                 };
1156
1157                 pwm: pwm@1c20e00 {
1158                         compatible = "allwinner,sun7i-a20-pwm";
1159                         reg = <0x01c20e00 0xc>;
1160                         clocks = <&osc24M>;
1161                         #pwm-cells = <3>;
1162                         status = "disabled";
1163                 };
1164
1165                 spdif: spdif@1c21000 {
1166                         #sound-dai-cells = <0>;
1167                         compatible = "allwinner,sun4i-a10-spdif";
1168                         reg = <0x01c21000 0x400>;
1169                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1170                         clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1171                         clock-names = "apb", "spdif";
1172                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1173                                <&dma SUN4I_DMA_NORMAL 2>;
1174                         dma-names = "rx", "tx";
1175                         status = "disabled";
1176                 };
1177
1178                 ir0: ir@1c21800 {
1179                         compatible = "allwinner,sun4i-a10-ir";
1180                         clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1181                         clock-names = "apb", "ir";
1182                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1183                         reg = <0x01c21800 0x40>;
1184                         status = "disabled";
1185                 };
1186
1187                 ir1: ir@1c21c00 {
1188                         compatible = "allwinner,sun4i-a10-ir";
1189                         clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1190                         clock-names = "apb", "ir";
1191                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1192                         reg = <0x01c21c00 0x40>;
1193                         status = "disabled";
1194                 };
1195
1196                 i2s1: i2s@1c22000 {
1197                         #sound-dai-cells = <0>;
1198                         compatible = "allwinner,sun4i-a10-i2s";
1199                         reg = <0x01c22000 0x400>;
1200                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1201                         clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1202                         clock-names = "apb", "mod";
1203                         dmas = <&dma SUN4I_DMA_NORMAL 4>,
1204                                <&dma SUN4I_DMA_NORMAL 4>;
1205                         dma-names = "rx", "tx";
1206                         status = "disabled";
1207                 };
1208
1209                 i2s0: i2s@1c22400 {
1210                         #sound-dai-cells = <0>;
1211                         compatible = "allwinner,sun4i-a10-i2s";
1212                         reg = <0x01c22400 0x400>;
1213                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1214                         clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1215                         clock-names = "apb", "mod";
1216                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
1217                                <&dma SUN4I_DMA_NORMAL 3>;
1218                         dma-names = "rx", "tx";
1219                         status = "disabled";
1220                 };
1221
1222                 lradc: lradc@1c22800 {
1223                         compatible = "allwinner,sun4i-a10-lradc-keys";
1224                         reg = <0x01c22800 0x100>;
1225                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1226                         status = "disabled";
1227                 };
1228
1229                 codec: codec@1c22c00 {
1230                         #sound-dai-cells = <0>;
1231                         compatible = "allwinner,sun7i-a20-codec";
1232                         reg = <0x01c22c00 0x40>;
1233                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1234                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1235                         clock-names = "apb", "codec";
1236                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1237                                <&dma SUN4I_DMA_NORMAL 19>;
1238                         dma-names = "rx", "tx";
1239                         status = "disabled";
1240                 };
1241
1242                 sid: eeprom@1c23800 {
1243                         compatible = "allwinner,sun7i-a20-sid";
1244                         reg = <0x01c23800 0x200>;
1245                 };
1246
1247                 i2s2: i2s@1c24400 {
1248                         #sound-dai-cells = <0>;
1249                         compatible = "allwinner,sun4i-a10-i2s";
1250                         reg = <0x01c24400 0x400>;
1251                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1252                         clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1253                         clock-names = "apb", "mod";
1254                         dmas = <&dma SUN4I_DMA_NORMAL 6>,
1255                                <&dma SUN4I_DMA_NORMAL 6>;
1256                         dma-names = "rx", "tx";
1257                         status = "disabled";
1258                 };
1259
1260                 rtp: rtp@1c25000 {
1261                         compatible = "allwinner,sun5i-a13-ts";
1262                         reg = <0x01c25000 0x100>;
1263                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1264                         #thermal-sensor-cells = <0>;
1265                 };
1266
1267                 uart0: serial@1c28000 {
1268                         compatible = "snps,dw-apb-uart";
1269                         reg = <0x01c28000 0x400>;
1270                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1271                         reg-shift = <2>;
1272                         reg-io-width = <4>;
1273                         clocks = <&ccu CLK_APB1_UART0>;
1274                         status = "disabled";
1275                 };
1276
1277                 uart1: serial@1c28400 {
1278                         compatible = "snps,dw-apb-uart";
1279                         reg = <0x01c28400 0x400>;
1280                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1281                         reg-shift = <2>;
1282                         reg-io-width = <4>;
1283                         clocks = <&ccu CLK_APB1_UART1>;
1284                         status = "disabled";
1285                 };
1286
1287                 uart2: serial@1c28800 {
1288                         compatible = "snps,dw-apb-uart";
1289                         reg = <0x01c28800 0x400>;
1290                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1291                         reg-shift = <2>;
1292                         reg-io-width = <4>;
1293                         clocks = <&ccu CLK_APB1_UART2>;
1294                         status = "disabled";
1295                 };
1296
1297                 uart3: serial@1c28c00 {
1298                         compatible = "snps,dw-apb-uart";
1299                         reg = <0x01c28c00 0x400>;
1300                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1301                         reg-shift = <2>;
1302                         reg-io-width = <4>;
1303                         clocks = <&ccu CLK_APB1_UART3>;
1304                         status = "disabled";
1305                 };
1306
1307                 uart4: serial@1c29000 {
1308                         compatible = "snps,dw-apb-uart";
1309                         reg = <0x01c29000 0x400>;
1310                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1311                         reg-shift = <2>;
1312                         reg-io-width = <4>;
1313                         clocks = <&ccu CLK_APB1_UART4>;
1314                         status = "disabled";
1315                 };
1316
1317                 uart5: serial@1c29400 {
1318                         compatible = "snps,dw-apb-uart";
1319                         reg = <0x01c29400 0x400>;
1320                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1321                         reg-shift = <2>;
1322                         reg-io-width = <4>;
1323                         clocks = <&ccu CLK_APB1_UART5>;
1324                         status = "disabled";
1325                 };
1326
1327                 uart6: serial@1c29800 {
1328                         compatible = "snps,dw-apb-uart";
1329                         reg = <0x01c29800 0x400>;
1330                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1331                         reg-shift = <2>;
1332                         reg-io-width = <4>;
1333                         clocks = <&ccu CLK_APB1_UART6>;
1334                         status = "disabled";
1335                 };
1336
1337                 uart7: serial@1c29c00 {
1338                         compatible = "snps,dw-apb-uart";
1339                         reg = <0x01c29c00 0x400>;
1340                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1341                         reg-shift = <2>;
1342                         reg-io-width = <4>;
1343                         clocks = <&ccu CLK_APB1_UART7>;
1344                         status = "disabled";
1345                 };
1346
1347                 ps20: ps2@1c2a000 {
1348                         compatible = "allwinner,sun4i-a10-ps2";
1349                         reg = <0x01c2a000 0x400>;
1350                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1351                         clocks = <&ccu CLK_APB1_PS20>;
1352                         status = "disabled";
1353                 };
1354
1355                 ps21: ps2@1c2a400 {
1356                         compatible = "allwinner,sun4i-a10-ps2";
1357                         reg = <0x01c2a400 0x400>;
1358                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1359                         clocks = <&ccu CLK_APB1_PS21>;
1360                         status = "disabled";
1361                 };
1362
1363                 i2c0: i2c@1c2ac00 {
1364                         compatible = "allwinner,sun7i-a20-i2c",
1365                                      "allwinner,sun4i-a10-i2c";
1366                         reg = <0x01c2ac00 0x400>;
1367                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1368                         clocks = <&ccu CLK_APB1_I2C0>;
1369                         pinctrl-names = "default";
1370                         pinctrl-0 = <&i2c0_pins>;
1371                         status = "disabled";
1372                         #address-cells = <1>;
1373                         #size-cells = <0>;
1374                 };
1375
1376                 i2c1: i2c@1c2b000 {
1377                         compatible = "allwinner,sun7i-a20-i2c",
1378                                      "allwinner,sun4i-a10-i2c";
1379                         reg = <0x01c2b000 0x400>;
1380                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1381                         clocks = <&ccu CLK_APB1_I2C1>;
1382                         pinctrl-names = "default";
1383                         pinctrl-0 = <&i2c1_pins>;
1384                         status = "disabled";
1385                         #address-cells = <1>;
1386                         #size-cells = <0>;
1387                 };
1388
1389                 i2c2: i2c@1c2b400 {
1390                         compatible = "allwinner,sun7i-a20-i2c",
1391                                      "allwinner,sun4i-a10-i2c";
1392                         reg = <0x01c2b400 0x400>;
1393                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1394                         clocks = <&ccu CLK_APB1_I2C2>;
1395                         pinctrl-names = "default";
1396                         pinctrl-0 = <&i2c2_pins>;
1397                         status = "disabled";
1398                         #address-cells = <1>;
1399                         #size-cells = <0>;
1400                 };
1401
1402                 i2c3: i2c@1c2b800 {
1403                         compatible = "allwinner,sun7i-a20-i2c",
1404                                      "allwinner,sun4i-a10-i2c";
1405                         reg = <0x01c2b800 0x400>;
1406                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1407                         clocks = <&ccu CLK_APB1_I2C3>;
1408                         pinctrl-names = "default";
1409                         pinctrl-0 = <&i2c3_pins>;
1410                         status = "disabled";
1411                         #address-cells = <1>;
1412                         #size-cells = <0>;
1413                 };
1414
1415                 can0: can@1c2bc00 {
1416                         compatible = "allwinner,sun7i-a20-can",
1417                                      "allwinner,sun4i-a10-can";
1418                         reg = <0x01c2bc00 0x400>;
1419                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1420                         clocks = <&ccu CLK_APB1_CAN>;
1421                         status = "disabled";
1422                 };
1423
1424                 i2c4: i2c@1c2c000 {
1425                         compatible = "allwinner,sun7i-a20-i2c",
1426                                      "allwinner,sun4i-a10-i2c";
1427                         reg = <0x01c2c000 0x400>;
1428                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1429                         clocks = <&ccu CLK_APB1_I2C4>;
1430                         status = "disabled";
1431                         #address-cells = <1>;
1432                         #size-cells = <0>;
1433                 };
1434
1435                 mali: gpu@1c40000 {
1436                         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1437                         reg = <0x01c40000 0x10000>;
1438                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1439                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1440                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1441                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1442                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1443                                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1444                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1445                         interrupt-names = "gp",
1446                                           "gpmmu",
1447                                           "pp0",
1448                                           "ppmmu0",
1449                                           "pp1",
1450                                           "ppmmu1",
1451                                           "pmu";
1452                         clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1453                         clock-names = "bus", "core";
1454                         resets = <&ccu RST_GPU>;
1455
1456                         assigned-clocks = <&ccu CLK_GPU>;
1457                         assigned-clock-rates = <384000000>;
1458                 };
1459
1460                 gmac: ethernet@1c50000 {
1461                         compatible = "allwinner,sun7i-a20-gmac";
1462                         reg = <0x01c50000 0x10000>;
1463                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1464                         interrupt-names = "macirq";
1465                         clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1466                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1467                         snps,pbl = <2>;
1468                         snps,fixed-burst;
1469                         snps,force_sf_dma_mode;
1470                         status = "disabled";
1471
1472                         gmac_mdio: mdio {
1473                                 compatible = "snps,dwmac-mdio";
1474                                 #address-cells = <1>;
1475                                 #size-cells = <0>;
1476                         };
1477                 };
1478
1479                 hstimer@1c60000 {
1480                         compatible = "allwinner,sun7i-a20-hstimer";
1481                         reg = <0x01c60000 0x1000>;
1482                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1483                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1484                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1485                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1486                         clocks = <&ccu CLK_AHB_HSTIMER>;
1487                 };
1488
1489                 gic: interrupt-controller@1c81000 {
1490                         compatible = "arm,gic-400";
1491                         reg = <0x01c81000 0x1000>,
1492                               <0x01c82000 0x2000>,
1493                               <0x01c84000 0x2000>,
1494                               <0x01c86000 0x2000>;
1495                         interrupt-controller;
1496                         #interrupt-cells = <3>;
1497                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1498                 };
1499
1500                 fe0: display-frontend@1e00000 {
1501                         compatible = "allwinner,sun7i-a20-display-frontend";
1502                         reg = <0x01e00000 0x20000>;
1503                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1504                         clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1505                                  <&ccu CLK_DRAM_DE_FE0>;
1506                         clock-names = "ahb", "mod",
1507                                       "ram";
1508                         resets = <&ccu RST_DE_FE0>;
1509
1510                         ports {
1511                                 #address-cells = <1>;
1512                                 #size-cells = <0>;
1513
1514                                 fe0_out: port@1 {
1515                                         #address-cells = <1>;
1516                                         #size-cells = <0>;
1517                                         reg = <1>;
1518
1519                                         fe0_out_be0: endpoint@0 {
1520                                                 reg = <0>;
1521                                                 remote-endpoint = <&be0_in_fe0>;
1522                                         };
1523
1524                                         fe0_out_be1: endpoint@1 {
1525                                                 reg = <1>;
1526                                                 remote-endpoint = <&be1_in_fe0>;
1527                                         };
1528                                 };
1529                         };
1530                 };
1531
1532                 fe1: display-frontend@1e20000 {
1533                         compatible = "allwinner,sun7i-a20-display-frontend";
1534                         reg = <0x01e20000 0x20000>;
1535                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1536                         clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1537                                  <&ccu CLK_DRAM_DE_FE1>;
1538                         clock-names = "ahb", "mod",
1539                                       "ram";
1540                         resets = <&ccu RST_DE_FE1>;
1541
1542                         ports {
1543                                 #address-cells = <1>;
1544                                 #size-cells = <0>;
1545
1546                                 fe1_out: port@1 {
1547                                         #address-cells = <1>;
1548                                         #size-cells = <0>;
1549                                         reg = <1>;
1550
1551                                         fe1_out_be0: endpoint@0 {
1552                                                 reg = <0>;
1553                                                 remote-endpoint = <&be0_in_fe1>;
1554                                         };
1555
1556                                         fe1_out_be1: endpoint@1 {
1557                                                 reg = <1>;
1558                                                 remote-endpoint = <&be1_in_fe1>;
1559                                         };
1560                                 };
1561                         };
1562                 };
1563
1564                 be1: display-backend@1e40000 {
1565                         compatible = "allwinner,sun7i-a20-display-backend";
1566                         reg = <0x01e40000 0x10000>;
1567                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1568                         clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1569                                  <&ccu CLK_DRAM_DE_BE1>;
1570                         clock-names = "ahb", "mod",
1571                                       "ram";
1572                         resets = <&ccu RST_DE_BE1>;
1573
1574                         ports {
1575                                 #address-cells = <1>;
1576                                 #size-cells = <0>;
1577
1578                                 be1_in: port@0 {
1579                                         #address-cells = <1>;
1580                                         #size-cells = <0>;
1581                                         reg = <0>;
1582
1583                                         be1_in_fe0: endpoint@0 {
1584                                                 reg = <0>;
1585                                                 remote-endpoint = <&fe0_out_be1>;
1586                                         };
1587
1588                                         be1_in_fe1: endpoint@1 {
1589                                                 reg = <1>;
1590                                                 remote-endpoint = <&fe1_out_be1>;
1591                                         };
1592                                 };
1593
1594                                 be1_out: port@1 {
1595                                         #address-cells = <1>;
1596                                         #size-cells = <0>;
1597                                         reg = <1>;
1598
1599                                         be1_out_tcon0: endpoint@0 {
1600                                                 reg = <0>;
1601                                                 remote-endpoint = <&tcon0_in_be1>;
1602                                         };
1603
1604                                         be1_out_tcon1: endpoint@1 {
1605                                                 reg = <1>;
1606                                                 remote-endpoint = <&tcon1_in_be1>;
1607                                         };
1608                                 };
1609                         };
1610                 };
1611
1612                 be0: display-backend@1e60000 {
1613                         compatible = "allwinner,sun7i-a20-display-backend";
1614                         reg = <0x01e60000 0x10000>;
1615                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1616                         clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1617                                  <&ccu CLK_DRAM_DE_BE0>;
1618                         clock-names = "ahb", "mod",
1619                                       "ram";
1620                         resets = <&ccu RST_DE_BE0>;
1621
1622                         ports {
1623                                 #address-cells = <1>;
1624                                 #size-cells = <0>;
1625
1626                                 be0_in: port@0 {
1627                                         #address-cells = <1>;
1628                                         #size-cells = <0>;
1629                                         reg = <0>;
1630
1631                                         be0_in_fe0: endpoint@0 {
1632                                                 reg = <0>;
1633                                                 remote-endpoint = <&fe0_out_be0>;
1634                                         };
1635
1636                                         be0_in_fe1: endpoint@1 {
1637                                                 reg = <1>;
1638                                                 remote-endpoint = <&fe1_out_be0>;
1639                                         };
1640                                 };
1641
1642                                 be0_out: port@1 {
1643                                         #address-cells = <1>;
1644                                         #size-cells = <0>;
1645                                         reg = <1>;
1646
1647                                         be0_out_tcon0: endpoint@0 {
1648                                                 reg = <0>;
1649                                                 remote-endpoint = <&tcon0_in_be0>;
1650                                         };
1651
1652                                         be0_out_tcon1: endpoint@1 {
1653                                                 reg = <1>;
1654                                                 remote-endpoint = <&tcon1_in_be0>;
1655                                         };
1656                                 };
1657                         };
1658                 };
1659         };
1660 };