arch/arm/boot/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 simplefb_hdmi: framebuffer-lcd0-hdmi {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  70                                  <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  71                                  <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  72                                  <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 simplefb_lcd: framebuffer-lcd0 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  81                                  <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  82                                  <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  83                         status = "disabled";
  84                 };
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  93                 clock-frequency = <24000000>;
  94                 arm,cpu-registers-not-fw-configured;
  95         };
  96
  97         cpus {
  98                 enable-method = "allwinner,sun6i-a31";
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 1008000 1200000
 111                                 864000  1200000
 112                                 720000  1100000
 113                                 480000  1000000
 114                                 >;
 115                         #cooling-cells = <2>;
 116                 };
 117
 118                 cpu1: cpu@1 {
 119                         compatible = "arm,cortex-a7";
 120                         device_type = "cpu";
 121                         reg = <1>;
 122                         clocks = <&ccu CLK_CPU>;
 123                         clock-latency = <244144>; /* 8 32k periods */
 124                         operating-points = <
 125                                 /* kHz    uV */
 126                                 1008000 1200000
 127                                 864000  1200000
 128                                 720000  1100000
 129                                 480000  1000000
 130                                 >;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu2: cpu@2 {
 135                         compatible = "arm,cortex-a7";
 136                         device_type = "cpu";
 137                         reg = <2>;
 138                         clocks = <&ccu CLK_CPU>;
 139                         clock-latency = <244144>; /* 8 32k periods */
 140                         operating-points = <
 141                                 /* kHz    uV */
 142                                 1008000 1200000
 143                                 864000  1200000
 144                                 720000  1100000
 145                                 480000  1000000
 146                                 >;
 147                         #cooling-cells = <2>;
 148                 };
 149
 150                 cpu3: cpu@3 {
 151                         compatible = "arm,cortex-a7";
 152                         device_type = "cpu";
 153                         reg = <3>;
 154                         clocks = <&ccu CLK_CPU>;
 155                         clock-latency = <244144>; /* 8 32k periods */
 156                         operating-points = <
 157                                 /* kHz    uV */
 158                                 1008000 1200000
 159                                 864000  1200000
 160                                 720000  1100000
 161                                 480000  1000000
 162                                 >;
 163                         #cooling-cells = <2>;
 164                 };
 165         };
 166
 167         thermal-zones {
 168                 cpu_thermal {
 169                         /* milliseconds */
 170                         polling-delay-passive = <250>;
 171                         polling-delay = <1000>;
 172                         thermal-sensors = <&rtp>;
 173
 174                         cooling-maps {
 175                                 map0 {
 176                                         trip = <&cpu_alert0>;
 177                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 178                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 179                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 180                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182                         };
 183
 184                         trips {
 185                                 cpu_alert0: cpu_alert0 {
 186                                         /* milliCelsius */
 187                                         temperature = <70000>;
 188                                         hysteresis = <2000>;
 189                                         type = "passive";
 190                                 };
 191
 192                                 cpu_crit: cpu_crit {
 193                                         /* milliCelsius */
 194                                         temperature = <100000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199                 };
 200         };
 201
 202         pmu {
 203                 compatible = "arm,cortex-a7-pmu";
 204                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 208         };
 209
 210         clocks {
 211                 #address-cells = <1>;
 212                 #size-cells = <1>;
 213                 ranges;
 214
 215                 osc24M: clk-24M {
 216                         #clock-cells = <0>;
 217                         compatible = "fixed-clock";
 218                         clock-frequency = <24000000>;
 219                         clock-accuracy = <50000>;
 220                         clock-output-names = "osc24M";
 221                 };
 222
 223                 osc32k: clk-32k {
 224                         #clock-cells = <0>;
 225                         compatible = "fixed-clock";
 226                         clock-frequency = <32768>;
 227                         clock-accuracy = <50000>;
 228                         clock-output-names = "ext_osc32k";
 229                 };
 230
 231                 /*
 232                  * The following two are dummy clocks, placeholders
 233                  * used in the gmac_tx clock. The gmac driver will
 234                  * choose one parent depending on the PHY interface
 235                  * mode, using clk_set_rate auto-reparenting.
 236                  *
 237                  * The actual TX clock rate is not controlled by the
 238                  * gmac_tx clock.
 239                  */
 240                 mii_phy_tx_clk: clk-mii-phy-tx {
 241                         #clock-cells = <0>;
 242                         compatible = "fixed-clock";
 243                         clock-frequency = <25000000>;
 244                         clock-output-names = "mii_phy_tx";
 245                 };
 246
 247                 gmac_int_tx_clk: clk-gmac-int-tx {
 248                         #clock-cells = <0>;
 249                         compatible = "fixed-clock";
 250                         clock-frequency = <125000000>;
 251                         clock-output-names = "gmac_int_tx";
 252                 };
 253
 254                 gmac_tx_clk: clk@1c200d0 {
 255                         #clock-cells = <0>;
 256                         compatible = "allwinner,sun7i-a20-gmac-clk";
 257                         reg = <0x01c200d0 0x4>;
 258                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 259                         clock-output-names = "gmac_tx";
 260                 };
 261         };
 262
 263         de: display-engine {
 264                 compatible = "allwinner,sun6i-a31-display-engine";
 265                 allwinner,pipelines = <&fe0>, <&fe1>;
 266                 status = "disabled";
 267         };
 268
 269         soc {
 270                 compatible = "simple-bus";
 271                 #address-cells = <1>;
 272                 #size-cells = <1>;
 273                 ranges;
 274
 275                 dma: dma-controller@1c02000 {
 276                         compatible = "allwinner,sun6i-a31-dma";
 277                         reg = <0x01c02000 0x1000>;
 278                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&ccu CLK_AHB1_DMA>;
 280                         resets = <&ccu RST_AHB1_DMA>;
 281                         #dma-cells = <1>;
 282                 };
 283
 284                 tcon0: lcd-controller@1c0c000 {
 285                         compatible = "allwinner,sun6i-a31-tcon";
 286                         reg = <0x01c0c000 0x1000>;
 287                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 288                         resets = <&ccu RST_AHB1_LCD0>;
 289                         reset-names = "lcd";
 290                         clocks = <&ccu CLK_AHB1_LCD0>,
 291                                  <&ccu CLK_LCD0_CH0>,
 292                                  <&ccu CLK_LCD0_CH1>;
 293                         clock-names = "ahb",
 294                                       "tcon-ch0",
 295                                       "tcon-ch1";
 296                         clock-output-names = "tcon0-pixel-clock";
 297                         #clock-cells = <0>;
 298
 299                         ports {
 300                                 #address-cells = <1>;
 301                                 #size-cells = <0>;
 302
 303                                 tcon0_in: port@0 {
 304                                         #address-cells = <1>;
 305                                         #size-cells = <0>;
 306                                         reg = <0>;
 307
 308                                         tcon0_in_drc0: endpoint@0 {
 309                                                 reg = <0>;
 310                                                 remote-endpoint = <&drc0_out_tcon0>;
 311                                         };
 312
 313                                         tcon0_in_drc1: endpoint@1 {
 314                                                 reg = <1>;
 315                                                 remote-endpoint = <&drc1_out_tcon0>;
 316                                         };
 317                                 };
 318
 319                                 tcon0_out: port@1 {
 320                                         #address-cells = <1>;
 321                                         #size-cells = <0>;
 322                                         reg = <1>;
 323
 324                                         tcon0_out_hdmi: endpoint@1 {
 325                                                 reg = <1>;
 326                                                 remote-endpoint = <&hdmi_in_tcon0>;
 327                                                 allwinner,tcon-channel = <1>;
 328                                         };
 329                                 };
 330                         };
 331                 };
 332
 333                 tcon1: lcd-controller@1c0d000 {
 334                         compatible = "allwinner,sun6i-a31-tcon";
 335                         reg = <0x01c0d000 0x1000>;
 336                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 337                         resets = <&ccu RST_AHB1_LCD1>;
 338                         reset-names = "lcd";
 339                         clocks = <&ccu CLK_AHB1_LCD1>,
 340                                  <&ccu CLK_LCD1_CH0>,
 341                                  <&ccu CLK_LCD1_CH1>;
 342                         clock-names = "ahb",
 343                                       "tcon-ch0",
 344                                       "tcon-ch1";
 345                         clock-output-names = "tcon1-pixel-clock";
 346                         #clock-cells = <0>;
 347
 348                         ports {
 349                                 #address-cells = <1>;
 350                                 #size-cells = <0>;
 351
 352                                 tcon1_in: port@0 {
 353                                         #address-cells = <1>;
 354                                         #size-cells = <0>;
 355                                         reg = <0>;
 356
 357                                         tcon1_in_drc0: endpoint@0 {
 358                                                 reg = <0>;
 359                                                 remote-endpoint = <&drc0_out_tcon1>;
 360                                         };
 361
 362                                         tcon1_in_drc1: endpoint@1 {
 363                                                 reg = <1>;
 364                                                 remote-endpoint = <&drc1_out_tcon1>;
 365                                         };
 366                                 };
 367
 368                                 tcon1_out: port@1 {
 369                                         #address-cells = <1>;
 370                                         #size-cells = <0>;
 371                                         reg = <1>;
 372
 373                                         tcon1_out_hdmi: endpoint@1 {
 374                                                 reg = <1>;
 375                                                 remote-endpoint = <&hdmi_in_tcon1>;
 376                                                 allwinner,tcon-channel = <1>;
 377                                         };
 378                                 };
 379                         };
 380                 };
 381
 382                 mmc0: mmc@1c0f000 {
 383                         compatible = "allwinner,sun7i-a20-mmc";
 384                         reg = <0x01c0f000 0x1000>;
 385                         clocks = <&ccu CLK_AHB1_MMC0>,
 386                                  <&ccu CLK_MMC0>,
 387                                  <&ccu CLK_MMC0_OUTPUT>,
 388                                  <&ccu CLK_MMC0_SAMPLE>;
 389                         clock-names = "ahb",
 390                                       "mmc",
 391                                       "output",
 392                                       "sample";
 393                         resets = <&ccu RST_AHB1_MMC0>;
 394                         reset-names = "ahb";
 395                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 396                         pinctrl-names = "default";
 397                         pinctrl-0 = <&mmc0_pins>;
 398                         status = "disabled";
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                 };
 402
 403                 mmc1: mmc@1c10000 {
 404                         compatible = "allwinner,sun7i-a20-mmc";
 405                         reg = <0x01c10000 0x1000>;
 406                         clocks = <&ccu CLK_AHB1_MMC1>,
 407                                  <&ccu CLK_MMC1>,
 408                                  <&ccu CLK_MMC1_OUTPUT>,
 409                                  <&ccu CLK_MMC1_SAMPLE>;
 410                         clock-names = "ahb",
 411                                       "mmc",
 412                                       "output",
 413                                       "sample";
 414                         resets = <&ccu RST_AHB1_MMC1>;
 415                         reset-names = "ahb";
 416                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 417                         pinctrl-names = "default";
 418                         pinctrl-0 = <&mmc1_pins>;
 419                         status = "disabled";
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                 };
 423
 424                 mmc2: mmc@1c11000 {
 425                         compatible = "allwinner,sun7i-a20-mmc";
 426                         reg = <0x01c11000 0x1000>;
 427                         clocks = <&ccu CLK_AHB1_MMC2>,
 428                                  <&ccu CLK_MMC2>,
 429                                  <&ccu CLK_MMC2_OUTPUT>,
 430                                  <&ccu CLK_MMC2_SAMPLE>;
 431                         clock-names = "ahb",
 432                                       "mmc",
 433                                       "output",
 434                                       "sample";
 435                         resets = <&ccu RST_AHB1_MMC2>;
 436                         reset-names = "ahb";
 437                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 438                         status = "disabled";
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                 };
 442
 443                 mmc3: mmc@1c12000 {
 444                         compatible = "allwinner,sun7i-a20-mmc";
 445                         reg = <0x01c12000 0x1000>;
 446                         clocks = <&ccu CLK_AHB1_MMC3>,
 447                                  <&ccu CLK_MMC3>,
 448                                  <&ccu CLK_MMC3_OUTPUT>,
 449                                  <&ccu CLK_MMC3_SAMPLE>;
 450                         clock-names = "ahb",
 451                                       "mmc",
 452                                       "output",
 453                                       "sample";
 454                         resets = <&ccu RST_AHB1_MMC3>;
 455                         reset-names = "ahb";
 456                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 457                         status = "disabled";
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                 };
 461
 462                 hdmi: hdmi@1c16000 {
 463                         compatible = "allwinner,sun6i-a31-hdmi";
 464                         reg = <0x01c16000 0x1000>;
 465                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 466                         clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
 467                                  <&ccu CLK_HDMI_DDC>,
 468                                  <&ccu CLK_PLL_VIDEO0_2X>,
 469                                  <&ccu CLK_PLL_VIDEO1_2X>;
 470                         clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
 471                         resets = <&ccu RST_AHB1_HDMI>;
 472                         reset-names = "ahb";
 473                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 474                         dmas = <&dma 13>, <&dma 13>, <&dma 14>;
 475                         status = "disabled";
 476
 477                         ports {
 478                                 #address-cells = <1>;
 479                                 #size-cells = <0>;
 480
 481                                 hdmi_in: port@0 {
 482                                         #address-cells = <1>;
 483                                         #size-cells = <0>;
 484                                         reg = <0>;
 485
 486                                         hdmi_in_tcon0: endpoint@0 {
 487                                                 reg = <0>;
 488                                                 remote-endpoint = <&tcon0_out_hdmi>;
 489                                         };
 490
 491                                         hdmi_in_tcon1: endpoint@1 {
 492                                                 reg = <1>;
 493                                                 remote-endpoint = <&tcon1_out_hdmi>;
 494                                         };
 495                                 };
 496
 497                                 hdmi_out: port@1 {
 498                                         reg = <1>;
 499                                 };
 500                         };
 501                 };
 502
 503                 usb_otg: usb@1c19000 {
 504                         compatible = "allwinner,sun6i-a31-musb";
 505                         reg = <0x01c19000 0x0400>;
 506                         clocks = <&ccu CLK_AHB1_OTG>;
 507                         resets = <&ccu RST_AHB1_OTG>;
 508                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 509                         interrupt-names = "mc";
 510                         phys = <&usbphy 0>;
 511                         phy-names = "usb";
 512                         extcon = <&usbphy 0>;
 513                         dr_mode = "otg";
 514                         status = "disabled";
 515                 };
 516
 517                 usbphy: phy@1c19400 {
 518                         compatible = "allwinner,sun6i-a31-usb-phy";
 519                         reg = <0x01c19400 0x10>,
 520                               <0x01c1a800 0x4>,
 521                               <0x01c1b800 0x4>;
 522                         reg-names = "phy_ctrl",
 523                                     "pmu1",
 524                                     "pmu2";
 525                         clocks = <&ccu CLK_USB_PHY0>,
 526                                  <&ccu CLK_USB_PHY1>,
 527                                  <&ccu CLK_USB_PHY2>;
 528                         clock-names = "usb0_phy",
 529                                       "usb1_phy",
 530                                       "usb2_phy";
 531                         resets = <&ccu RST_USB_PHY0>,
 532                                  <&ccu RST_USB_PHY1>,
 533                                  <&ccu RST_USB_PHY2>;
 534                         reset-names = "usb0_reset",
 535                                       "usb1_reset",
 536                                       "usb2_reset";
 537                         status = "disabled";
 538                         #phy-cells = <1>;
 539                 };
 540
 541                 ehci0: usb@1c1a000 {
 542                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 543                         reg = <0x01c1a000 0x100>;
 544                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 545                         clocks = <&ccu CLK_AHB1_EHCI0>;
 546                         resets = <&ccu RST_AHB1_EHCI0>;
 547                         phys = <&usbphy 1>;
 548                         phy-names = "usb";
 549                         status = "disabled";
 550                 };
 551
 552                 ohci0: usb@1c1a400 {
 553                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 554                         reg = <0x01c1a400 0x100>;
 555                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
 557                         resets = <&ccu RST_AHB1_OHCI0>;
 558                         phys = <&usbphy 1>;
 559                         phy-names = "usb";
 560                         status = "disabled";
 561                 };
 562
 563                 ehci1: usb@1c1b000 {
 564                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 565                         reg = <0x01c1b000 0x100>;
 566                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&ccu CLK_AHB1_EHCI1>;
 568                         resets = <&ccu RST_AHB1_EHCI1>;
 569                         phys = <&usbphy 2>;
 570                         phy-names = "usb";
 571                         status = "disabled";
 572                 };
 573
 574                 ohci1: usb@1c1b400 {
 575                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 576                         reg = <0x01c1b400 0x100>;
 577                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
 579                         resets = <&ccu RST_AHB1_OHCI1>;
 580                         phys = <&usbphy 2>;
 581                         phy-names = "usb";
 582                         status = "disabled";
 583                 };
 584
 585                 ohci2: usb@1c1c400 {
 586                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 587                         reg = <0x01c1c400 0x100>;
 588                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 589                         clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
 590                         resets = <&ccu RST_AHB1_OHCI2>;
 591                         status = "disabled";
 592                 };
 593
 594                 ccu: clock@1c20000 {
 595                         compatible = "allwinner,sun6i-a31-ccu";
 596                         reg = <0x01c20000 0x400>;
 597                         clocks = <&osc24M>, <&rtc 0>;
 598                         clock-names = "hosc", "losc";
 599                         #clock-cells = <1>;
 600                         #reset-cells = <1>;
 601                 };
 602
 603                 pio: pinctrl@1c20800 {
 604                         compatible = "allwinner,sun6i-a31-pinctrl";
 605                         reg = <0x01c20800 0x400>;
 606                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 607                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 608                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 610                         clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
 611                         clock-names = "apb", "hosc", "losc";
 612                         gpio-controller;
 613                         interrupt-controller;
 614                         #interrupt-cells = <3>;
 615                         #gpio-cells = <3>;
 616
 617                         gmac_gmii_pins: gmac-gmii-pins {
 618                                 pins = "PA0", "PA1", "PA2", "PA3",
 619                                                 "PA4", "PA5", "PA6", "PA7",
 620                                                 "PA8", "PA9", "PA10", "PA11",
 621                                                 "PA12", "PA13", "PA14", "PA15",
 622                                                 "PA16", "PA17", "PA18", "PA19",
 623                                                 "PA20", "PA21", "PA22", "PA23",
 624                                                 "PA24", "PA25", "PA26", "PA27";
 625                                 function = "gmac";
 626                                 /*
 627                                  * data lines in GMII mode run at 125MHz and
 628                                  * might need a higher signal drive strength
 629                                  */
 630                                 drive-strength = <30>;
 631                         };
 632
 633                         gmac_mii_pins: gmac-mii-pins {
 634                                 pins = "PA0", "PA1", "PA2", "PA3",
 635                                                 "PA8", "PA9", "PA11",
 636                                                 "PA12", "PA13", "PA14", "PA19",
 637                                                 "PA20", "PA21", "PA22", "PA23",
 638                                                 "PA24", "PA26", "PA27";
 639                                 function = "gmac";
 640                         };
 641
 642                         gmac_rgmii_pins: gmac-rgmii-pins {
 643                                 pins = "PA0", "PA1", "PA2", "PA3",
 644                                                 "PA9", "PA10", "PA11",
 645                                                 "PA12", "PA13", "PA14", "PA19",
 646                                                 "PA20", "PA25", "PA26", "PA27";
 647                                 function = "gmac";
 648                                 /*
 649                                  * data lines in RGMII mode use DDR mode
 650                                  * and need a higher signal drive strength
 651                                  */
 652                                 drive-strength = <40>;
 653                         };
 654
 655                         i2c0_pins: i2c0-pins {
 656                                 pins = "PH14", "PH15";
 657                                 function = "i2c0";
 658                         };
 659
 660                         i2c1_pins: i2c1-pins {
 661                                 pins = "PH16", "PH17";
 662                                 function = "i2c1";
 663                         };
 664
 665                         i2c2_pins: i2c2-pins {
 666                                 pins = "PH18", "PH19";
 667                                 function = "i2c2";
 668                         };
 669
 670                         lcd0_rgb888_pins: lcd0-rgb888-pins {
 671                                 pins = "PD0", "PD1", "PD2", "PD3",
 672                                                  "PD4", "PD5", "PD6", "PD7",
 673                                                  "PD8", "PD9", "PD10", "PD11",
 674                                                  "PD12", "PD13", "PD14", "PD15",
 675                                                  "PD16", "PD17", "PD18", "PD19",
 676                                                  "PD20", "PD21", "PD22", "PD23",
 677                                                  "PD24", "PD25", "PD26", "PD27";
 678                                 function = "lcd0";
 679                         };
 680
 681                         mmc0_pins: mmc0-pins {
 682                                 pins = "PF0", "PF1", "PF2",
 683                                                  "PF3", "PF4", "PF5";
 684                                 function = "mmc0";
 685                                 drive-strength = <30>;
 686                                 bias-pull-up;
 687                         };
 688
 689                         mmc1_pins: mmc1-pins {
 690                                 pins = "PG0", "PG1", "PG2", "PG3",
 691                                                  "PG4", "PG5";
 692                                 function = "mmc1";
 693                                 drive-strength = <30>;
 694                                 bias-pull-up;
 695                         };
 696
 697                         mmc2_4bit_pins: mmc2-4bit-pins {
 698                                 pins = "PC6", "PC7", "PC8", "PC9",
 699                                                  "PC10", "PC11";
 700                                 function = "mmc2";
 701                                 drive-strength = <30>;
 702                                 bias-pull-up;
 703                         };
 704
 705                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 706                                 pins = "PC6", "PC7", "PC8", "PC9",
 707                                                  "PC10", "PC11", "PC12",
 708                                                  "PC13", "PC14", "PC15",
 709                                                  "PC24";
 710                                 function = "mmc2";
 711                                 drive-strength = <30>;
 712                                 bias-pull-up;
 713                         };
 714
 715                         mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
 716                                 pins = "PC6", "PC7", "PC8", "PC9",
 717                                                  "PC10", "PC11", "PC12",
 718                                                  "PC13", "PC14", "PC15",
 719                                                  "PC24";
 720                                 function = "mmc3";
 721                                 drive-strength = <40>;
 722                                 bias-pull-up;
 723                         };
 724
 725                         spdif_tx_pin: spdif-tx-pin {
 726                                 pins = "PH28";
 727                                 function = "spdif";
 728                         };
 729
 730                         uart0_ph_pins: uart0-ph-pins {
 731                                 pins = "PH20", "PH21";
 732                                 function = "uart0";
 733                         };
 734                 };
 735
 736                 timer@1c20c00 {
 737                         compatible = "allwinner,sun4i-a10-timer";
 738                         reg = <0x01c20c00 0xa0>;
 739                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 740                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 745                         clocks = <&osc24M>;
 746                 };
 747
 748                 wdt1: watchdog@1c20ca0 {
 749                         compatible = "allwinner,sun6i-a31-wdt";
 750                         reg = <0x01c20ca0 0x20>;
 751                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&osc24M>;
 753                 };
 754
 755                 spdif: spdif@1c21000 {
 756                         #sound-dai-cells = <0>;
 757                         compatible = "allwinner,sun6i-a31-spdif";
 758                         reg = <0x01c21000 0x400>;
 759                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 760                         clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
 761                         resets = <&ccu RST_APB1_SPDIF>;
 762                         clock-names = "apb", "spdif";
 763                         dmas = <&dma 2>, <&dma 2>;
 764                         dma-names = "rx", "tx";
 765                         status = "disabled";
 766                 };
 767
 768                 i2s0: i2s@1c22000 {
 769                         #sound-dai-cells = <0>;
 770                         compatible = "allwinner,sun6i-a31-i2s";
 771                         reg = <0x01c22000 0x400>;
 772                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 773                         clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
 774                         resets = <&ccu RST_APB1_DAUDIO0>;
 775                         clock-names = "apb", "mod";
 776                         dmas = <&dma 3>, <&dma 3>;
 777                         dma-names = "rx", "tx";
 778                         status = "disabled";
 779                 };
 780
 781                 i2s1: i2s@1c22400 {
 782                         #sound-dai-cells = <0>;
 783                         compatible = "allwinner,sun6i-a31-i2s";
 784                         reg = <0x01c22400 0x400>;
 785                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 786                         clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
 787                         resets = <&ccu RST_APB1_DAUDIO1>;
 788                         clock-names = "apb", "mod";
 789                         dmas = <&dma 4>, <&dma 4>;
 790                         dma-names = "rx", "tx";
 791                         status = "disabled";
 792                 };
 793
 794                 lradc: lradc@1c22800 {
 795                         compatible = "allwinner,sun4i-a10-lradc-keys";
 796                         reg = <0x01c22800 0x100>;
 797                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 798                         status = "disabled";
 799                 };
 800
 801                 rtp: rtp@1c25000 {
 802                         compatible = "allwinner,sun6i-a31-ts";
 803                         reg = <0x01c25000 0x100>;
 804                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 805                         #thermal-sensor-cells = <0>;
 806                 };
 807
 808                 uart0: serial@1c28000 {
 809                         compatible = "snps,dw-apb-uart";
 810                         reg = <0x01c28000 0x400>;
 811                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 812                         reg-shift = <2>;
 813                         reg-io-width = <4>;
 814                         clocks = <&ccu CLK_APB2_UART0>;
 815                         resets = <&ccu RST_APB2_UART0>;
 816                         dmas = <&dma 6>, <&dma 6>;
 817                         dma-names = "rx", "tx";
 818                         status = "disabled";
 819                 };
 820
 821                 uart1: serial@1c28400 {
 822                         compatible = "snps,dw-apb-uart";
 823                         reg = <0x01c28400 0x400>;
 824                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 825                         reg-shift = <2>;
 826                         reg-io-width = <4>;
 827                         clocks = <&ccu CLK_APB2_UART1>;
 828                         resets = <&ccu RST_APB2_UART1>;
 829                         dmas = <&dma 7>, <&dma 7>;
 830                         dma-names = "rx", "tx";
 831                         status = "disabled";
 832                 };
 833
 834                 uart2: serial@1c28800 {
 835                         compatible = "snps,dw-apb-uart";
 836                         reg = <0x01c28800 0x400>;
 837                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 838                         reg-shift = <2>;
 839                         reg-io-width = <4>;
 840                         clocks = <&ccu CLK_APB2_UART2>;
 841                         resets = <&ccu RST_APB2_UART2>;
 842                         dmas = <&dma 8>, <&dma 8>;
 843                         dma-names = "rx", "tx";
 844                         status = "disabled";
 845                 };
 846
 847                 uart3: serial@1c28c00 {
 848                         compatible = "snps,dw-apb-uart";
 849                         reg = <0x01c28c00 0x400>;
 850                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 851                         reg-shift = <2>;
 852                         reg-io-width = <4>;
 853                         clocks = <&ccu CLK_APB2_UART3>;
 854                         resets = <&ccu RST_APB2_UART3>;
 855                         dmas = <&dma 9>, <&dma 9>;
 856                         dma-names = "rx", "tx";
 857                         status = "disabled";
 858                 };
 859
 860                 uart4: serial@1c29000 {
 861                         compatible = "snps,dw-apb-uart";
 862                         reg = <0x01c29000 0x400>;
 863                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 864                         reg-shift = <2>;
 865                         reg-io-width = <4>;
 866                         clocks = <&ccu CLK_APB2_UART4>;
 867                         resets = <&ccu RST_APB2_UART4>;
 868                         dmas = <&dma 10>, <&dma 10>;
 869                         dma-names = "rx", "tx";
 870                         status = "disabled";
 871                 };
 872
 873                 uart5: serial@1c29400 {
 874                         compatible = "snps,dw-apb-uart";
 875                         reg = <0x01c29400 0x400>;
 876                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 877                         reg-shift = <2>;
 878                         reg-io-width = <4>;
 879                         clocks = <&ccu CLK_APB2_UART5>;
 880                         resets = <&ccu RST_APB2_UART5>;
 881                         dmas = <&dma 22>, <&dma 22>;
 882                         dma-names = "rx", "tx";
 883                         status = "disabled";
 884                 };
 885
 886                 i2c0: i2c@1c2ac00 {
 887                         compatible = "allwinner,sun6i-a31-i2c";
 888                         reg = <0x01c2ac00 0x400>;
 889                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 890                         clocks = <&ccu CLK_APB2_I2C0>;
 891                         resets = <&ccu RST_APB2_I2C0>;
 892                         pinctrl-names = "default";
 893                         pinctrl-0 = <&i2c0_pins>;
 894                         status = "disabled";
 895                         #address-cells = <1>;
 896                         #size-cells = <0>;
 897                 };
 898
 899                 i2c1: i2c@1c2b000 {
 900                         compatible = "allwinner,sun6i-a31-i2c";
 901                         reg = <0x01c2b000 0x400>;
 902                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 903                         clocks = <&ccu CLK_APB2_I2C1>;
 904                         resets = <&ccu RST_APB2_I2C1>;
 905                         pinctrl-names = "default";
 906                         pinctrl-0 = <&i2c1_pins>;
 907                         status = "disabled";
 908                         #address-cells = <1>;
 909                         #size-cells = <0>;
 910                 };
 911
 912                 i2c2: i2c@1c2b400 {
 913                         compatible = "allwinner,sun6i-a31-i2c";
 914                         reg = <0x01c2b400 0x400>;
 915                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 916                         clocks = <&ccu CLK_APB2_I2C2>;
 917                         resets = <&ccu RST_APB2_I2C2>;
 918                         pinctrl-names = "default";
 919                         pinctrl-0 = <&i2c2_pins>;
 920                         status = "disabled";
 921                         #address-cells = <1>;
 922                         #size-cells = <0>;
 923                 };
 924
 925                 i2c3: i2c@1c2b800 {
 926                         compatible = "allwinner,sun6i-a31-i2c";
 927                         reg = <0x01c2b800 0x400>;
 928                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 929                         clocks = <&ccu CLK_APB2_I2C3>;
 930                         resets = <&ccu RST_APB2_I2C3>;
 931                         status = "disabled";
 932                         #address-cells = <1>;
 933                         #size-cells = <0>;
 934                 };
 935
 936                 gmac: ethernet@1c30000 {
 937                         compatible = "allwinner,sun7i-a20-gmac";
 938                         reg = <0x01c30000 0x1054>;
 939                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 940                         interrupt-names = "macirq";
 941                         clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
 942                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 943                         resets = <&ccu RST_AHB1_EMAC>;
 944                         reset-names = "stmmaceth";
 945                         snps,pbl = <2>;
 946                         snps,fixed-burst;
 947                         snps,force_sf_dma_mode;
 948                         status = "disabled";
 949
 950                         mdio: mdio {
 951                                 compatible = "snps,dwmac-mdio";
 952                                 #address-cells = <1>;
 953                                 #size-cells = <0>;
 954                         };
 955                 };
 956
 957                 crypto: crypto-engine@1c15000 {
 958                         compatible = "allwinner,sun6i-a31-crypto",
 959                                      "allwinner,sun4i-a10-crypto";
 960                         reg = <0x01c15000 0x1000>;
 961                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 962                         clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
 963                         clock-names = "ahb", "mod";
 964                         resets = <&ccu RST_AHB1_SS>;
 965                         reset-names = "ahb";
 966                 };
 967
 968                 codec: codec@1c22c00 {
 969                         #sound-dai-cells = <0>;
 970                         compatible = "allwinner,sun6i-a31-codec";
 971                         reg = <0x01c22c00 0x400>;
 972                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 973                         clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
 974                         clock-names = "apb", "codec";
 975                         resets = <&ccu RST_APB1_CODEC>;
 976                         dmas = <&dma 15>, <&dma 15>;
 977                         dma-names = "rx", "tx";
 978                         status = "disabled";
 979                 };
 980
 981                 timer@1c60000 {
 982                         compatible = "allwinner,sun6i-a31-hstimer",
 983                                      "allwinner,sun7i-a20-hstimer";
 984                         reg = <0x01c60000 0x1000>;
 985                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 986                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 987                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 988                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 989                         clocks = <&ccu CLK_AHB1_HSTIMER>;
 990                         resets = <&ccu RST_AHB1_HSTIMER>;
 991                 };
 992
 993                 spi0: spi@1c68000 {
 994                         compatible = "allwinner,sun6i-a31-spi";
 995                         reg = <0x01c68000 0x1000>;
 996                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 997                         clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
 998                         clock-names = "ahb", "mod";
 999                         dmas = <&dma 23>, <&dma 23>;
1000                         dma-names = "rx", "tx";
1001                         resets = <&ccu RST_AHB1_SPI0>;
1002                         status = "disabled";
1003                         #address-cells = <1>;
1004                         #size-cells = <0>;
1005                 };
1006
1007                 spi1: spi@1c69000 {
1008                         compatible = "allwinner,sun6i-a31-spi";
1009                         reg = <0x01c69000 0x1000>;
1010                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1011                         clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1012                         clock-names = "ahb", "mod";
1013                         dmas = <&dma 24>, <&dma 24>;
1014                         dma-names = "rx", "tx";
1015                         resets = <&ccu RST_AHB1_SPI1>;
1016                         status = "disabled";
1017                         #address-cells = <1>;
1018                         #size-cells = <0>;
1019                 };
1020
1021                 spi2: spi@1c6a000 {
1022                         compatible = "allwinner,sun6i-a31-spi";
1023                         reg = <0x01c6a000 0x1000>;
1024                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1025                         clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1026                         clock-names = "ahb", "mod";
1027                         dmas = <&dma 25>, <&dma 25>;
1028                         dma-names = "rx", "tx";
1029                         resets = <&ccu RST_AHB1_SPI2>;
1030                         status = "disabled";
1031                         #address-cells = <1>;
1032                         #size-cells = <0>;
1033                 };
1034
1035                 spi3: spi@1c6b000 {
1036                         compatible = "allwinner,sun6i-a31-spi";
1037                         reg = <0x01c6b000 0x1000>;
1038                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1039                         clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1040                         clock-names = "ahb", "mod";
1041                         dmas = <&dma 26>, <&dma 26>;
1042                         dma-names = "rx", "tx";
1043                         resets = <&ccu RST_AHB1_SPI3>;
1044                         status = "disabled";
1045                         #address-cells = <1>;
1046                         #size-cells = <0>;
1047                 };
1048
1049                 gic: interrupt-controller@1c81000 {
1050                         compatible = "arm,gic-400";
1051                         reg = <0x01c81000 0x1000>,
1052                               <0x01c82000 0x2000>,
1053                               <0x01c84000 0x2000>,
1054                               <0x01c86000 0x2000>;
1055                         interrupt-controller;
1056                         #interrupt-cells = <3>;
1057                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1058                 };
1059
1060                 fe0: display-frontend@1e00000 {
1061                         compatible = "allwinner,sun6i-a31-display-frontend";
1062                         reg = <0x01e00000 0x20000>;
1063                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1064                         clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1065                                  <&ccu CLK_DRAM_FE0>;
1066                         clock-names = "ahb", "mod",
1067                                       "ram";
1068                         resets = <&ccu RST_AHB1_FE0>;
1069
1070                         ports {
1071                                 #address-cells = <1>;
1072                                 #size-cells = <0>;
1073
1074                                 fe0_out: port@1 {
1075                                         #address-cells = <1>;
1076                                         #size-cells = <0>;
1077                                         reg = <1>;
1078
1079                                         fe0_out_be0: endpoint@0 {
1080                                                 reg = <0>;
1081                                                 remote-endpoint = <&be0_in_fe0>;
1082                                         };
1083
1084                                         fe0_out_be1: endpoint@1 {
1085                                                 reg = <1>;
1086                                                 remote-endpoint = <&be1_in_fe0>;
1087                                         };
1088                                 };
1089                         };
1090                 };
1091
1092                 fe1: display-frontend@1e20000 {
1093                         compatible = "allwinner,sun6i-a31-display-frontend";
1094                         reg = <0x01e20000 0x20000>;
1095                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1096                         clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1097                                  <&ccu CLK_DRAM_FE1>;
1098                         clock-names = "ahb", "mod",
1099                                       "ram";
1100                         resets = <&ccu RST_AHB1_FE1>;
1101
1102                         ports {
1103                                 #address-cells = <1>;
1104                                 #size-cells = <0>;
1105
1106                                 fe1_out: port@1 {
1107                                         #address-cells = <1>;
1108                                         #size-cells = <0>;
1109                                         reg = <1>;
1110
1111                                         fe1_out_be0: endpoint@0 {
1112                                                 reg = <0>;
1113                                                 remote-endpoint = <&be0_in_fe1>;
1114                                         };
1115
1116                                         fe1_out_be1: endpoint@1 {
1117                                                 reg = <1>;
1118                                                 remote-endpoint = <&be1_in_fe1>;
1119                                         };
1120                                 };
1121                         };
1122                 };
1123
1124                 be1: display-backend@1e40000 {
1125                         compatible = "allwinner,sun6i-a31-display-backend";
1126                         reg = <0x01e40000 0x10000>;
1127                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1128                         clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1129                                  <&ccu CLK_DRAM_BE1>;
1130                         clock-names = "ahb", "mod",
1131                                       "ram";
1132                         resets = <&ccu RST_AHB1_BE1>;
1133
1134                         assigned-clocks = <&ccu CLK_BE1>;
1135                         assigned-clock-rates = <300000000>;
1136
1137                         ports {
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140
1141                                 be1_in: port@0 {
1142                                         #address-cells = <1>;
1143                                         #size-cells = <0>;
1144                                         reg = <0>;
1145
1146                                         be1_in_fe0: endpoint@0 {
1147                                                 reg = <0>;
1148                                                 remote-endpoint = <&fe0_out_be1>;
1149                                         };
1150
1151                                         be1_in_fe1: endpoint@1 {
1152                                                 reg = <1>;
1153                                                 remote-endpoint = <&fe1_out_be1>;
1154                                         };
1155                                 };
1156
1157                                 be1_out: port@1 {
1158                                         #address-cells = <1>;
1159                                         #size-cells = <0>;
1160                                         reg = <1>;
1161
1162                                         be1_out_drc1: endpoint@1 {
1163                                                 reg = <1>;
1164                                                 remote-endpoint = <&drc1_in_be1>;
1165                                         };
1166                                 };
1167                         };
1168                 };
1169
1170                 drc1: drc@1e50000 {
1171                         compatible = "allwinner,sun6i-a31-drc";
1172                         reg = <0x01e50000 0x10000>;
1173                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1174                         clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1175                                  <&ccu CLK_DRAM_DRC1>;
1176                         clock-names = "ahb", "mod",
1177                                       "ram";
1178                         resets = <&ccu RST_AHB1_DRC1>;
1179
1180                         assigned-clocks = <&ccu CLK_IEP_DRC1>;
1181                         assigned-clock-rates = <300000000>;
1182
1183                         ports {
1184                                 #address-cells = <1>;
1185                                 #size-cells = <0>;
1186
1187                                 drc1_in: port@0 {
1188                                         #address-cells = <1>;
1189                                         #size-cells = <0>;
1190                                         reg = <0>;
1191
1192                                         drc1_in_be1: endpoint@1 {
1193                                                 reg = <1>;
1194                                                 remote-endpoint = <&be1_out_drc1>;
1195                                         };
1196                                 };
1197
1198                                 drc1_out: port@1 {
1199                                         #address-cells = <1>;
1200                                         #size-cells = <0>;
1201                                         reg = <1>;
1202
1203                                         drc1_out_tcon0: endpoint@0 {
1204                                                 reg = <0>;
1205                                                 remote-endpoint = <&tcon0_in_drc1>;
1206                                         };
1207
1208                                         drc1_out_tcon1: endpoint@1 {
1209                                                 reg = <1>;
1210                                                 remote-endpoint = <&tcon1_in_drc1>;
1211                                         };
1212                                 };
1213                         };
1214                 };
1215
1216                 be0: display-backend@1e60000 {
1217                         compatible = "allwinner,sun6i-a31-display-backend";
1218                         reg = <0x01e60000 0x10000>;
1219                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1220                         clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1221                                  <&ccu CLK_DRAM_BE0>;
1222                         clock-names = "ahb", "mod",
1223                                       "ram";
1224                         resets = <&ccu RST_AHB1_BE0>;
1225
1226                         assigned-clocks = <&ccu CLK_BE0>;
1227                         assigned-clock-rates = <300000000>;
1228
1229                         ports {
1230                                 #address-cells = <1>;
1231                                 #size-cells = <0>;
1232
1233                                 be0_in: port@0 {
1234                                         #address-cells = <1>;
1235                                         #size-cells = <0>;
1236                                         reg = <0>;
1237
1238                                         be0_in_fe0: endpoint@0 {
1239                                                 reg = <0>;
1240                                                 remote-endpoint = <&fe0_out_be0>;
1241                                         };
1242
1243                                         be0_in_fe1: endpoint@1 {
1244                                                 reg = <1>;
1245                                                 remote-endpoint = <&fe1_out_be0>;
1246                                         };
1247                                 };
1248
1249                                 be0_out: port@1 {
1250                                         reg = <1>;
1251
1252                                         be0_out_drc0: endpoint {
1253                                                 remote-endpoint = <&drc0_in_be0>;
1254                                         };
1255                                 };
1256                         };
1257                 };
1258
1259                 drc0: drc@1e70000 {
1260                         compatible = "allwinner,sun6i-a31-drc";
1261                         reg = <0x01e70000 0x10000>;
1262                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1263                         clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1264                                  <&ccu CLK_DRAM_DRC0>;
1265                         clock-names = "ahb", "mod",
1266                                       "ram";
1267                         resets = <&ccu RST_AHB1_DRC0>;
1268
1269                         assigned-clocks = <&ccu CLK_IEP_DRC0>;
1270                         assigned-clock-rates = <300000000>;
1271
1272                         ports {
1273                                 #address-cells = <1>;
1274                                 #size-cells = <0>;
1275
1276                                 drc0_in: port@0 {
1277                                         reg = <0>;
1278
1279                                         drc0_in_be0: endpoint {
1280                                                 remote-endpoint = <&be0_out_drc0>;
1281                                         };
1282                                 };
1283
1284                                 drc0_out: port@1 {
1285                                         #address-cells = <1>;
1286                                         #size-cells = <0>;
1287                                         reg = <1>;
1288
1289                                         drc0_out_tcon0: endpoint@0 {
1290                                                 reg = <0>;
1291                                                 remote-endpoint = <&tcon0_in_drc0>;
1292                                         };
1293
1294                                         drc0_out_tcon1: endpoint@1 {
1295                                                 reg = <1>;
1296                                                 remote-endpoint = <&tcon1_in_drc0>;
1297                                         };
1298                                 };
1299                         };
1300                 };
1301
1302                 rtc: rtc@1f00000 {
1303                         #clock-cells = <1>;
1304                         compatible = "allwinner,sun6i-a31-rtc";
1305                         reg = <0x01f00000 0x54>;
1306                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1307                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1308                         clocks = <&osc32k>;
1309                         clock-output-names = "osc32k";
1310                 };
1311
1312                 nmi_intc: interrupt-controller@1f00c00 {
1313                         compatible = "allwinner,sun6i-a31-r-intc";
1314                         interrupt-controller;
1315                         #interrupt-cells = <2>;
1316                         reg = <0x01f00c00 0x400>;
1317                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1318                 };
1319
1320                 prcm@1f01400 {
1321                         compatible = "allwinner,sun6i-a31-prcm";
1322                         reg = <0x01f01400 0x200>;
1323
1324                         ar100: ar100_clk {
1325                                 compatible = "allwinner,sun6i-a31-ar100-clk";
1326                                 #clock-cells = <0>;
1327                                 clocks = <&rtc 0>, <&osc24M>,
1328                                          <&ccu CLK_PLL_PERIPH>,
1329                                          <&ccu CLK_PLL_PERIPH>;
1330                                 clock-output-names = "ar100";
1331                         };
1332
1333                         ahb0: ahb0_clk {
1334                                 compatible = "fixed-factor-clock";
1335                                 #clock-cells = <0>;
1336                                 clock-div = <1>;
1337                                 clock-mult = <1>;
1338                                 clocks = <&ar100>;
1339                                 clock-output-names = "ahb0";
1340                         };
1341
1342                         apb0: apb0_clk {
1343                                 compatible = "allwinner,sun6i-a31-apb0-clk";
1344                                 #clock-cells = <0>;
1345                                 clocks = <&ahb0>;
1346                                 clock-output-names = "apb0";
1347                         };
1348
1349                         apb0_gates: apb0_gates_clk {
1350                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1351                                 #clock-cells = <1>;
1352                                 clocks = <&apb0>;
1353                                 clock-output-names = "apb0_pio", "apb0_ir",
1354                                                 "apb0_timer", "apb0_p2wi",
1355                                                 "apb0_uart", "apb0_1wire",
1356                                                 "apb0_i2c";
1357                         };
1358
1359                         ir_clk: ir_clk {
1360                                 #clock-cells = <0>;
1361                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1362                                 clocks = <&rtc 0>, <&osc24M>;
1363                                 clock-output-names = "ir";
1364                         };
1365
1366                         apb0_rst: apb0_rst {
1367                                 compatible = "allwinner,sun6i-a31-clock-reset";
1368                                 #reset-cells = <1>;
1369                         };
1370                 };
1371
1372                 cpucfg@1f01c00 {
1373                         compatible = "allwinner,sun6i-a31-cpuconfig";
1374                         reg = <0x01f01c00 0x300>;
1375                 };
1376
1377                 ir: ir@1f02000 {
1378                         compatible = "allwinner,sun6i-a31-ir";
1379                         clocks = <&apb0_gates 1>, <&ir_clk>;
1380                         clock-names = "apb", "ir";
1381                         resets = <&apb0_rst 1>;
1382                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1383                         reg = <0x01f02000 0x40>;
1384                         status = "disabled";
1385                 };
1386
1387                 r_pio: pinctrl@1f02c00 {
1388                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1389                         reg = <0x01f02c00 0x400>;
1390                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1391                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1392                         clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
1393                         clock-names = "apb", "hosc", "losc";
1394                         resets = <&apb0_rst 0>;
1395                         gpio-controller;
1396                         interrupt-controller;
1397                         #interrupt-cells = <3>;
1398                         #gpio-cells = <3>;
1399
1400                         s_ir_rx_pin: s-ir-rx-pin {
1401                                 pins = "PL4";
1402                                 function = "s_ir";
1403                         };
1404
1405                         s_p2wi_pins: s-p2wi-pins {
1406                                 pins = "PL0", "PL1";
1407                                 function = "s_p2wi";
1408                         };
1409                 };
1410
1411                 p2wi: i2c@1f03400 {
1412                         compatible = "allwinner,sun6i-a31-p2wi";
1413                         reg = <0x01f03400 0x400>;
1414                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415                         clocks = <&apb0_gates 3>;
1416                         clock-frequency = <100000>;
1417                         resets = <&apb0_rst 3>;
1418                         pinctrl-names = "default";
1419                         pinctrl-0 = <&s_p2wi_pins>;
1420                         status = "disabled";
1421                         #address-cells = <1>;
1422                         #size-cells = <0>;
1423                 };
1424         };
1425 };